BSDL Files Library for JTAG

The only free public library that contains thousands of BSDL (Boundary Scan Description Language) models to use with BScan/JTAG tools

BSDL model: R1QGA3636

	--**************************************************************************							
	--*	*** RENESAS R1QGA3636 BSDL Model ***						
	--*							
	--*	File Name:	R1QGA3636.BSDL					
	--*	Revision :	B0.1b					
	--*	Date     :	2010.07.27					
	--*	Model    :	BSDL					
	--*							
	--*	Company  :	Renesas Electronics Corp.					
	--*	Part No. :	R1QGA3636					
	--*							
	--*	Description:						
	--*		- Function of R1QGA3636					
	--*		    36M QDR-II+ (IO=SIO, Org=x36, BL=4, RL=2.0, ODT=No )					
	--*			(SIO: Separate I/O, 		CIO: Common I/O,		
	--*			 BL: Burst Length		RL: Read Latency,								
	--*			 ODT: On Die Termination)										
	--*		- Please refer to Datasheet of R1QGA3636											
	--*													
	--*	Version History:												
	--*		Rev.B0.0a: Added models for 36M QDR II+ and 144M QDR II/II+ series to Renesas QDR BSDL model series.											
	--*		Rev.B0.1a: Changed company name. (Renesas Technology -> Renesas Electronics)											
	--*		Rev.B0.1b: Updated comments and descriptions.											
	--*													
	--*													
	--*													
	--*		Copyright : (C) 2010 Renesas Electronics Corp. All rights reserved.											
	--*													
	--**************************************************************************													

	entity	R1QGA3636	is											

	generic (PHYSICAL_PIN_MAP : string := "FBGA");						

	port	(					
	 	K	:	in	bit;		
	 	K_n	:	in	bit;		
	 	SA	:	in	bit_vector(0 to	17	);
	 	R_n	:	in	bit;		
	 	W_n	:	in	bit;		
	 	BW0_n	:	in	bit;		
	 	BW1_n	:	in	bit;		
	 	BW2_n	:	in	bit;		
	 	BW3_n	:	in	bit;		
	 	ZQ	:	in	bit;		
	 	DOFF_n	:	in	bit;		
	 	CQ	:	buffer	bit;		
	 	CQ_n	:	buffer	bit;		
	 	D	:	in	bit_vector(0 to	35	);
	 	Q	:	inout	bit_vector(0 to	35	);
	 	QVLD	:	buffer	bit;		
	 	TCK	:	in	bit;		
	 	TMS	:	in	bit;		
	 	TDI	:	in	bit;		
	 	TDO	:	out	bit;		
	 	VSS	:	linkage	bit_vector(0 to	24	);
	 	VDD	:	linkage	bit_vector(0 to	9	);			
	 	VDDQ	:	linkage	bit_vector(0 to	15	);			
	 	VREF	:	linkage	bit_vector(0 to	1	);			
	 	NC	:	linkage	bit_vector(0 to	4	));			
										
		use STD_1149_1_2001.all;								

		attribute COMPONENT_CONFORMANCE of			R1QGA3636	: entity is "STD_1149_1_1993";				

		attribute PIN_MAP of			R1QGA3636	: entity is PHYSICAL_PIN_MAP;				

		constant FBGA:PIN_MAP_STRING:=								
										
	 	"	K	:	B6	 ,"& --	Positive Input Clock			
	 	"	K_n	:	A6	 ,"& --	Negative Input Clock			
	 	"	SA	:(	N6,P7,N7,R7,R8,P8,R9,A9,B8,C7,C5,B4,R3,R4,P4,P5,N5,R5	),"& --	Address			
	 	"	R_n	:	A8	 ,"& --	Read			
	 	"	W_n	:	A4	 ,"& --	Write			
	 	"	BW0_n	:	B7	 ,"& --	BYTE WRITE			
	 	"	BW1_n	:	A7	 ,"& --	BYTE WRITE			
	 	"	BW2_n	:	A5	 ,"& --	BYTE WRITE			
	 	"	BW3_n	:	B5	 ,"& --	BYTE WRITE			
	 	"	ZQ	:	H11	 ,"& --	Impedance Match			
	 	"	DOFF_n	:	H1	 ,"& --	DLL OFF			
	 	"	CQ	:	A11	 ,"& --	Positive Echo Clock			
	 	"	CQ_n	:	A1	 ,"& --	Negative Echo Clock			
	 	"	D	:(	P10,N11,M11,K10,J11,G11,E10,D11,C11,N10,M9,L9,J9,G10,F9,D10,C9,B9,B3,C3,D2,F3,G2,J3,L3,M3,N2,C1,D1,E2,G1,J1,K2,M1,N1,P2	),"& --				
	 	"	Q	:(	P11,M10,L11,K11,J10,F11,E11,C10,B11,P9,N9,L10,K9,G9,F10,E9,D9,B10,B2,D3,E3,F2,G3,K3,L2,N3,P3,B1,C2,E1,F1,J2,K1,L1,M2,P1	),"& --				
	 	"	QVLD	:	P6	 ,"& --	Q_valid			
	 	"	TCK	:	R2	 ,"& --	Test Clock			
	 	"	TMS	:	R10	 ,"& --	Test Mode Select			
	 	"	TDI	:	R11	 ,"& --	Test Data-In			
	 	"	TDO	:	R1	 ,"& --	Test Data-Out			
	 	"	VSS	:(	C4,C8,D4,D5,D6,D7,D8,E5,E6,E7,F6,G6,H6,J6,K6,L5,L6,L7,M4,M5,M6,M7,M8,N4,N8	),"& --				
	 	"	VDD	:(	F5,F7,G5,G7,H5,H7,J5,J7,K5,K7	),"& --				
	 	"	VDDQ	:(	E4,E8,F4,F8,G4,G8,H3,H4,H8,H9,J4,J8,K4,K8,L4,L8	),"& --				
	 	"	VREF	:(	H2,H10	),"& --	HSTL Input Reference Voltage			
	 	"	NC	:(	R6,A10,C6,A3,A2	)";				

		attribute TAP_SCAN_IN       of			TDI	: signal is true;				
		attribute TAP_SCAN_OUT      of			TDO	: signal is true;				
		attribute TAP_SCAN_MODE     of			TMS	: signal is true;	
		attribute TAP_SCAN_CLOCK    of			TCK	: signal is (10.0e6, BOTH);	

		attribute INSTRUCTION_LENGTH of			R1QGA3636	: entity is 3;	

		attribute INSTRUCTION_OPCODE of			R1QGA3636	: entity is	

		"	EXTEST	(000),	"&		
		"	IDCODE	(001),	"&		
		"	SAMPLEZ	(010),	"&		
		"	RESERV1	(011),	"&		
		"	SAMPLE	(100),	"& --Sample(-Preload)		
		"	RESERV2	(101),	"&		
		"	RESERV3	(110),	"&		
		"	BYPASS	(111)	";		

		attribute INSTRUCTION_CAPTURE of			R1QGA3636	: entity is "001";	

		attribute INSTRUCTION_PRIVATE of			R1QGA3636	: entity is "RESERV1, RESERV2, RESERV3";	

		attribute IDCODE_REGISTER of			R1QGA3636	: entity is	

			"000"		& --Reserved for version number		
			"00010011011101010"		& --Device ID		
			"01000100011"		& --RENASAS JEDEC ID		
			"1"		; --		

		attribute REGISTER_ACCESS of			R1QGA3636	: entity is "BOUNDARY (SAMPLEZ)";	

		attribute BOUNDARY_LENGTH of			R1QGA3636	: entity is 109;	

		attribute BOUNDARY_REGISTER of			R1QGA3636	: entity is	
								
		"0	(BC_4,	*,	internal,	X		),"&
		"1	(BC_9,	QVLD,	output2,	X		),"&
		"2	(BC_4,	SA(0),	input,	X		),"&
		"3	(BC_4,	SA(1),	input,	X		),"&
		"4	(BC_4,	SA(2),	input,	X		),"&
		"5	(BC_4,	SA(3),	input,	X		),"&
		"6	(BC_4,	SA(4),	input,	X		),"&
		"7	(BC_4,	SA(5),	input,	X		),"&
		"8	(BC_4,	SA(6),	input,	X		),"&
		"9	(BC_7,	Q(0),	bidir,	X,108,0,Z		),"&
		"10	(BC_4,	D(0),	input,	X		),"&
		"11	(BC_4,	D(9),	input,	X		),"&
		"12	(BC_7,	Q(9),	bidir,	X,108,0,Z		),"&
		"13	(BC_7,	Q(1),	bidir,	X,108,0,Z		),"&
		"14	(BC_4,	D(1),	input,	X		),"&
		"15	(BC_4,	D(10),	input,	X		),"&
		"16	(BC_7,	Q(10),	bidir,	X,108,0,Z		),"&
		"17	(BC_7,	Q(2),	bidir,	X,108,0,Z		),"&
		"18	(BC_4,	D(2),	input,	X		),"&
		"19	(BC_4,	D(11),	input,	X		),"&
		"20	(BC_7,	Q(11),	bidir,	X,108,0,Z		),"&
		"21	(BC_7,	Q(3),	bidir,	X,108,0,Z		),"&
		"22	(BC_4,	D(3),	input,	X		),"&
		"23	(BC_4,	D(12),	input,	X		),"&
		"24	(BC_7,	Q(12),	bidir,	X,108,0,Z		),"&
		"25	(BC_7,	Q(4),	bidir,	X,108,0,Z		),"&
		"26	(BC_4,	D(4),	input,	X		),"&
		"27	(BC_4,	ZQ,	input,	X		),"&
		"28	(BC_4,	D(13),	input,	X		),"&
		"29	(BC_7,	Q(13),	bidir,	X,108,0,Z		),"&
		"30	(BC_7,	Q(5),	bidir,	X,108,0,Z		),"&
		"31	(BC_4,	D(5),	input,	X		),"&
		"32	(BC_4,	D(14),	input,	X		),"&
		"33	(BC_7,	Q(14),	bidir,	X,108,0,Z		),"&
		"34	(BC_7,	Q(6),	bidir,	X,108,0,Z		),"&
		"35	(BC_4,	D(6),	input,	X		),"&
		"36	(BC_4,	D(15),	input,	X		),"&
		"37	(BC_7,	Q(15),	bidir,	X,108,0,Z		),"&
		"38	(BC_7,	Q(7),	bidir,	X,108,0,Z		),"&
		"39	(BC_4,	D(7),	input,	X		),"&
		"40	(BC_4,	D(16),	input,	X		),"&
		"41	(BC_7,	Q(16),	bidir,	X,108,0,Z		),"&
		"42	(BC_7,	Q(8),	bidir,	X,108,0,Z		),"&
		"43	(BC_4,	D(8),	input,	X		),"&
		"44	(BC_4,	D(17),	input,	X		),"&
		"45	(BC_7,	Q(17),	bidir,	X,108,0,Z		),"&
		"46	(BC_9,	CQ,	output2,	X		),"&
		"47	(BC_4,	*,	internal,	X		),"&
		"48	(BC_4,	SA(7),	input,	X		),"&
		"49	(BC_4,	SA(8),	input,	X		),"&
		"50	(BC_4,	SA(9),	input,	X		),"&
		"51	(BC_4,	*,	internal,	X		),"&
		"52	(BC_4,	R_n,	input,	X		),"&
		"53	(BC_4,	BW1_n,	input,	X		),"&
		"54	(BC_4,	BW0_n,	input,	X		),"&
		"55	(BC_4,	K,	input,	X		),"&
		"56	(BC_4,	K_n,	input,	X		),"&
		"57	(BC_4,	BW3_n,	input,	X		),"&
		"58	(BC_4,	BW2_n,	input,	X		),"&
		"59	(BC_4,	W_n,	input,	X		),"&
		"60	(BC_4,	SA(10),	input,	X		),"&
		"61	(BC_4,	SA(11),	input,	X		),"&
		"62	(BC_4,	*,	internal,	X		),"&
		"63	(BC_4,	*,	internal,	X		),"&
		"64	(BC_9,	CQ_n,	output2,	X		),"&
		"65	(BC_7,	Q(18),	bidir,	X,108,0,Z		),"&
		"66	(BC_4,	D(18),	input,	X		),"&
		"67	(BC_4,	D(27),	input,	X		),"&
		"68	(BC_7,	Q(27),	bidir,	X,108,0,Z		),"&
		"69	(BC_7,	Q(19),	bidir,	X,108,0,Z		),"&
		"70	(BC_4,	D(19),	input,	X		),"&
		"71	(BC_4,	D(28),	input,	X		),"&
		"72	(BC_7,	Q(28),	bidir,	X,108,0,Z		),"&
		"73	(BC_7,	Q(20),	bidir,	X,108,0,Z		),"&
		"74	(BC_4,	D(20),	input,	X		),"&
		"75	(BC_4,	D(29),	input,	X		),"&
		"76	(BC_7,	Q(29),	bidir,	X,108,0,Z		),"&
		"77	(BC_7,	Q(21),	bidir,	X,108,0,Z		),"&
		"78	(BC_4,	D(21),	input,	X		),"&
		"79	(BC_4,	D(30),	input,	X		),"&
		"80	(BC_7,	Q(30),	bidir,	X,108,0,Z		),"&
		"81	(BC_7,	Q(22),	bidir,	X,108,0,Z		),"&
		"82	(BC_4,	D(22),	input,	X		),"&
		"83	(BC_4,	DOFF_n,	input,	X		),"&
		"84	(BC_4,	D(31),	input,	X		),"&
		"85	(BC_7,	Q(31),	bidir,	X,108,0,Z		),"&
		"86	(BC_7,	Q(23),	bidir,	X,108,0,Z		),"&
		"87	(BC_4,	D(23),	input,	X		),"&
		"88	(BC_4,	D(32),	input,	X		),"&
		"89	(BC_7,	Q(32),	bidir,	X,108,0,Z		),"&
		"90	(BC_7,	Q(24),	bidir,	X,108,0,Z		),"&
		"91	(BC_4,	D(24),	input,	X		),"&
		"92	(BC_4,	D(33),	input,	X		),"&
		"93	(BC_7,	Q(33),	bidir,	X,108,0,Z		),"&
		"94	(BC_7,	Q(25),	bidir,	X,108,0,Z		),"&
		"95	(BC_4,	D(25),	input,	X		),"&
		"96	(BC_4,	D(34),	input,	X		),"&
		"97	(BC_7,	Q(34),	bidir,	X,108,0,Z		),"&
		"98	(BC_7,	Q(26),	bidir,	X,108,0,Z		),"&
		"99	(BC_4,	D(26),	input,	X		),"&
		"100	(BC_4,	D(35),	input,	X		),"&
		"101	(BC_7,	Q(35),	bidir,	X,108,0,Z		),"&
		"102	(BC_4,	SA(12),	input,	X		),"&
		"103	(BC_4,	SA(13),	input,	X		),"&
		"104	(BC_4,	SA(14),	input,	X		),"&
		"105	(BC_4,	SA(15),	input,	X		),"&
		"106	(BC_4,	SA(16),	input,	X		),"&
		"107	(BC_4,	SA(17),	input,	X		),"&
		"108	(BC_2,	*,	controlr,	0)";		

	end	R1QGA3636	;