BSDL Files Library for JTAG

The only free public library that contains thousands of BSDL (Boundary Scan Description Language) models to use with BScan/JTAG tools

BSDL model: LPC11AXX

-- BSDL listing from io_top_create.pl, Fri Feb 10 14:13:11 2012
-- 
-- pins not part of boundary scan are listed as type 'linkage'

entity LPC11Axx is

generic (PHYSICAL_PIN_MAP : string := "HVQFN33");

port (
  P0_26_UART_TXD_SSP1_MISO_CT16B1_CAP1_CT32B0_CAP2 : inout      bit;  -- P0_26_UART_TXD_SSP1_MISO_CT16B1_CAP1_CT32B0_CAP2
  nRESET_P0_0                              : in      bit;  -- nRESET_P0_0
  P0_1_UART_RXD_CLKOUT_CT32B0_MAT2_SSP0_SSEL_CLKIN : inout      bit;  -- P0_1_UART_RXD_CLKOUT_CT32B0_MAT2_SSP0_SSEL_CLKIN
  XTALIN                                   : linkage    bit;  -- XTALIN
  XTALOUT                                  : linkage    bit;  -- XTALOUT
  VDDIO_EXT_11                             : linkage    bit;  -- VDDIO_EXT_1
  P0_24_I2C_SCL_CLKIN_CT16B1_CAP0          : inout      bit;  -- P0_24_I2C_SCL_CLKIN_CT16B1_CAP0
  P0_18_unused_SSP0_SSEL_CT16B0_CAP0_CT16B1_CAP1 : inout      bit;  -- P0_18_unused_SSP0_SSEL_CT16B0_CAP0_CT16B1_CAP1
  P0_19_CLKIN_CLKOUT_SSP0_MOSI_CT16B1_MAT0 : inout      bit;  -- P0_19_CLKIN_CLKOUT_SSP0_MOSI_CT16B1_MAT0
  P0_2_I2C_SCL_ACMP_O_SWCLK_CT16B0_CAP0 : inout      bit;  -- P0_2_I2C_SCL_ACMP_O_SWCLK_CT16B0_CAP0
  P0_3_I2C_SDA_ACMP_O_SWDIO_CT16B1_CAP0 : inout      bit;  -- P0_3_I2C_SDA_ACMP_O_SWDIO_CT16B1_CAP0
  P0_25_I2C_SDA_SSP1_SSEL_CT16B1_MAT0      : inout      bit;  -- P0_25_I2C_SDA_SSP1_SSEL_CT16B1_MAT0
  P0_16_ATRG0_ACMP_I3_CT16B0_CAP1_I2C_SCL : inout      bit;  -- P0_16_ATRG0_ACMP_I3_CT16B0_CAP1_I2C_SCL
  P0_17_ATRG1_ACMP_I4_CT16B0_CAP2_CT16B0_MAT0 : inout      bit;  -- P0_17_ATRG1_ACMP_I4_CT16B0_CAP2_CT16B0_MAT0
  P0_20_unused_SSP0_SCLK_CT32B1_CAP0_CT16B1_MAT2 : inout      bit;  -- P0_20_unused_SSP0_SCLK_CT32B1_CAP0_CT16B1_MAT2
  P0_21_UART_nCTS_ACMP_O_CT32B1_CAP1_UART_SCLK : inout      bit;  -- P0_21_UART_nCTS_ACMP_O_CT32B1_CAP1_UART_SCLK
  P0_22_SSP0_MISO_ACMP_I5_CT32B1_MAT2_CT32B1_CAP2 : inout      bit;  -- P0_22_SSP0_MISO_ACMP_I5_CT32B1_MAT2_CT32B1_CAP2
  P0_4_unused_AOUT_CT16B0_MAT1_SSP0_MOSI : inout      bit;  -- P0_4_unused_AOUT_CT16B0_MAT1_SSP0_MOSI
  JTAG_TCK_SWCLK_P0_5_VDDCMP_CT16B0_MAT2_SSP0_SCLK : in         bit;  -- JTAG_TCK_SWCLK_P0_5_VDDCMP_CT16B0_MAT2_SSP0_SCLK
  P0_14_SSP1_MISO_AD6_CT32B0_CAP1_CT16B1_MAT1 : inout      bit;  -- P0_14_SSP1_MISO_AD6_CT32B0_CAP1_CT16B1_MAT1
  JTAG_TDI_P0_6_AD0_CT32B0_MAT3_SSP0_MISO : in         bit;  -- JTAG_TDI_P0_6_AD0_CT32B0_MAT3_SSP0_MISO
  JTAG_TMS_P0_7_AD1_CT32B1_CAP0_CT16B0_MAT0 : in         bit;  -- JTAG_TMS_P0_7_AD1_CT32B1_CAP0_CT16B0_MAT0
  JTAG_TDO_P0_8_AD2_CT32B1_MAT0_SSP1_SCLK  : out        bit;  -- JTAG_TDO_P0_8_AD2_CT32B1_MAT0_SSP1_SCLK
  JTAG_nTRST_P0_9_AD3_CT32B1_MAT1_CT16B0_MAT1_UART_nCTS : in         bit;  -- JTAG_nTRST_P0_9_AD3_CT32B1_MAT1_CT16B0_MAT1_UART_nCTS
  SWDIO_P0_10_AD4_CT32B1_MAT2_CT16B0_MAT2_UART_nRTS : inout      bit;  -- SWDIO_P0_10_AD4_CT32B1_MAT2_CT16B0_MAT2_UART_nRTS
  P0_11_UART_SCLK_AD5_CT32B1_MAT3_CT32B0_CAP0_WAKEUP : inout      bit;  -- P0_11_UART_SCLK_AD5_CT32B1_MAT3_CT32B0_CAP0_WAKEUP
  P0_15_UART_TXD_AD7_CT32B0_CAP2_I2C_SDA   : inout      bit;  -- P0_15_UART_TXD_AD7_CT32B0_CAP2_I2C_SDA
  P0_27_SSP1_MOSI_ACMP_I1_CT32B1_MAT1_CT16B1_CAP2 : inout      bit;  -- P0_27_SSP1_MOSI_ACMP_I1_CT32B1_MAT1_CT16B1_CAP2
  VDDMAIN_EXT1                             : linkage    bit;  -- VDDMAIN_EXT
  P0_23_UART_nRTS_ACMP_O_CT32B0_CAP0_UART_SCLK : inout      bit;  -- P0_23_UART_nRTS_ACMP_O_CT32B0_CAP0_UART_SCLK
  P0_12_UART_RXD_ACMP_O_CT32B0_MAT0_I2C_SCL_CLKIN : inout      bit;  -- P0_12_UART_RXD_ACMP_O_CT32B0_MAT0_I2C_SCL_CLKIN
  P0_13_UART_TXD_ACMP_I2_CT32B0_MAT1_I2C_SDA : inout      bit   -- P0_13_UART_TXD_ACMP_I2_CT32B0_MAT1_I2C_SDA
);

use STD_1149_1_2001.all;

attribute COMPONENT_CONFORMANCE of LPC11Axx : entity is "std_1149_1_2001";

attribute PIN_MAP               of LPC11Axx : entity is PHYSICAL_PIN_MAP;

constant HVQFN33 : PIN_MAP_STRING :=
  "P0_26_UART_TXD_SSP1_MISO_CT16B1_CAP1_CT32B0_CAP2 :     1," &
  "nRESET_P0_0                              :     2," &
  "P0_1_UART_RXD_CLKOUT_CT32B0_MAT2_SSP0_SSEL_CLKIN :     3," &
  "XTALIN                                   :     4," &
  "XTALOUT                                  :     5," &
  "VDDIO_EXT_11                             :     6," &
  "P0_24_I2C_SCL_CLKIN_CT16B1_CAP0          :     7," &
  "P0_18_unused_SSP0_SSEL_CT16B0_CAP0_CT16B1_CAP1 :     8," &
  "P0_19_CLKIN_CLKOUT_SSP0_MOSI_CT16B1_MAT0 :     9," &
  "P0_2_I2C_SCL_ACMP_O_SWCLK_CT16B0_CAP0 :    10," &
  "P0_3_I2C_SDA_ACMP_O_SWDIO_CT16B1_CAP0 :    11," &
  "P0_25_I2C_SDA_SSP1_SSEL_CT16B1_MAT0      :    12," &
  "P0_16_ATRG0_ACMP_I3_CT16B0_CAP1_I2C_SCL :    13," &
  "P0_17_ATRG1_ACMP_I4_CT16B0_CAP2_CT16B0_MAT0 :    14," &
  "P0_20_unused_SSP0_SCLK_CT32B1_CAP0_CT16B1_MAT2 :    15," &
  "P0_21_UART_nCTS_ACMP_O_CT32B1_CAP1_UART_SCLK :    16," &
  "P0_22_SSP0_MISO_ACMP_I5_CT32B1_MAT2_CT32B1_CAP2 :    17," &
  "P0_4_unused_AOUT_CT16B0_MAT1_SSP0_MOSI :    18," &
  "JTAG_TCK_SWCLK_P0_5_VDDCMP_CT16B0_MAT2_SSP0_SCLK :    19," &
  "P0_14_SSP1_MISO_AD6_CT32B0_CAP1_CT16B1_MAT1 :    20," &
  "JTAG_TDI_P0_6_AD0_CT32B0_MAT3_SSP0_MISO :    21," &
  "JTAG_TMS_P0_7_AD1_CT32B1_CAP0_CT16B0_MAT0 :    22," &
  "JTAG_TDO_P0_8_AD2_CT32B1_MAT0_SSP1_SCLK  :    23," &
  "JTAG_nTRST_P0_9_AD3_CT32B1_MAT1_CT16B0_MAT1_UART_nCTS :    24," &
  "SWDIO_P0_10_AD4_CT32B1_MAT2_CT16B0_MAT2_UART_nRTS :    25," &
  "P0_11_UART_SCLK_AD5_CT32B1_MAT3_CT32B0_CAP0_WAKEUP :    26," &
  "P0_15_UART_TXD_AD7_CT32B0_CAP2_I2C_SDA   :    27," &
  "P0_27_SSP1_MOSI_ACMP_I1_CT32B1_MAT1_CT16B1_CAP2 :    28," &
  "VDDMAIN_EXT1                             :    29," &
  "P0_23_UART_nRTS_ACMP_O_CT32B0_CAP0_UART_SCLK :    30," &
  "P0_12_UART_RXD_ACMP_O_CT32B0_MAT0_I2C_SCL_CLKIN :    31," &
  "P0_13_UART_TXD_ACMP_I2_CT32B0_MAT1_I2C_SDA :    32";


-- *********************************************************************
-- *                       IEEE 1149.1 TAP PORTS                       *
-- *********************************************************************
-- This section specifies the TAP ports. For the TAP TCK port, the
--  parameters in the brackets are: 
--        First Field : Maximum  TCK frequency.
--        Second Field: Allowable states where TCK may be stopped.

    attribute    TAP_SCAN_CLOCK   of JTAG_TCK_SWCLK_P0_5_VDDCMP_CT16B0_MAT2_SSP0_SCLK  : signal  is (10.00e+06,BOTH);
    attribute    TAP_SCAN_IN      of JTAG_TDI_P0_6_AD0_CT32B0_MAT3_SSP0_MISO  : signal  is true;
    attribute    TAP_SCAN_MODE    of JTAG_TMS_P0_7_AD1_CT32B1_CAP0_CT16B0_MAT0  : signal  is true;
    attribute    TAP_SCAN_OUT     of JTAG_TDO_P0_8_AD2_CT32B1_MAT0_SSP1_SCLK  : signal  is true;
    attribute    TAP_SCAN_RESET   of JTAG_nTRST_P0_9_AD3_CT32B1_MAT1_CT16B0_MAT1_UART_nCTS  : signal  is true;

-- Specifies the compliance enable patterns for the design. It lists a set of  
-- design ports and the values that they should be set to, in order to enable  
-- compliance to IEEE Std 1149.1

   attribute COMPLIANCE_PATTERNS of LPC11Axx: entity is 
        "(nRESET_P0_0) (0)";

-- *********************************************************************
-- *                   INSTRUCTIONS AND REGISTER ACCESS                *
-- *********************************************************************

    attribute INSTRUCTION_LENGTH of LPC11Axx : entity is 5;
    attribute INSTRUCTION_OPCODE of LPC11Axx : entity is   
        "extest     (00000)," &
        "sample     (00001)," &
        "preload    (00001)," &
        "highz      (00010)," &
        "clamp      (00011)," &
        "idcode     (00100)," &
        "resrvd     (00101, 00110, 00111, 01000, 01001, 01010, 01011, 01100)," &
        "bypass     (11111)";
    attribute INSTRUCTION_CAPTURE of LPC11Axx : entity is "00001";
    attribute INSTRUCTION_PRIVATE of LPC11Axx : entity is "resrvd";

    attribute IDCODE_REGISTER     of LPC11Axx : entity is 
        "0100"                 &    -- Version Number 
        "xxxxxxxxxxxxxxxx"     &    -- Part Number 
        "00000010101"          &    -- Manufacturer ID 
        "1";                        -- Required by IEEE 

    attribute REGISTER_ACCESS     of LPC11Axx : entity is 
        "BOUNDARY  (extest, sample, preload), " & 
        "DEVICE_ID (idcode), " & 
        "BYPASS    (highz, clamp, bypass)";

-- *********************************************************************
-- *                    BOUNDARY SCAN CELL INFORMATION                 *
-- *********************************************************************
    attribute BOUNDARY_LENGTH   of LPC11Axx : entity is 108;
    attribute BOUNDARY_REGISTER of LPC11Axx : entity is 
-- #     cell    name                                              function  safe    control disable disable
--       type                                                                bit     signal   value  result
   "107   (BC_0,  *                                                 , INTERNAL,  X                         ),"&
   "106   (BC_0,  *                                                 , INTERNAL,  X                         ),"&
   "105   (BC_0,  *                                                 , INTERNAL,  X                         ),"&
   "104   (BC_0,  *                                                 , INTERNAL,  X                         ),"&
   "103   (BC_0,  *                                                 , INTERNAL,  X                         ),"&
   "102   (BC_0,  *                                                 , INTERNAL,  X                         ),"&
   "101   (BC_4,  SWDIO_P0_10_AD4_CT32B1_MAT2_CT16B0_MAT2_UART_nRTS , INPUT,     X                         ),"&
   "100   (BC_1,  SWDIO_P0_10_AD4_CT32B1_MAT2_CT16B0_MAT2_UART_nRTS , OUTPUT3,   X,      99,     0,      Z ),"&
   " 99   (BC_1,  *                                                 , CONTROL,   0                         ),"&
   " 98   (BC_4,  P0_11_UART_SCLK_AD5_CT32B1_MAT3_CT32B0_CAP0_WAKEUP, INPUT,     X                         ),"&
   " 97   (BC_1,  P0_11_UART_SCLK_AD5_CT32B1_MAT3_CT32B0_CAP0_WAKEUP, OUTPUT3,   X,      96,     0,      Z ),"&
   " 96   (BC_1,  *                                                 , CONTROL,   0                         ),"&
   " 95   (BC_0,  *                                                 , INTERNAL,  X                         ),"&
   " 94   (BC_0,  *                                                 , INTERNAL,  X                         ),"&
   " 93   (BC_0,  *                                                 , INTERNAL,  X                         ),"&
   " 92   (BC_4,  P0_15_UART_TXD_AD7_CT32B0_CAP2_I2C_SDA            , INPUT,     X                         ),"&
   " 91   (BC_1,  P0_15_UART_TXD_AD7_CT32B0_CAP2_I2C_SDA            , OUTPUT3,   X,      90,     0,      Z ),"&
   " 90   (BC_1,  *                                                 , CONTROL,   0                         ),"&
   " 89   (BC_4,  P0_27_SSP1_MOSI_ACMP_I1_CT32B1_MAT1_CT16B1_CAP2   , INPUT,     X                         ),"&
   " 88   (BC_1,  P0_27_SSP1_MOSI_ACMP_I1_CT32B1_MAT1_CT16B1_CAP2   , OUTPUT3,   X,      87,     0,      Z ),"&
   " 87   (BC_1,  *                                                 , CONTROL,   0                         ),"&
   " 86   (BC_4,  P0_23_UART_nRTS_ACMP_O_CT32B0_CAP0_UART_SCLK      , INPUT,     X                         ),"&
   " 85   (BC_1,  P0_23_UART_nRTS_ACMP_O_CT32B0_CAP0_UART_SCLK      , OUTPUT3,   X,      84,     0,      Z ),"&
   " 84   (BC_1,  *                                                 , CONTROL,   0                         ),"&
   " 83   (BC_4,  P0_12_UART_RXD_ACMP_O_CT32B0_MAT0_I2C_SCL_CLKIN, INPUT,     X                         ),"&
   " 82   (BC_1,  P0_12_UART_RXD_ACMP_O_CT32B0_MAT0_I2C_SCL_CLKIN, OUTPUT3,   X,      81,     0,      Z ),"&
   " 81   (BC_1,  *                                                 , CONTROL,   0                         ),"&
   " 80   (BC_4,  P0_13_UART_TXD_ACMP_I2_CT32B0_MAT1_I2C_SDA  , INPUT,     X                         ),"&
   " 79   (BC_1,  P0_13_UART_TXD_ACMP_I2_CT32B0_MAT1_I2C_SDA  , OUTPUT3,   X,      78,     0,      Z ),"&
   " 78   (BC_1,  *                                                 , CONTROL,   0                         ),"&
   " 77   (BC_0,  *                                                 , INTERNAL,  X                         ),"&
   " 76   (BC_0,  *                                                 , INTERNAL,  X                         ),"&
   " 75   (BC_0,  *                                                 , INTERNAL,  X                         ),"&
   " 74   (BC_4,  P0_26_UART_TXD_SSP1_MISO_CT16B1_CAP1_CT32B0_CAP2  , INPUT,     X                         ),"&
   " 73   (BC_1,  P0_26_UART_TXD_SSP1_MISO_CT16B1_CAP1_CT32B0_CAP2  , OUTPUT3,   X,      72,     0,      Z ),"&
   " 72   (BC_1,  *                                                 , CONTROL,   0                         ),"&
   " 71   (BC_0,  *                                                 , INTERNAL,  X                         ),"&
   " 70   (BC_0,  *                                                 , INTERNAL,  X                         ),"&
   " 69   (BC_0,  *                                                 , INTERNAL,  X                         ),"&
   " 68   (BC_4,  P0_1_UART_RXD_CLKOUT_CT32B0_MAT2_SSP0_SSEL_CLKIN, INPUT,     X                         ),"&
   " 67   (BC_1,  P0_1_UART_RXD_CLKOUT_CT32B0_MAT2_SSP0_SSEL_CLKIN, OUTPUT3,   X,      66,     0,      Z ),"&
   " 66   (BC_1,  *                                                 , CONTROL,   0                         ),"&
   " 65   (BC_4,  P0_24_I2C_SCL_CLKIN_CT16B1_CAP0                   , INPUT,     X                         ),"&
   " 64   (BC_1,  P0_24_I2C_SCL_CLKIN_CT16B1_CAP0                   , OUTPUT3,   X,      63,     0,      Z ),"&
   " 63   (BC_1,  *                                                 , CONTROL,   0                         ),"&
   " 62   (BC_4,  P0_18_unused_SSP0_SSEL_CT16B0_CAP0_CT16B1_CAP1    , INPUT,     X                         ),"&
   " 61   (BC_1,  P0_18_unused_SSP0_SSEL_CT16B0_CAP0_CT16B1_CAP1    , OUTPUT3,   X,      60,     0,      Z ),"&
   " 60   (BC_1,  *                                                 , CONTROL,   0                         ),"&
   " 59   (BC_0,  *                                                 , INTERNAL,  X                         ),"&
   " 58   (BC_0,  *                                                 , INTERNAL,  X                         ),"&
   " 57   (BC_0,  *                                                 , INTERNAL,  X                         ),"&
   " 56   (BC_0,  *                                                 , INTERNAL,  X                         ),"&
   " 55   (BC_0,  *                                                 , INTERNAL,  X                         ),"&
   " 54   (BC_0,  *                                                 , INTERNAL,  X                         ),"&
   " 53   (BC_0,  *                                                 , INTERNAL,  X                         ),"&
   " 52   (BC_0,  *                                                 , INTERNAL,  X                         ),"&
   " 51   (BC_0,  *                                                 , INTERNAL,  X                         ),"&
   " 50   (BC_4,  P0_19_CLKIN_CLKOUT_SSP0_MOSI_CT16B1_MAT0          , INPUT,     X                         ),"&
   " 49   (BC_1,  P0_19_CLKIN_CLKOUT_SSP0_MOSI_CT16B1_MAT0          , OUTPUT3,   X,      48,     0,      Z ),"&
   " 48   (BC_1,  *                                                 , CONTROL,   0                         ),"&
   " 47   (BC_4,  P0_2_I2C_SCL_ACMP_O_SWCLK_CT16B0_CAP0       , INPUT,     X                         ),"&
   " 46   (BC_1,  P0_2_I2C_SCL_ACMP_O_SWCLK_CT16B0_CAP0       , OUTPUT3,   X,      45,     0,  WEAK1 ),"&
   " 45   (BC_1,  *                                                 , CONTROL,   0                         ),"&
   " 44   (BC_4,  P0_3_I2C_SDA_ACMP_O_SWDIO_CT16B1_CAP0       , INPUT,     X                         ),"&
   " 43   (BC_1,  P0_3_I2C_SDA_ACMP_O_SWDIO_CT16B1_CAP0       , OUTPUT3,   X,      42,     0,  WEAK1 ),"&
   " 42   (BC_1,  *                                                 , CONTROL,   0                         ),"&
   " 41   (BC_4,  P0_25_I2C_SDA_SSP1_SSEL_CT16B1_MAT0               , INPUT,     X                         ),"&
   " 40   (BC_1,  P0_25_I2C_SDA_SSP1_SSEL_CT16B1_MAT0               , OUTPUT3,   X,      39,     0,      Z ),"&
   " 39   (BC_1,  *                                                 , CONTROL,   0                         ),"&
   " 38   (BC_4,  P0_16_ATRG0_ACMP_I3_CT16B0_CAP1_I2C_SCL     , INPUT,     X                         ),"&
   " 37   (BC_1,  P0_16_ATRG0_ACMP_I3_CT16B0_CAP1_I2C_SCL     , OUTPUT3,   X,      36,     0,      Z ),"&
   " 36   (BC_1,  *                                                 , CONTROL,   0                         ),"&
   " 35   (BC_0,  *                                                 , INTERNAL,  X                         ),"&
   " 34   (BC_0,  *                                                 , INTERNAL,  X                         ),"&
   " 33   (BC_0,  *                                                 , INTERNAL,  X                         ),"&
   " 32   (BC_0,  *                                                 , INTERNAL,  X                         ),"&
   " 31   (BC_0,  *                                                 , INTERNAL,  X                         ),"&
   " 30   (BC_0,  *                                                 , INTERNAL,  X                         ),"&
   " 29   (BC_4,  P0_17_ATRG1_ACMP_I4_CT16B0_CAP2_CT16B0_MAT0, INPUT,     X                         ),"&
   " 28   (BC_1,  P0_17_ATRG1_ACMP_I4_CT16B0_CAP2_CT16B0_MAT0, OUTPUT3,   X,      27,     0,      Z ),"&
   " 27   (BC_1,  *                                                 , CONTROL,   0                         ),"&
   " 26   (BC_4,  P0_20_unused_SSP0_SCLK_CT32B1_CAP0_CT16B1_MAT2, INPUT,     X                         ),"&
   " 25   (BC_1,  P0_20_unused_SSP0_SCLK_CT32B1_CAP0_CT16B1_MAT2, OUTPUT3,   X,      24,     0,      Z ),"&
   " 24   (BC_1,  *                                                 , CONTROL,   0                         ),"&
   " 23   (BC_4,  P0_21_UART_nCTS_ACMP_O_CT32B1_CAP1_UART_SCLK      , INPUT,     X                         ),"&
   " 22   (BC_1,  P0_21_UART_nCTS_ACMP_O_CT32B1_CAP1_UART_SCLK      , OUTPUT3,   X,      21,     0,      Z ),"&
   " 21   (BC_1,  *                                                 , CONTROL,   0                         ),"&
   " 20   (BC_0,  *                                                 , INTERNAL,  X                         ),"&
   " 19   (BC_0,  *                                                 , INTERNAL,  X                         ),"&
   " 18   (BC_0,  *                                                 , INTERNAL,  X                         ),"&
   " 17   (BC_0,  *                                                 , INTERNAL,  X                         ),"&
   " 16   (BC_0,  *                                                 , INTERNAL,  X                         ),"&
   " 15   (BC_0,  *                                                 , INTERNAL,  X                         ),"&
   " 14   (BC_0,  *                                                 , INTERNAL,  X                         ),"&
   " 13   (BC_0,  *                                                 , INTERNAL,  X                         ),"&
   " 12   (BC_0,  *                                                 , INTERNAL,  X                         ),"&
   " 11   (BC_4,  P0_22_SSP0_MISO_ACMP_I5_CT32B1_MAT2_CT32B1_CAP2   , INPUT,     X                         ),"&
   " 10   (BC_1,  P0_22_SSP0_MISO_ACMP_I5_CT32B1_MAT2_CT32B1_CAP2   , OUTPUT3,   X,       9,     0,      Z ),"&
   "  9   (BC_1,  *                                                 , CONTROL,   0                         ),"&
   "  8   (BC_4,  P0_4_unused_AOUT_CT16B0_MAT1_SSP0_MOSI      , INPUT,     X                         ),"&
   "  7   (BC_1,  P0_4_unused_AOUT_CT16B0_MAT1_SSP0_MOSI      , OUTPUT3,   X,       6,     0,      Z ),"&
   "  6   (BC_1,  *                                                 , CONTROL,   0                         ),"&
   "  5   (BC_4,  P0_14_SSP1_MISO_AD6_CT32B0_CAP1_CT16B1_MAT1       , INPUT,     X                         ),"&
   "  4   (BC_1,  P0_14_SSP1_MISO_AD6_CT32B0_CAP1_CT16B1_MAT1       , OUTPUT3,   X,       3,     0,      Z ),"&
   "  3   (BC_1,  *                                                 , CONTROL,   0                         ),"&
   "  2   (BC_0,  *                                                 , INTERNAL,  X                         ),"&
   "  1   (BC_0,  *                                                 , INTERNAL,  X                         ),"&
   "  0   (BC_0,  *                                                 , INTERNAL,  X                         )";
end LPC11Axx;