-- *************************************(C) COPYRIGHT 20xx NXP Semiconductors *************************************************
-- File Name: LQFP64.bsdl
-- Version: V1.0
-- Date: 11/05/2014
-- Description: Boundary Scan Description Language (BSDL) file for the NXP Semiconductors Microcontrollers
-- ********************************************************************************************************************************************
-- BSDL file that is described herein is for illustrative purposes only which provides customers to perform boundary
-- scan on the LPC products. This file is supplied "AS IS" without any warranties of any kind.NXP Semiconductors
-- assumes no responsibility or liability for the use of the file, conveys no license or rights under any patent, copyright,
-- mask work right, or any other intellectual property rights in or to any products. NXP Semiconductors reserves the
-- right to make changes in the file without notification. NXP Semiconductors also makes no representation or warranty
-- that such application will be suitable for the specified use without further testing or modification.
-- Permission to use, copy, modify, and distribute this file is hereby granted, under NXP Semiconductors' without fee,
-- provided that it is used in conjunction with NXP Semiconductors microcontrollers. This copyright, permission, and
-- disclaimer notice must appear in all copies of this file.
-- ********************************************************************************************************************************************
--
-- pins not part of boundary scan are listed as type 'linkage'
entity LPC540xx is
generic (PHYSICAL_PIN_MAP : string := "LQFP64");
port (
p0_23 : inout bit; -- P0[23]_bi2c0_scl_unused_ct0cap0_ezh_pio23
p0_24 : inout bit; -- P0[24]_bi2c0_sda_unused_ct0cap1_ezh_pio24_ct0mat0
p0_25 : inout bit; -- P0[25]_bi2c1_scl_minuart1_cts_ct0cap2_ezh_pio25_ct1cap1
p0_26 : inout bit; -- P0[26]_bi2c1_sda_unused_ct0cap3_ezh_pio26
p0_27 : inout bit; -- P0[27]_bi2c2_scl_unused_ct2cap0_ezh_pio27
p0_28 : inout bit; -- P0[28]_bi2c2_sda_unused_ct2mat0_ezh_pio28
p1_16 : inout bit; -- P1[16]_unused_ct0mat0_ct0cap0_lspi1_sselsn_1
vdde1 : linkage bit; -- Vdd(3v3)
gnde1 : linkage bit; -- Vss
p1_17 : inout bit; -- P1[17]
p0_29 : inout bit; -- P0[29]_adcin0_sct0_out2_ct0mat3_ezh_pio29_ct0cap1_ct0mat1
p0_30 : inout bit; -- P0[30]_adcin1_sct0_out3_ct0mat2_ezh_pio30_ct0cap2
p0_31 : inout bit; -- P0[31]_adcin2_minuart2_cts_ct2cap2_ezh_pio31_ct0cap3_ct0mat3
p1_0 : inout bit; -- P1[0]_adcin3_minuart2_rts_ct3mat1_unused_ct0cap0
p1_1 : inout bit; -- P1[1]_adcin4_swo_sct0_out4
p1_2 : inout bit; -- P1[2]_adcin5_lspi1_sselsn_3_sct0_out5
p1_3 : inout bit; -- P1[3]_adcin6_lspi1_sselsn_2_sct0_out6_unused_lspi0_sck_ct0cap1
p1_4 : inout bit; -- P1[4]_adcin7_lspi1_sselsn_1_sct0_out7_unused_lspi0_miso_ct0mat1
p1_5 : inout bit; -- P1[5]_adcin8_lspi1_sselsn_0_ct1cap0_unused_ct1mat3_pvt_amber0_alert
vssa1 : linkage bit; -- Vssa
vrefn1 : linkage bit; -- Vrefn
vrefp1 : linkage bit; -- Vrefp
vdda1 : linkage bit; -- Vdda
vdde2 : linkage bit; -- Vdd(3v3)
gnde2 : linkage bit; -- Vss
p1_6 : inout bit; -- P1[6]_adcin9_lspi1_sck_ct1cap2_unused_ct1mat2_pvt_red0_alert
p1_7 : inout bit; -- P1[7]_adcin10_lspi1_mosi_ct1mat2_unused_ct1cap2_pvt_amber1_alert
p1_8 : inout bit; -- P1[8]_adcin11_lspi1_miso_ct1mat3_unused_ct1cap3_pvt_red1_alert
p1_9 : inout bit; -- P1[9]_unused_lspi0_mosi_ct0cap2
p1_10 : inout bit; -- P1[10]_unused_minuart1_txd_sct0_out4
p0_0 : inout bit; -- P0[0]_minuart0_rxd_lspi0_sselsn_0_ct0cap0_ezh_pio0_sct0_out3
p0_1 : inout bit; -- P0[1]_minuart0_txd_lspi0_sselsn_1_ct0cap1_ezh_pio1_sct0_out1
rtcx1 : linkage bit; -- RTCX1
vddreg : linkage bit; -- Vdd(reg)
rtcx2 : linkage bit; -- RTCX2
p0_2 : inout bit; -- P0[2]_minuart0_cts_unused_ct2cap1_ezh_pio2
p0_3 : inout bit; -- P0[3]_minuart0_rts_unused_ct1mat3_ezh_pio3
p0_4 : inout bit; -- P0[4]_minuart0_sclk_lspi0_sselsn_2_ct0cap2_ezh_pio4
p0_5 : inout bit; -- P0[5]_minuart1_rxd_sct0_out6_ct0mat0_ezh_pio5
p0_6 : inout bit; -- P0[6]_minuart1_txd_unused_ct0mat1_ezh_pio6
p0_7 : inout bit; -- P0[7]_minuart1_sclk_sct0_out0_ct0mat2_ezh_pio7_ct0cap2
p1_11 : inout bit; -- P1[11]_unused_minuart1_rts_ct1cap0
p0_8 : inout bit; -- P0[8]_minuart2_rxd_sct0_out1_ct0mat3_ezh_pio8
p0_9 : inout bit; -- P0[9]_minuart2_txd_sct0_out2_ct3cap0_ezh_pio9_lspi0_sselsn_0
p0_10 : inout bit; -- P0[10]_minuart2_sclk_sct0_out3_ct3mat0_ezh_pio10
p0_11 : inout bit; -- P0[11]_lspi0_sck_minuart1_rxd_ct2mat1_ezh_pio11
p0_12 : inout bit; -- P0[12]_lspi0_mosi_minuart1_txd_ct2mat3_ezh_pio12
p0_13 : inout bit; -- P0[13]_lspi0_miso_sct0_out4_ct2mat0_ezh_pio13
p0_14 : in bit; -- P0[14]_lspi0_sselsn_0_sct0_out5_ct2mat1_ezh_pio14_unused_unused_unused_JTAG_TCK
p0_15 : out bit; -- P0[15]_lspi0_sselsn_1_swo_ct2mat2_ezh_pio15_unused_unused_unused_JTAG_TDO
p1_12 : inout bit; -- P1[12]_unused_minuart3_rxd_ct1mat0_lspi1_sck
p0_16 : inout bit; -- P0[16]_lspi0_sselsn_2_minuart1_cts_ct3mat1_ezh_pio16_swclk_tck
p0_17 : inout bit; -- P0[17]_lspi0_sselsn_3_minuart1_rts_ct3mat2_ezh_pio17_swdio
p1_13 : inout bit; -- P1[13]_unused_minuart3_txd_ct1mat1_lspi1_mosi
gnde3 : linkage bit; -- Vss
vdde3 : linkage bit; -- Vdd(3v3)
p1_14 : inout bit; -- P1[14]_unused_minuart2_rxd_sct0_out7_lspi1_miso
p0_18 : in bit; -- P0[18]_minuart3_txd_sct0_out0_ct0mat0_ezh_pio18_unused_unused_unused_JTAG_TRSTn
p0_19 : in bit; -- P0[19]_minuart3_sclk_sct0_out1_ct0mat1_ezh_pio19_unused_unused_unused_JTAG_TDI
p0_20 : in bit; -- P0[20]_minuart3_rxd_minuart0_sclk_ct3cap0_ezh_pio20_unused_unused_unused_JTAG_TMS
p0_21 : inout bit; -- P0[21]_clkout_minuart0_txd_ct3mat0_ezh_pio21
p1_15 : inout bit; -- P1[15]_unused_sct0_out5_ct1cap3_lspi1_sselsn_0
p0_22 : inout bit; -- P0[22]_clkin_minuart0_rxd_ct3mat3_ezh_pio22
reset_n : in bit -- RESETn
);
use STD_1149_1_2001.all;
attribute COMPONENT_CONFORMANCE of LPC540xx : entity is "std_1149_1_2001";
attribute PIN_MAP of LPC540xx : entity is PHYSICAL_PIN_MAP;
constant LQFP64 : PIN_MAP_STRING :=
"p0_23 : 1," &
"p0_24 : 2," &
"p0_25 : 3," &
"p0_26 : 4," &
"p0_27 : 5," &
"p0_28 : 6," &
"p1_16 : 7," &
"vdde1 : 8," &
"gnde1 : 9," &
"p1_17 : 10," &
"p0_29 : 11," &
"p0_30 : 12," &
"p0_31 : 13," &
"p1_0 : 14," &
"p1_1 : 15," &
"p1_2 : 16," &
"p1_3 : 17," &
"p1_4 : 18," &
"p1_5 : 19," &
"vssa1 : 20," &
"vrefn1 : 21," &
"vrefp1 : 22," &
"vdda1 : 23," &
"vdde2 : 24," &
"gnde2 : 25," &
"p1_6 : 26," &
"p1_7 : 27," &
"p1_8 : 28," &
"p1_9 : 29," &
"p1_10 : 30," &
"p0_0 : 31," &
"p0_1 : 32," &
"rtcx1 : 34," &
"vddreg : 33," &
"rtcx2 : 35," &
"p0_2 : 36," &
"p0_3 : 37," &
"p0_4 : 38," &
"p0_5 : 39," &
"p0_6 : 40," &
"p0_7 : 41," &
"p1_11 : 42," &
"p0_8 : 43," &
"p0_9 : 44," &
"p0_10 : 45," &
"p0_11 : 46," &
"p0_12 : 47," &
"p0_13 : 48," &
"p0_14 : 49," &
"p0_15 : 50," &
"p1_12 : 51," &
"p0_16 : 52," &
"p0_17 : 53," &
"p1_13 : 54," &
"gnde3 : 55," &
"vdde3 : 56," &
"p1_14 : 57," &
"p0_18 : 58," &
"p0_19 : 59," &
"p0_20 : 60," &
"p0_21 : 61," &
"p1_15 : 62," &
"p0_22 : 63," &
"reset_n : 64";
-- *********************************************************************
-- * IEEE 1149.1 TAP PORTS *
-- *********************************************************************
-- This section specifies the TAP ports. For the TAP TCK port, the
-- parameters in the brackets are:
-- First Field : Maximum TCK frequency.
-- Second Field: Allowable states where TCK may be stopped.
attribute TAP_SCAN_CLOCK of p0_14 : signal is (10.00e+06,BOTH);
attribute TAP_SCAN_IN of p0_19 : signal is true;
attribute TAP_SCAN_MODE of p0_20 : signal is true;
attribute TAP_SCAN_OUT of p0_15 : signal is true;
attribute TAP_SCAN_RESET of p0_18 : signal is true;
-- Specifies the compliance enable patterns for the design. It lists a set of
-- design ports and the values that they should be set to, in order to enable
-- compliance to IEEE Std 1149.1
attribute COMPLIANCE_PATTERNS of LPC540xx: entity is
"(reset_n) (0)";
-- *********************************************************************
-- * INSTRUCTIONS AND REGISTER ACCESS *
-- *********************************************************************
attribute INSTRUCTION_LENGTH of LPC540xx : entity is 5;
attribute INSTRUCTION_OPCODE of LPC540xx : entity is
"extest (00000)," &
"sample (00001)," &
"preload (00001)," &
"highz (00010)," &
"clamp (00011)," &
"idcode (00100)," &
"resrvd (00101, 00110, 00111, 01000, 01001, 01010, 01011, 01100)," &
"bypass (11111)";
attribute INSTRUCTION_CAPTURE of LPC540xx : entity is "00001";
attribute INSTRUCTION_PRIVATE of LPC540xx : entity is "resrvd";
attribute IDCODE_REGISTER of LPC540xx : entity is
"0xxx" & -- Version Number
"1111111011001110" & -- Part Number
"00000010101" & -- Manufacturer ID
"1"; -- Required by IEEE
attribute REGISTER_ACCESS of LPC540xx : entity is
"BOUNDARY (extest, sample, preload), " &
"DEVICE_ID (idcode), " &
"BYPASS (highz, clamp, bypass)";
-- *********************************************************************
-- * BOUNDARY SCAN CELL INFORMATION *
-- *********************************************************************
attribute BOUNDARY_LENGTH of LPC540xx : entity is 135;
attribute BOUNDARY_REGISTER of LPC540xx : entity is
-- # cell name function safe control disable disable
-- type bit signal value result
"134 (BC_4, p0_21 , INPUT, X ),"&
"133 (BC_1, p0_21 , OUTPUT3, X, 132, 0, Z ),"&
"132 (BC_1, * , CONTROL, 0 ),"&
"131 (BC_4, p1_15 , INPUT, X ),"&
"130 (BC_1, p1_15 , OUTPUT3, X, 129, 0, Z ),"&
"129 (BC_1, * , CONTROL, 0 ),"&
"128 (BC_4, p0_22 , INPUT, X ),"&
"127 (BC_1, p0_22 , OUTPUT3, X, 126, 0, Z ),"&
"126 (BC_1, * , CONTROL, 0 ),"&
"125 (BC_4, p0_23 , INPUT, X ),"&
"124 (BC_1, p0_23 , OUTPUT3, X, 123, 0, Z ),"&
"123 (BC_1, * , CONTROL, 0 ),"&
"122 (BC_4, p0_24 , INPUT, X ),"&
"121 (BC_1, p0_24 , OUTPUT3, X, 120, 0, Z ),"&
"120 (BC_1, * , CONTROL, 0 ),"&
"119 (BC_4, p0_25 , INPUT, X ),"&
"118 (BC_1, p0_25 , OUTPUT3, X, 117, 0, Z ),"&
"117 (BC_1, * , CONTROL, 0 ),"&
"116 (BC_4, p0_26 , INPUT, X ),"&
"115 (BC_1, p0_26 , OUTPUT3, X, 114, 0, Z ),"&
"114 (BC_1, * , CONTROL, 0 ),"&
"113 (BC_4, p0_27 , INPUT, X ),"&
"112 (BC_1, p0_27 , OUTPUT3, X, 111, 0, Z ),"&
"111 (BC_1, * , CONTROL, 0 ),"&
"110 (BC_4, p0_28 , INPUT, X ),"&
"109 (BC_1, p0_28 , OUTPUT3, X, 108, 0, Z ),"&
"108 (BC_1, * , CONTROL, 0 ),"&
"107 (BC_4, p1_16 , INPUT, X ),"&
"106 (BC_1, p1_16 , OUTPUT3, X, 105, 0, Z ),"&
"105 (BC_1, * , CONTROL, 0 ),"&
"104 (BC_4, p1_17 , INPUT, X ),"&
"103 (BC_1, p1_17 , OUTPUT3, X, 102, 0, Z ),"&
"102 (BC_1, * , CONTROL, 0 ),"&
"101 (BC_4, p0_29 , INPUT, X ),"&
"100 (BC_1, p0_29 , OUTPUT3, X, 99, 0, Z ),"&
" 99 (BC_1, * , CONTROL, 0 ),"&
" 98 (BC_4, p0_30 , INPUT, X ),"&
" 97 (BC_1, p0_30 , OUTPUT3, X, 96, 0, Z ),"&
" 96 (BC_1, * , CONTROL, 0 ),"&
" 95 (BC_4, p0_31 , INPUT, X ),"&
" 94 (BC_1, p0_31 , OUTPUT3, X, 93, 0, Z ),"&
" 93 (BC_1, * , CONTROL, 0 ),"&
" 92 (BC_4, p1_0 , INPUT, X ),"&
" 91 (BC_1, p1_0 , OUTPUT3, X, 90, 0, Z ),"&
" 90 (BC_1, * , CONTROL, 0 ),"&
" 89 (BC_4, p1_1 , INPUT, X ),"&
" 88 (BC_1, p1_1 , OUTPUT3, X, 87, 0, Z ),"&
" 87 (BC_1, * , CONTROL, 0 ),"&
" 86 (BC_4, p1_2 , INPUT, X ),"&
" 85 (BC_1, p1_2 , OUTPUT3, X, 84, 0, Z ),"&
" 84 (BC_1, * , CONTROL, 0 ),"&
" 83 (BC_4, p1_3 , INPUT, X ),"&
" 82 (BC_1, p1_3 , OUTPUT3, X, 81, 0, Z ),"&
" 81 (BC_1, * , CONTROL, 0 ),"&
" 80 (BC_4, p1_4 , INPUT, X ),"&
" 79 (BC_1, p1_4 , OUTPUT3, X, 78, 0, Z ),"&
" 78 (BC_1, * , CONTROL, 0 ),"&
" 77 (BC_4, p1_5 , INPUT, X ),"&
" 76 (BC_1, p1_5 , OUTPUT3, X, 75, 0, Z ),"&
" 75 (BC_1, * , CONTROL, 0 ),"&
" 74 (BC_4, p1_6 , INPUT, X ),"&
" 73 (BC_1, p1_6 , OUTPUT3, X, 72, 0, Z ),"&
" 72 (BC_1, * , CONTROL, 0 ),"&
" 71 (BC_4, p1_7 , INPUT, X ),"&
" 70 (BC_1, p1_7 , OUTPUT3, X, 69, 0, Z ),"&
" 69 (BC_1, * , CONTROL, 0 ),"&
" 68 (BC_4, p1_8 , INPUT, X ),"&
" 67 (BC_1, p1_8 , OUTPUT3, X, 66, 0, Z ),"&
" 66 (BC_1, * , CONTROL, 0 ),"&
" 65 (BC_4, p1_9 , INPUT, X ),"&
" 64 (BC_1, p1_9 , OUTPUT3, X, 63, 0, Z ),"&
" 63 (BC_1, * , CONTROL, 0 ),"&
" 62 (BC_4, p1_10 , INPUT, X ),"&
" 61 (BC_1, p1_10 , OUTPUT3, X, 60, 0, Z ),"&
" 60 (BC_1, * , CONTROL, 0 ),"&
" 59 (BC_4, p0_0 , INPUT, X ),"&
" 58 (BC_1, p0_0 , OUTPUT3, X, 57, 0, Z ),"&
" 57 (BC_1, * , CONTROL, 0 ),"&
" 56 (BC_4, p0_1 , INPUT, X ),"&
" 55 (BC_1, p0_1 , OUTPUT3, X, 54, 0, Z ),"&
" 54 (BC_1, * , CONTROL, 0 ),"&
" 53 (BC_4, p0_2 , INPUT, X ),"&
" 52 (BC_1, p0_2 , OUTPUT3, X, 51, 0, Z ),"&
" 51 (BC_1, * , CONTROL, 0 ),"&
" 50 (BC_4, p0_3 , INPUT, X ),"&
" 49 (BC_1, p0_3 , OUTPUT3, X, 48, 0, Z ),"&
" 48 (BC_1, * , CONTROL, 0 ),"&
" 47 (BC_4, p0_4 , INPUT, X ),"&
" 46 (BC_1, p0_4 , OUTPUT3, X, 45, 0, Z ),"&
" 45 (BC_1, * , CONTROL, 0 ),"&
" 44 (BC_4, p0_5 , INPUT, X ),"&
" 43 (BC_1, p0_5 , OUTPUT3, X, 42, 0, Z ),"&
" 42 (BC_1, * , CONTROL, 0 ),"&
" 41 (BC_4, p0_6 , INPUT, X ),"&
" 40 (BC_1, p0_6 , OUTPUT3, X, 39, 0, Z ),"&
" 39 (BC_1, * , CONTROL, 0 ),"&
" 38 (BC_4, p0_7 , INPUT, X ),"&
" 37 (BC_1, p0_7 , OUTPUT3, X, 36, 0, Z ),"&
" 36 (BC_1, * , CONTROL, 0 ),"&
" 35 (BC_4, p1_11 , INPUT, X ),"&
" 34 (BC_1, p1_11 , OUTPUT3, X, 33, 0, Z ),"&
" 33 (BC_1, * , CONTROL, 0 ),"&
" 32 (BC_4, p0_8 , INPUT, X ),"&
" 31 (BC_1, p0_8 , OUTPUT3, X, 30, 0, Z ),"&
" 30 (BC_1, * , CONTROL, 0 ),"&
" 29 (BC_4, p0_9 , INPUT, X ),"&
" 28 (BC_1, p0_9 , OUTPUT3, X, 27, 0, Z ),"&
" 27 (BC_1, * , CONTROL, 0 ),"&
" 26 (BC_4, p0_10 , INPUT, X ),"&
" 25 (BC_1, p0_10 , OUTPUT3, X, 24, 0, Z ),"&
" 24 (BC_1, * , CONTROL, 0 ),"&
" 23 (BC_4, p0_11 , INPUT, X ),"&
" 22 (BC_1, p0_11 , OUTPUT3, X, 21, 0, Z ),"&
" 21 (BC_1, * , CONTROL, 0 ),"&
" 20 (BC_4, p0_12 , INPUT, X ),"&
" 19 (BC_1, p0_12 , OUTPUT3, X, 18, 0, Z ),"&
" 18 (BC_1, * , CONTROL, 0 ),"&
" 17 (BC_4, p0_13 , INPUT, X ),"&
" 16 (BC_1, p0_13 , OUTPUT3, X, 15, 0, Z ),"&
" 15 (BC_1, * , CONTROL, 0 ),"&
" 14 (BC_4, p1_12 , INPUT, X ),"&
" 13 (BC_1, p1_12 , OUTPUT3, X, 12, 0, Z ),"&
" 12 (BC_1, * , CONTROL, 0 ),"&
" 11 (BC_4, p0_16 , INPUT, X ),"&
" 10 (BC_1, p0_16 , OUTPUT3, X, 9, 0, Z ),"&
" 9 (BC_1, * , CONTROL, 0 ),"&
" 8 (BC_4, p0_17 , INPUT, X ),"&
" 7 (BC_1, p0_17 , OUTPUT3, X, 6, 0, Z ),"&
" 6 (BC_1, * , CONTROL, 0 ),"&
" 5 (BC_4, p1_13 , INPUT, X ),"&
" 4 (BC_1, p1_13 , OUTPUT3, X, 3, 0, Z ),"&
" 3 (BC_1, * , CONTROL, 0 ),"&
" 2 (BC_4, p1_14 , INPUT, X ),"&
" 1 (BC_1, p1_14 , OUTPUT3, X, 0, 0, Z ),"&
" 0 (BC_1, * , CONTROL, 0 )";
end LPC540xx;