----------------------------------------------------------------------
-- TI TMS320CENTAURUS Fixed & Floating Point DSP with Boundary Scan --
----------------------------------------------------------------------
-- Supported Devices: TMS320CENTAURUS Revision 3.0 --
----------------------------------------------------------------------
-- Created by : Texas Instruments Incorporated --
-- Documentation : TMS320CENTAURUS Users Guide --
-- BSDL Revision : 2.0 originally created --
-- Release Comments :
-- DDR and MLB differential pins are reperesented as differential in BSDL --
-- ddr1_ck,ddr0_nck and ddr1_ck,ddr1_nck were made differential
-- ddr0_nck and ddr1_nck related BSCAN cells were set to internal --
-- BSDL Status : Preliminary --
-- Date Created : 7/03/2012 --
-- --
----------------------------------------------------------------------
-- --
-- IMPORTANT NOTICE
-- Texas Instruments Incorporated (TI) reserves the right to make
-- changes to its products or to discontinue any semiconductor
-- product or service without notice, and advises its customers to
-- obtain the latest version of the relevant information to
-- verify, before placing orders, that the information being
-- relied on is current.
-- TI warrants performance of its semiconductor products and
-- related software to the specifications applicable at the time
-- of sale in accordance with TI's standard warranty. Testing and
-- other quality control techniques are utilized to the extent TI
-- deems necessary to support this warranty. Specific testing of
-- all parameters of each device is not necessarily performed,
-- except those mandated by government requirements.
--
-- Certain applications using semiconductor devices may involve
-- potential risks of death, personal injury, or severe property
-- or environmental damage ("Critical Applications").
-- TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED,
-- AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN
-- LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER
-- CRITICAL APPLICATIONS.
-- Inclusion of TI products in such applications is understood
-- to be fully at the risk of the customer. Use of TI products
-- in such applications requires the written approval of an
-- appropriate TI officer. Questions concerning potential risk
-- applications should be directed to TI through a local SC sales
-- office.
-- In order to minimize risks associated with the customer's
-- applications, adequate design and operating safeguards should
-- be provided by the
-- customer to minimize inherent or procedural hazards.
-- TI assumes no liability for applications assistance, customer
-- product design, software performance, or infringement of
-- patents or services described herein. Nor does TI warrant or
-- represent that any license, either express or implied, is
-- granted under any patent right, copyright, mask work right, or
-- other intellectual property right of TI covering or relating
-- to any combination, machine, or process in which such
-- semiconductor products or services might be or are used.
-- Copyright (c) 2001, Texas Instruments Incorporated
-------------------------------------------------------------------
entity TMS320CENTAURUS is
generic(PHYSICAL_PIN_MAP : string := "ZWT");
port(
ddr1_a13 : inout bit;
ddr1_a14 : inout bit;
ddr1_a01 : inout bit;
ddr1_csn1 : inout bit;
ddr1_csn0 : inout bit;
ddr1_odt1 : inout bit;
ddr1_odt0 : inout bit;
ddr1_rst : inout bit;
ddr1_cke : inout bit;
ddr1_rasn : inout bit;
ddr1_casn : inout bit;
ddr1_a11 : inout bit;
ddr1_a00 : inout bit;
ddr1_a10 : inout bit;
ddr1_ba1 : inout bit;
ddr1_a07 : inout bit;
ddr1_a12 : inout bit;
ddr1_a02 : inout bit;
ddr1_a06 : inout bit;
ddr1_a09 : inout bit;
ddr1_a08 : inout bit;
ddr1_a04 : inout bit;
ddr1_a03 : inout bit;
ddr1_nck : inout bit;
ddr1_ck : inout bit;
ddr1_a05 : inout bit;
ddr1_ba0 : inout bit;
ddr1_wen : inout bit;
ddr1_ba2 : inout bit;
ddr1_dqm3 : inout bit;
ddr1_dqm2 : inout bit;
ddr1_dqm1 : inout bit;
ddr1_dqm0 : inout bit;
ddr1_dqs3 : inout bit;
ddr1_dqs2 : inout bit;
ddr1_dqs1 : inout bit;
ddr1_dqs0 : inout bit;
ddr1_d31 : inout bit;
ddr1_d30 : inout bit;
ddr1_d29 : inout bit;
ddr1_d28 : inout bit;
ddr1_d27 : inout bit;
ddr1_d26 : inout bit;
ddr1_d25 : inout bit;
ddr1_d24 : inout bit;
ddr1_d23 : inout bit;
ddr1_d22 : inout bit;
ddr1_d21 : inout bit;
ddr1_d20 : inout bit;
ddr1_d19 : inout bit;
ddr1_d18 : inout bit;
ddr1_d17 : inout bit;
ddr1_d16 : inout bit;
ddr1_d15 : inout bit;
ddr1_d14 : inout bit;
ddr1_d13 : inout bit;
ddr1_d12 : inout bit;
ddr1_d11 : inout bit;
ddr1_d10 : inout bit;
ddr1_d09 : inout bit;
ddr1_d08 : inout bit;
ddr1_d07 : inout bit;
ddr1_d06 : inout bit;
ddr1_d05 : inout bit;
ddr1_d04 : inout bit;
ddr1_d03 : inout bit;
ddr1_d02 : inout bit;
ddr1_d01 : inout bit;
ddr1_d00 : inout bit;
ddr0_a13 : inout bit;
ddr0_a14 : inout bit;
ddr0_a01 : inout bit;
ddr0_csn1 : inout bit;
ddr0_csn0 : inout bit;
ddr0_odt1 : inout bit;
ddr0_odt0 : inout bit;
ddr0_rst : inout bit;
ddr0_cke : inout bit;
ddr0_rasn : inout bit;
ddr0_casn : inout bit;
ddr0_a11 : inout bit;
ddr0_a00 : inout bit;
ddr0_a10 : inout bit;
ddr0_ba1 : inout bit;
ddr0_a07 : inout bit;
ddr0_a12 : inout bit;
ddr0_a02 : inout bit;
ddr0_a06 : inout bit;
ddr0_a09 : inout bit;
ddr0_a08 : inout bit;
ddr0_a04 : inout bit;
ddr0_a03 : inout bit;
ddr0_nck : inout bit;
ddr0_ck : inout bit;
ddr0_a05 : inout bit;
ddr0_ba0 : inout bit;
ddr0_wen : inout bit;
ddr0_ba2 : inout bit;
ddr0_dqm3 : inout bit;
ddr0_dqm2 : inout bit;
ddr0_dqm1 : inout bit;
ddr0_dqm0 : inout bit;
ddr0_dqs3 : inout bit;
ddr0_dqs2 : inout bit;
ddr0_dqs1 : inout bit;
ddr0_dqs0 : inout bit;
ddr0_d31 : inout bit;
ddr0_d30 : inout bit;
ddr0_d29 : inout bit;
ddr0_d28 : inout bit;
ddr0_d27 : inout bit;
ddr0_d26 : inout bit;
ddr0_d25 : inout bit;
ddr0_d24 : inout bit;
ddr0_d23 : inout bit;
ddr0_d22 : inout bit;
ddr0_d21 : inout bit;
ddr0_d20 : inout bit;
ddr0_d19 : inout bit;
ddr0_d18 : inout bit;
ddr0_d17 : inout bit;
ddr0_d16 : inout bit;
ddr0_d15 : inout bit;
ddr0_d14 : inout bit;
ddr0_d13 : inout bit;
ddr0_d12 : inout bit;
ddr0_d11 : inout bit;
ddr0_d10 : inout bit;
ddr0_d09 : inout bit;
ddr0_d08 : inout bit;
ddr0_d07 : inout bit;
ddr0_d06 : inout bit;
ddr0_d05 : inout bit;
ddr0_d04 : inout bit;
ddr0_d03 : inout bit;
ddr0_d02 : inout bit;
ddr0_d01 : inout bit;
ddr0_d00 : inout bit;
gmii0_txen : inout bit;
gmii0_txd7 : inout bit;
gmii0_txd6 : inout bit;
gmii0_txd5 : inout bit;
gmii0_txd4 : inout bit;
gmii0_txd3 : inout bit;
gmii0_txd2 : inout bit;
gmii0_txd1 : inout bit;
gmii0_txd0 : inout bit;
gmii0_gtxclk : inout bit;
gmii0_rxdv : inout bit;
gmii0_rxd7 : inout bit;
gmii0_rxd6 : inout bit;
gmii0_rxd5 : inout bit;
gmii0_rxd4 : inout bit;
gmii0_rxd3 : inout bit;
gmii0_rxd2 : inout bit;
gmii0_rxd1 : inout bit;
gmii0_rxclk : inout bit;
gmii0_rxer : inout bit;
gmii0_rxd0 : inout bit;
gmii0_crs : inout bit;
gmii0_col : inout bit;
gmii0_txclk : inout bit;
mdio_d : inout bit;
mdio_mclk : inout bit;
rmii_refclk : inout bit;
gpmc_cs3 : inout bit;
gpmc_cs4 : inout bit;
mmc2_dat7 : inout bit;
mmc2_dat6 : inout bit;
mmc2_dat5 : inout bit;
mmc2_dat4 : inout bit;
mmc2_dat3 : inout bit;
mmc2_dat2 : inout bit;
mmc2_clk : inout bit;
mmc2_dat1 : inout bit;
mmc2_dat0 : inout bit;
gpmc_cs0 : inout bit;
gpmc_cs1 : inout bit;
gpmc_cs2 : inout bit;
gpmc_clk : inout bit;
gpmc_advn_ale : inout bit;
gpmc_oen_ren : inout bit;
gpmc_wen : inout bit;
gpmc_ben0 : inout bit;
gpmc_ben1 : inout bit;
gpmc_wait0 : inout bit;
gpmc_ad00 : inout bit;
gpmc_ad01 : inout bit;
gpmc_ad02 : inout bit;
gpmc_ad03 : inout bit;
gpmc_ad04 : inout bit;
gpmc_ad05 : inout bit;
gpmc_ad06 : inout bit;
gpmc_ad07 : inout bit;
gpmc_ad08 : inout bit;
gpmc_ad09 : inout bit;
gpmc_ad10 : inout bit;
gpmc_ad11 : inout bit;
gpmc_ad12 : inout bit;
gpmc_ad13 : inout bit;
gpmc_ad14 : inout bit;
gpmc_ad15 : inout bit;
gpmc_a23 : inout bit;
gpmc_a22 : inout bit;
gpmc_a21 : inout bit;
gpmc_a20 : inout bit;
gpmc_a19 : inout bit;
gpmc_a18 : inout bit;
gpmc_a17 : inout bit;
gpmc_a16 : inout bit;
vout1_b_cb_c2 : inout bit;
vout1_r_cr2 : inout bit;
vout1_r_cr3 : inout bit;
vout1_g_y_yc2 : inout bit;
vout1_r_cr9 : inout bit;
vout1_r_cr8 : inout bit;
vout1_r_cr7 : inout bit;
vout1_r_cr6 : inout bit;
vout1_r_cr5 : inout bit;
vout1_r_cr4 : inout bit;
vout1_g_y_yc9 : inout bit;
vout1_g_y_yc8 : inout bit;
vout1_g_y_yc7 : inout bit;
vout1_g_y_yc6 : inout bit;
vout1_g_y_yc5 : inout bit;
vout1_g_y_yc4 : inout bit;
vout1_g_y_yc3 : inout bit;
vout1_b_cb_c9 : inout bit;
vout1_b_cb_c8 : inout bit;
vout1_b_cb_c7 : inout bit;
vout1_b_cb_c6 : inout bit;
vout1_b_cb_c5 : inout bit;
vout1_b_cb_c4 : inout bit;
vout1_b_cb_c3 : inout bit;
vout1_avid : inout bit;
vout1_vsync : inout bit;
vout1_hsync : inout bit;
vout1_clk : inout bit;
i2c1_scl : inout bit;
i2c1_sda : inout bit;
vout1_fid : inout bit;
vout1_b_cb_c0 : inout bit;
vout1_b_cb_c1 : inout bit;
vout1_r_cr0 : inout bit;
vout1_r_cr1 : inout bit;
vout1_g_y_yc0 : inout bit;
vout1_g_y_yc1 : inout bit;
vout0_fid : inout bit;
vin0_fld1 : inout bit;
vin0_fld0_mux1 : inout bit;
vin0_de1 : inout bit;
vin0_de0_mux1 : inout bit;
vin0_d23 : inout bit;
vin0_d22 : inout bit;
vin0_d21 : inout bit;
vin0_d20 : inout bit;
vin0_d19 : inout bit;
vin0_d18 : inout bit;
vin0_d17 : inout bit;
vin0_d16 : inout bit;
vin0_clk1 : inout bit;
vin0_de0_mux0 : inout bit;
vin0_fld0_mux0 : inout bit;
vin0_clk0 : inout bit;
vin0_hsync0 : inout bit;
vin0_vsync0 : inout bit;
vin0_d15 : inout bit;
vin0_d14 : inout bit;
vin0_d13 : inout bit;
vin0_d12 : inout bit;
vin0_d11 : inout bit;
vin0_d10 : inout bit;
vin0_d9 : inout bit;
vin0_d8 : inout bit;
vin0_d7 : inout bit;
vin0_d6 : inout bit;
vin0_d5 : inout bit;
vin0_d4 : inout bit;
vin0_d3 : inout bit;
vin0_d2 : inout bit;
vin0_d1 : inout bit;
vin0_d0 : inout bit;
emu1 : inout bit;
emu0 : inout bit;
vout0_clk : inout bit;
vout0_hsync : inout bit;
vout0_vsync : inout bit;
vout0_avid : inout bit;
vout0_b_cb_c2 : inout bit;
vout0_b_cb_c3 : inout bit;
vout0_b_cb_c4 : inout bit;
vout0_b_cb_c5 : inout bit;
vout0_b_cb_c6 : inout bit;
vout0_b_cb_c7 : inout bit;
vout0_b_cb_c8 : inout bit;
vout0_b_cb_c9 : inout bit;
vout0_g_y_yc2 : inout bit;
vout0_g_y_yc3 : inout bit;
vout0_g_y_yc4 : inout bit;
vout0_g_y_yc5 : inout bit;
vout0_g_y_yc6 : inout bit;
vout0_g_y_yc7 : inout bit;
vout0_g_y_yc8 : inout bit;
vout0_g_y_yc9 : inout bit;
vout0_r_cr2 : inout bit;
vout0_r_cr3 : inout bit;
vout0_r_cr4 : inout bit;
vout0_r_cr5 : inout bit;
vout0_r_cr6 : inout bit;
vout0_r_cr7 : inout bit;
vout0_r_cr8 : inout bit;
vout0_r_cr9 : inout bit;
usb_drvvbus : inout bit;
dcan0_tx : inout bit;
uart0_rxd : inout bit;
uart0_txd : inout bit;
uart0_ctsn : inout bit;
uart0_rtsn : inout bit;
uart0_dcdn : inout bit;
uart0_dsrn : inout bit;
uart0_dtrn : inout bit;
uart0_rin : inout bit;
spi0_cs1 : inout bit;
dcan0_rx : inout bit;
spi0_cs0 : inout bit;
spi0_sclk : inout bit;
spi0_d1 : inout bit;
spi0_d0 : inout bit;
spi1_cs0 : inout bit;
spi1_sclk : inout bit;
spi1_d1 : inout bit;
spi1_d0 : inout bit;
i2c0_scl : inout bit;
i2c0_sda : inout bit;
mlbp_dat_p : inout bit;
mlbp_dat_n : inout bit;
mlbp_sig_p : inout bit;
mlbp_sig_n : inout bit;
mlb_sig : inout bit;
mlb_dat : inout bit;
mlb_clk : inout bit;
osc_wake : inout bit;
mmc1_clk : inout bit;
mmc1_cmd : inout bit;
mmc1_dat0 : inout bit;
mmc1_dat1 : inout bit;
mmc1_dat2 : inout bit;
mmc1_dat3 : inout bit;
mmc0_dat3 : inout bit;
mmc0_dat2 : inout bit;
mmc0_dat1 : inout bit;
mmc0_dat0 : inout bit;
mmc0_cmd : inout bit;
mmc0_clk : inout bit;
mcasp2_clkx : inout bit;
mcasp2_fsx : inout bit;
mcasp2_axr0 : inout bit;
mcasp2_axr1 : inout bit;
mcasp2_axr2 : inout bit;
mcasp1_axr1 : inout bit;
mcasp1_axr0 : inout bit;
mcasp1_fsx : inout bit;
mcasp1_aclkx : inout bit;
mcasp1_axr3 : inout bit;
mcasp1_axr2 : inout bit;
mcasp1_fsr : inout bit;
mcasp1_clkr : inout bit;
mcasp0_axr3 : inout bit;
mcasp0_axr4 : inout bit;
mcasp0_axr5 : inout bit;
mcasp0_axr6 : inout bit;
mcasp0_axr7 : inout bit;
mcasp0_axr8 : inout bit;
mcasp0_axr9 : inout bit;
mcasp0_aclkx : inout bit;
mcasp0_fsx : inout bit;
mcasp0_clkr : inout bit;
mcasp0_axr2 : inout bit;
mcasp0_axr1 : inout bit;
mcasp0_axr0 : inout bit;
mcasp0_fsr : inout bit;
xref_clk0 : inout bit;
xref_clk1 : inout bit;
xref_clk2 : inout bit;
mcasp2_axr3 : inout bit;
mcasp5_clkx : inout bit;
mcasp5_fsx : inout bit;
mcasp5_axr0 : inout bit;
mcasp5_axr1 : inout bit;
mcasp4_axr1 : inout bit;
mcasp4_axr0 : inout bit;
mcasp4_fsx : inout bit;
mcasp4_clkx : inout bit;
mcasp3_axr3 : inout bit;
mcasp3_axr2 : inout bit;
mcasp3_axr1 : inout bit;
mcasp3_axr0 : inout bit;
mcasp3_fsx : inout bit;
mcasp3_clkx : inout bit;
resetn : inout bit;
nmin : inout bit;
rstoutn : inout bit;
clkin32 : inout bit;
mlbp_clk_p : in bit;
porz : in bit;
trstn : in bit;
tclk : in bit;
tdi : in bit;
tms : in bit;
tdo : out bit;
ddr0_dqsn0 : inout bit;
ddr0_dqsn1 : inout bit;
ddr0_dqsn2 : inout bit;
ddr0_dqsn3 : inout bit;
ddr1_dqsn0 : inout bit;
ddr1_dqsn1 : inout bit;
ddr1_dqsn2 : inout bit;
ddr1_dqsn3 : inout bit;
mlbp_clk_n : in bit;
-- Pins below had internal cell only
-- ddr0_strben3 : inout bit;
-- ddr0_strben2 : inout bit;
-- ddr0_strben1 : inout bit;
-- ddr0_strben0 : inout bit;
-- ddr1_strben3 : inout bit;
-- ddr1_strben2 : inout bit;
-- ddr1_strben1 : inout bit;
-- ddr1_strben0 : inout bit;
-- pcie_rxn0 : in bit;
-- pcie_rxp0 : in bit;
-- pcie_txp0 : out bit;
-- pcie_txn0 : out bit;
-- sata_rxn0 : in bit;
-- sata_rxp0 : in bit;
-- sata_txp0 : out bit;
-- sata_txn0 : out bit;
-- Pins below had no boundary scan cell
-- atestv : inout bit;
-- csi21_dx0 : inout bit;
-- csi21_dx1 : inout bit;
-- csi21_dx2 : inout bit;
-- csi21_dx3 : inout bit;
-- csi21_dx4 : inout bit;
-- csi21_dy0 : inout bit;
-- csi21_dy1 : inout bit;
-- csi21_dy2 : inout bit;
-- csi21_dy3 : inout bit;
-- csi21_dy4 : inout bit;
-- cvideo_rset : inout bit;
-- cvideo_tvout0 : inout bit;
-- cvideo_tvout1 : inout bit;
-- cvideo_vfb0 : inout bit;
-- cvideo_vfb1 : inout bit;
-- ddr0_vtp : inout bit;
-- ddr1_vtp : inout bit;
-- dvdd_mlbp : inout bit;
-- dvdd_mlbp : inout bit;
-- hdmi_clockx : inout bit;
-- hdmi_clocky : inout bit;
-- hdmi_data0x : inout bit;
-- hdmi_data0y : inout bit;
-- hdmi_data1x : inout bit;
-- hdmi_data1y : inout bit;
-- hdmi_data2x : inout bit;
-- hdmi_data2y : inout bit;
-- iforce : inout bit;
-- pcie_amux : inout bit;
-- rtck : inout bit;
-- sata_amux : inout bit;
-- serdes_xrefclkip : in bit;
-- serdes_xrefclkin : in bit;
-- usb0_ce : inout bit;
-- usb0_dm : inout bit;
-- usb0_dp : inout bit;
-- usb0_id : inout bit;
-- usb1_ce : inout bit;
-- usb1_dm : inout bit;
-- usb1_dp : inout bit;
-- usb_vbusin : inout bit;
-- vbiaslvds : inout bit;
-- vdd_osc : inout bit;
-- vrefddr0 : inout bit;
-- vrefddr0 : inout bit;
-- vrefddr1 : inout bit;
-- vrefddr1 : inout bit;
-- vsense : inout bit;
-- vss_osc0 : inout bit;
-- vss_osc1 : inout bit;
-- vss_serdes : inout bit;
-- xi_osc0 : inout bit;
-- xi_osc1 : inout bit;
-- xo_osc0 : inout bit;
-- xo_osc1 : inout bit;
vbbnw : linkage bit;
vbbnw_arm : linkage bit;
vbbnw_gem : linkage bit;
vbbnw_iva : linkage bit;
vdd : linkage bit_vector(21 downto 0);
vdd0 : linkage bit;
vdd_arm : linkage bit_vector(6 downto 0);
vdd_gem : linkage bit_vector(7 downto 0);
vdd_iva : linkage bit_vector(4 downto 0);
vdda18_usb0 : linkage bit;
vdda18_usb1 : linkage bit;
vdda33_usb0 : linkage bit_vector(1 downto 0);
vdda33_usb0otg : linkage bit_vector(1 downto 0);
vdda33_usb1 : linkage bit_vector(1 downto 0);
vdda33_usb1otg : linkage bit_vector(1 downto 0);
vdda_arm_pll : linkage bit;
vdda_audio : linkage bit;
vdda_avdac : linkage bit;
vdda_bandgap0 : linkage bit_vector(6 downto 0);
vdda_bandgap1 : linkage bit_vector(6 downto 0);
vdda_csi21 : linkage bit;
vdda_ddr : linkage bit;
vdda_dss : linkage bit;
vdda_gem_iva : linkage bit;
vdda_hdmi : linkage bit;
vdda_iss_l3l4 : linkage bit;
vdda_sgx : linkage bit;
vdda_video0 : linkage bit;
vdda_video1 : linkage bit;
vddram_arm : linkage bit;
vddram_core0 : linkage bit;
vddram_core1 : linkage bit;
vddram_core2 : linkage bit;
vddram_gem : linkage bit;
vddram_iva : linkage bit;
vddrx_pcie : linkage bit_vector(1 downto 0);
vddrx_sata : linkage bit_vector(1 downto 0);
vdds : linkage bit;
vdds0 : linkage bit_vector(6 downto 0);
vdds1 : linkage bit_vector(11 downto 0);
vdds18v : linkage bit_vector(6 downto 0);
vdds18v1 : linkage bit_vector(6 downto 0);
vdds18v2 : linkage bit_vector(6 downto 0);
vdds18v3 : linkage bit_vector(6 downto 0);
vdds18v4 : linkage bit_vector(6 downto 0);
vdds18v5 : linkage bit_vector(6 downto 0);
vdds2 : linkage bit_vector(11 downto 0);
vdds3 : linkage bit_vector(6 downto 0);
vdds_ldo_arm : linkage bit_vector(6 downto 0);
vdds_ldo_core0 : linkage bit_vector(6 downto 0);
vdds_ldo_core1 : linkage bit_vector(6 downto 0);
vdds_ldo_core2 : linkage bit_vector(6 downto 0);
vdds_ldo_gem : linkage bit_vector(6 downto 0);
vdds_ldo_gem_iva : linkage bit_vector(6 downto 0);
vddshv : linkage bit_vector(5 downto 0);
vddshv1 : linkage bit_vector(5 downto 0);
vddshv10 : linkage bit_vector(17 downto 0);
vddshv2 : linkage bit_vector(17 downto 0);
vddshv3 : linkage bit_vector(1 downto 0);
vddshv5 : linkage bit_vector(17 downto 0);
vddshv6 : linkage bit_vector(17 downto 0);
vddshv7 : linkage bit_vector(17 downto 0);
vddshv8 : linkage bit_vector(17 downto 0);
vddshv9 : linkage bit_vector(1 downto 0);
vddtx_pcie : linkage bit_vector(1 downto 0);
vddtx_sata : linkage bit_vector(1 downto 0);
vpp : linkage bit;
vpp1 : linkage bit;
vrefddr0 : linkage bit;
vrefddr1 : linkage bit;
vss : linkage bit_vector(96 downto 0);
vssa_audio : linkage bit_vector(94 downto 0);
vssa_avdac : linkage bit_vector(1 downto 0);
vssa_csi21 : linkage bit_vector(1 downto 0);
vssa_ddr : linkage bit_vector(94 downto 0);
vssa_dss : linkage bit_vector(94 downto 0);
vssa_gem_iva : linkage bit_vector(94 downto 0);
vssa_hdmi : linkage bit_vector(1 downto 0);
vssa_iss_l3l4 : linkage bit_vector(94 downto 0);
vssa_sgx : linkage bit_vector(94 downto 0);
vssa_usb0 : linkage bit_vector(1 downto 0);
vssa_usb1 : linkage bit_vector(1 downto 0);
vssa_video0 : linkage bit_vector(94 downto 0);
vssa_video1 : linkage bit_vector(94 downto 0);
vssd_pcie : linkage bit_vector(94 downto 0);
vssd_sata : linkage bit_vector(94 downto 0);
vsspll_pcie : linkage bit_vector(94 downto 0);
vsspll_sata : linkage bit_vector(94 downto 0);
vssrx_pcie : linkage bit_vector(94 downto 0);
vssrx_sata : linkage bit_vector(94 downto 0);
vsstx_pcie : linkage bit_vector(94 downto 0);
vsstx_sata : linkage bit_vector(94 downto 0));
use STD_1149_1_2001.all; -- Get standard attributes and definitions
attribute COMPONENT_CONFORMANCE of TMS320CENTAURUS: entity is
"STD_1149_1_2001";
attribute PIN_MAP of TMS320CENTAURUS: entity is PHYSICAL_PIN_MAP;
constant ZWT : PIN_MAP_STRING :=
"clkin32 : J7," &
"dcan0_rx : AG6," &
"dcan0_tx : AH6," &
"ddr0_a00 : B19," &
"ddr0_a01 : F19," &
"ddr0_a02 : D18," &
"ddr0_a03 : E15," &
"ddr0_a04 : D15," &
"ddr0_a05 : B17," &
"ddr0_a06 : A15," &
"ddr0_a07 : E18," &
"ddr0_a08 : B15," &
"ddr0_a09 : C15," &
"ddr0_a10 : A19," &
"ddr0_a11 : D17," &
"ddr0_a12 : E17," &
"ddr0_a13 : F17," &
"ddr0_a14 : F16," &
"ddr0_ba0 : F15," &
"ddr0_ba1 : A20," &
"ddr0_ba2 : A18," &
"ddr0_casn : C18," &
"ddr0_ck : B16," &
"ddr0_cke : H18," &
"ddr0_csn0 : F18," &
"ddr0_csn1 : G17," &
"ddr0_d00 : E27," &
"ddr0_d01 : F26," &
"ddr0_d02 : E26," &
"ddr0_d03 : F25," &
"ddr0_d04 : F24," &
"ddr0_d05 : E25," &
"ddr0_d06 : D26," &
"ddr0_d07 : C28," &
"ddr0_d08 : C27," &
"ddr0_d09 : C25," &
"ddr0_d10 : C26," &
"ddr0_d11 : A27," &
"ddr0_d12 : B25," &
"ddr0_d13 : D24," &
"ddr0_d14 : A25," &
"ddr0_d15 : A24," &
"ddr0_d16 : B24," &
"ddr0_d17 : F22," &
"ddr0_d18 : H21," &
"ddr0_d19 : G21," &
"ddr0_d20 : D23," &
"ddr0_d21 : E23," &
"ddr0_d22 : C23," &
"ddr0_d23 : B22," &
"ddr0_d24 : H20," &
"ddr0_d25 : F21," &
"ddr0_d26 : G20," &
"ddr0_d27 : A22," &
"ddr0_d28 : C20," &
"ddr0_d29 : C21," &
"ddr0_d30 : D21," &
"ddr0_d31 : B20," &
"ddr0_dqm0 : E28," &
"ddr0_dqm1 : B28," &
"ddr0_dqm2 : C24," &
"ddr0_dqm3 : F20," &
"ddr0_dqs0 : D28," &
"ddr0_dqs1 : B26," &
"ddr0_dqs2 : B23," &
"ddr0_dqs3 : B21," &
"ddr0_dqsn0 : D27," &
"ddr0_dqsn1 : A26," &
"ddr0_dqsn2 : A23," &
"ddr0_dqsn3 : A21," &
"ddr0_nck : A16," &
"ddr0_odt0 : G18," &
"ddr0_odt1 : H19," &
"ddr0_rasn : B18," &
"ddr0_rst : G19," &
"ddr0_wen : C17," &
"ddr1_a00 : B11," &
"ddr1_a01 : F10," &
"ddr1_a02 : C11," &
"ddr1_a03 : A14," &
"ddr1_a04 : B14," &
"ddr1_a05 : B12," &
"ddr1_a06 : D14," &
"ddr1_a07 : A9," &
"ddr1_a08 : E14," &
"ddr1_a09 : C14," &
"ddr1_a10 : F12," &
"ddr1_a11 : A11," &
"ddr1_a12 : B10," &
"ddr1_a13 : E11," &
"ddr1_a14 : D11," &
"ddr1_ba0 : F14," &
"ddr1_ba1 : A10," &
"ddr1_ba2 : D12," &
"ddr1_casn : F13," &
"ddr1_ck : B13," &
"ddr1_cke : H11," &
"ddr1_csn0 : G12," &
"ddr1_csn1 : G11," &
"ddr1_d00 : E3," &
"ddr1_d01 : F3," &
"ddr1_d02 : E2," &
"ddr1_d03 : E1," &
"ddr1_d04 : F5," &
"ddr1_d05 : E4," &
"ddr1_d06 : D3," &
"ddr1_d07 : C1," &
"ddr1_d08 : C2," &
"ddr1_d09 : D5," &
"ddr1_d10 : C3," &
"ddr1_d11 : A2," &
"ddr1_d12 : B4," &
"ddr1_d13 : C4," &
"ddr1_d14 : A4," &
"ddr1_d15 : A5," &
"ddr1_d16 : H8," &
"ddr1_d17 : F7," &
"ddr1_d18 : C5," &
"ddr1_d19 : B5," &
"ddr1_d20 : C6," &
"ddr1_d21 : E6," &
"ddr1_d22 : D6," &
"ddr1_d23 : B7," &
"ddr1_d24 : F9," &
"ddr1_d25 : H9," &
"ddr1_d26 : F8," &
"ddr1_d27 : A7," &
"ddr1_d28 : C9," &
"ddr1_d29 : D8," &
"ddr1_d30 : C8," &
"ddr1_d31 : B9," &
"ddr1_dqm0 : F4," &
"ddr1_dqm1 : B2," &
"ddr1_dqm2 : G8," &
"ddr1_dqm3 : G9," &
"ddr1_dqs0 : D1," &
"ddr1_dqs1 : B3," &
"ddr1_dqs2 : A6," &
"ddr1_dqs3 : B8," &
"ddr1_dqsn0 : D2," &
"ddr1_dqsn1 : A3," &
"ddr1_dqsn2 : B6," &
"ddr1_dqsn3 : A8," &
"ddr1_nck : A13," &
"ddr1_odt0 : H10," &
"ddr1_odt1 : F11," &
"ddr1_rasn : C12," &
"ddr1_rst : G10," &
"ddr1_wen : E12," &
"emu0 : AG8," &
"emu1 : AE11," &
"gmii0_col : L23," &
"gmii0_crs : R25," &
"gmii0_gtxclk : K23," &
"gmii0_rxclk : H27," &
"gmii0_rxd0 : G28," &
"gmii0_rxd1 : P23," &
"gmii0_rxd2 : R23," &
"gmii0_rxd3 : J25," &
"gmii0_rxd4 : T23," &
"gmii0_rxd5 : H26," &
"gmii0_rxd6 : F28," &
"gmii0_rxd7 : G27," &
"gmii0_rxdv : K22," &
"gmii0_rxer : J26," &
"gmii0_txclk : L24," &
"gmii0_txd0 : J24," &
"gmii0_txd1 : H25," &
"gmii0_txd2 : H22," &
"gmii0_txd3 : H23," &
"gmii0_txd4 : G23," &
"gmii0_txd5 : F27," &
"gmii0_txd6 : J22," &
"gmii0_txd7 : H24," &
"gmii0_txen : J23," &
"gpmc_a16 : AD27," &
"gpmc_a17 : V23," &
"gpmc_a18 : AE28," &
"gpmc_a19 : AC27," &
"gpmc_a20 : AD28," &
"gpmc_a21 : AC28," &
"gpmc_a22 : AB27," &
"gpmc_a23 : AA26," &
"gpmc_ad00 : U26," &
"gpmc_ad01 : Y28," &
"gpmc_ad02 : V27," &
"gpmc_ad03 : W27," &
"gpmc_ad04 : V26," &
"gpmc_ad05 : AA28," &
"gpmc_ad06 : U25," &
"gpmc_ad07 : V25," &
"gpmc_ad08 : Y27," &
"gpmc_ad09 : AB28," &
"gpmc_ad10 : Y26," &
"gpmc_ad11 : AA27," &
"gpmc_ad12 : U24," &
"gpmc_ad13 : U23," &
"gpmc_ad14 : V24," &
"gpmc_ad15 : Y25," &
"gpmc_advn_ale : M26," &
"gpmc_ben0 : U27," &
"gpmc_ben1 : V28," &
"gpmc_clk : R26," &
"gpmc_cs0 : T28," &
"gpmc_cs1 : K28," &
"gpmc_cs2 : M25," &
"gpmc_cs3 : P26," &
"gpmc_cs4 : P25," &
"gpmc_oen_ren : T27," &
"gpmc_wait0 : W28," &
"gpmc_wen : U28," &
"i2c0_scl : AC4," &
"i2c0_sda : AB6," &
"i2c1_scl : AF24," &
"i2c1_sda : AG24," &
"mcasp0_aclkx : R4," &
"mcasp0_axr0 : J2," &
"mcasp0_axr1 : J1," &
"mcasp0_axr2 : L4," &
"mcasp0_axr3 : M5," &
"mcasp0_axr4 : R6," &
"mcasp0_axr5 : M3," &
"mcasp0_axr6 : M4," &
"mcasp0_axr7 : L2," &
"mcasp0_axr8 : L1," &
"mcasp0_axr9 : M6," &
"mcasp0_clkr : K2," &
"mcasp0_fsr : K1," &
"mcasp0_fsx : L3," &
"mcasp1_aclkx : U5," &
"mcasp1_axr0 : V4," &
"mcasp1_axr1 : T6," &
"mcasp1_axr2 : R3," &
"mcasp1_axr3 : N6," &
"mcasp1_clkr : M1," &
"mcasp1_fsr : M2," &
"mcasp1_fsx : V3," &
"mcasp2_axr0 : N2," &
"mcasp2_axr1 : V6," &
"mcasp2_axr2 : V5," &
"mcasp2_axr3 : H2," &
"mcasp2_clkx : U6," &
"mcasp2_fsx : AA5," &
"mcasp3_axr0 : G1," &
"mcasp3_axr1 : G2," &
"mcasp3_axr2 : F2," &
"mcasp3_axr3 : J6," &
"mcasp3_clkx : G6," &
"mcasp3_fsx : H4," &
"mcasp4_axr0 : H6," &
"mcasp4_axr1 : J4," &
"mcasp4_clkx : K7," &
"mcasp4_fsx : H3," &
"mcasp5_axr0 : L7," &
"mcasp5_axr1 : L6," &
"mcasp5_clkx : J3," &
"mcasp5_fsx : H5," &
"mdio_d : P24," &
"mdio_mclk : H28," &
"mlb_clk : U3," &
"mlb_dat : T2," &
"mlb_sig : U4," &
"mlbp_clk_n : U2," &
"mlbp_clk_p : U1," &
"mlbp_dat_n : V2," &
"mlbp_dat_p : V1," &
"mlbp_sig_n : W2," &
"mlbp_sig_p : W1," &
"mmc0_clk : Y6," &
"mmc0_cmd : N1," &
"mmc0_dat0 : R7," &
"mmc0_dat1 : Y5," &
"mmc0_dat2 : Y3," &
"mmc0_dat3 : Y4," &
"mmc1_clk : P3," &
"mmc1_cmd : P2," &
"mmc1_dat0 : P1," &
"mmc1_dat1 : P5," &
"mmc1_dat2 : P4," &
"mmc1_dat3 : P6," &
"mmc2_clk : M23," &
"mmc2_dat0 : L26," &
"mmc2_dat1 : M24," &
"mmc2_dat2 : K27," &
"mmc2_dat3 : J28," &
"mmc2_dat4 : R24," &
"mmc2_dat5 : P22," &
"mmc2_dat6 : N23," &
"mmc2_dat7 : L25," &
"nmin : H7," &
"osc_wake : W6," &
"porz : F1," &
"resetn : J5," &
"rmii_refclk : J27," &
"rstoutn : K6," &
"spi0_cs0 : AD6," &
"spi0_cs1 : AE5," &
"spi0_d0 : AE3," &
"spi0_d1 : AF3," &
"spi0_sclk : AC7," &
"spi1_cs0 : AD3," &
"spi1_d0 : AA6," &
"spi1_d1 : AA3," &
"spi1_sclk : AC3," &
"tclk : W7," &
"tdi : Y7," &
"tdo : AC5," &
"tms : AA7," &
"trstn : AA4," &
"uart0_ctsn : AE6," &
"uart0_dcdn : AH4," &
"uart0_dsrn : AG4," &
"uart0_dtrn : AG2," &
"uart0_rin : AF4," &
"uart0_rtsn : AF5," &
"uart0_rxd : AH5," &
"uart0_txd : AG5," &
"usb_drvvbus : AF11," &
"vin0_clk0 : AB20," &
"vin0_clk1 : AE17," &
"vin0_d0 : AF9," &
"vin0_d1 : AB11," &
"vin0_d10 : AH9," &
"vin0_d11 : AH17," &
"vin0_d12 : AG17," &
"vin0_d13 : AF17," &
"vin0_d14 : AC12," &
"vin0_d15 : AC14," &
"vin0_d16 : AA21," &
"vin0_d17 : AB21," &
"vin0_d18 : AF20," &
"vin0_d19 : AF21," &
"vin0_d2 : AC9," &
"vin0_d20 : AC17," &
"vin0_d21 : AE18," &
"vin0_d22 : AC21," &
"vin0_d23 : AC16," &
"vin0_d3 : AE12," &
"vin0_d4 : AH8," &
"vin0_d5 : AG16," &
"vin0_d6 : AH16," &
"vin0_d7 : AA11," &
"vin0_d8 : AB15," &
"vin0_d9 : AG9," &
"vin0_de0_mux0 : AE21," &
"vin0_de0_mux1 : AB17," &
"vin0_de1 : AC15," &
"vin0_fld0_mux0 : AA20," &
"vin0_fld0_mux1 : AC22," &
"vin0_fld1 : AD17," &
"vin0_hsync0 : AC20," &
"vin0_vsync0 : AD20," &
"vout0_avid : AA10," &
"vout0_b_cb_c2 : AG7," &
"vout0_b_cb_c3 : AE15," &
"vout0_b_cb_c4 : AD11," &
"vout0_b_cb_c5 : AD15," &
"vout0_b_cb_c6 : AC10," &
"vout0_b_cb_c7 : AB10," &
"vout0_b_cb_c8 : AF15," &
"vout0_b_cb_c9 : AG15," &
"vout0_clk : AD12," &
"vout0_fid : AF18," &
"vout0_g_y_yc2 : AH7," &
"vout0_g_y_yc3 : AH15," &
"vout0_g_y_yc4 : AB8," &
"vout0_g_y_yc5 : AB12," &
"vout0_g_y_yc6 : AA8," &
"vout0_g_y_yc7 : AD14," &
"vout0_g_y_yc8 : AE14," &
"vout0_g_y_yc9 : AF14," &
"vout0_hsync : AC11," &
"vout0_r_cr2 : AD9," &
"vout0_r_cr3 : AB9," &
"vout0_r_cr4 : AA9," &
"vout0_r_cr5 : AF8," &
"vout0_r_cr6 : AF6," &
"vout0_r_cr7 : AF12," &
"vout0_r_cr8 : AE8," &
"vout0_r_cr9 : AC13," &
"vout0_vsync : AB13," &
"vout1_avid : Y22," &
"vout1_b_cb_c0 : AD23," &
"vout1_b_cb_c1 : AE23," &
"vout1_b_cb_c2 : AF28," &
"vout1_b_cb_c3 : AH25," &
"vout1_b_cb_c4 : AG25," &
"vout1_b_cb_c5 : AF25," &
"vout1_b_cb_c6 : AD25," &
"vout1_b_cb_c7 : AC25," &
"vout1_b_cb_c8 : AH26," &
"vout1_b_cb_c9 : AA24," &
"vout1_clk : AE24," &
"vout1_fid : AB23," &
"vout1_g_y_yc0 : AC18," &
"vout1_g_y_yc1 : AD18," &
"vout1_g_y_yc2 : AF27," &
"vout1_g_y_yc3 : Y23," &
"vout1_g_y_yc4 : W22," &
"vout1_g_y_yc5 : AG26," &
"vout1_g_y_yc6 : AH27," &
"vout1_g_y_yc7 : AF26," &
"vout1_g_y_yc8 : AE26," &
"vout1_g_y_yc9 : AD26," &
"vout1_hsync : AC24," &
"vout1_r_cr0 : AA22," &
"vout1_r_cr1 : AC19," &
"vout1_r_cr2 : AE27," &
"vout1_r_cr3 : AG28," &
"vout1_r_cr4 : AG27," &
"vout1_r_cr5 : AC26," &
"vout1_r_cr6 : AA25," &
"vout1_r_cr7 : V22," &
"vout1_r_cr8 : W23," &
"vout1_r_cr9 : Y24," &
"vout1_vsync : AA23," &
"xref_clk0 : L5," &
"xref_clk1 : R5," &
"xref_clk2 : H1," &
-- "atestv0 : AD8," &
-- "atestv1 : AD8," &
-- "atestv2 : AD8," &
-- "atestv3 : AD8," &
-- "atestv5 : AD8," &
-- "atestv6 : AD8," &
-- "csi21_dx0 : L27," &
-- "csi21_dx1 : M27," &
-- "csi21_dx2 : N28," &
-- "csi21_dx3 : P28," &
-- "csi21_dx4 : R27," &
-- "csi21_dy0 : L28," &
-- "csi21_dy1 : M28," &
-- "csi21_dy2 : N27," &
-- "csi21_dy3 : P27," &
-- "csi21_dy4 : R28," &
-- "cvideo_rset : AH23," &
-- "cvideo_tvout0 : AH24," &
-- "cvideo_tvout1 : AH22," &
-- "cvideo_vfb0 : AG23," &
-- "cvideo_vfb1 : AG22," &
-- "ddr0_vtp : B27," &
-- "ddr1_vtp : B1," &
-- "hdmi_clockx : AH21," &
-- "hdmi_clocky : AG21," &
-- "hdmi_data0x : AH20," &
-- "hdmi_data0y : AG20," &
-- "hdmi_data1x : AH19," &
-- "hdmi_data1y : AG19," &
-- "hdmi_data2x : AH18," &
-- "hdmi_data2y : AG18," &
-- "rtck : AD4," &
-- "sata_amux : U8," &
-- "sata_rxn0 : AA2," &
-- "sata_rxp0 : AA1," &
-- "sata_txn0 : AB1," &
-- "sata_txp0 : AB2," &
-- "serdes_xrefclkin : AF2," &
-- "serdes_xrefclkip : AF1," &
-- "pcie_amux : V8," &
-- "pcie_rxn0 : AC1," &
-- "pcie_rxp0 : AC2," &
-- "pcie_txn0 : AD1," &
-- "pcie_txp0 : AD2," &
-- "usb0_ce : AH10," &
-- "usb0_dm : AH11," &
-- "usb0_dp : AG11," &
-- "usb0_id : AG10," &
-- "usb1_ce : AH14," &
-- "usb1_dm : AH13," &
-- "usb1_dp : AG13," &
-- "usb1_id : AH12," &
-- "usb_vbusin : AG12," &
-- "usb1_vbusin : AG14," &
-- "xi_osc0 : AH2," &
-- "xi_osc1 : R1," &
-- "xo_osc0 : AH3," &
-- "xo_osc1 : T1," &
"vbbnw : (T10)," &
"vbbnw_arm : (W14)," &
"vbbnw_gem : (P10)," &
"vbbnw_iva : (N10)," &
"vdd : (K12,K18,K9,L15,L17,L19,M16,M18,N17,N19,P12,P14,P16,R15,R17,R19,T12,U11,U13,U17,U19,W11)," &
"vdd0 : (T11)," &
"vdd_arm : (T14,T15,T16,U15,U16,V15,V16)," &
"vdd_gem : (K10,L10,L11,L12,L9,M10,M12,N9)," &
"vdd_iva : (L14,M13,M14,N13,N14)," &
"vdda18_usb0 : (AA12)," &
"vdda18_usb1 : (W13)," &
"vdda33_usb0 : (AA13,AF13)," &
"vdda_arm_pll : (R13)," &
"vdda_audio : (R18)," &
"vdda_avdac : (AB19)," &
"vdda_bandgap0 : (L20,M7,R20,U7,V10,W15,Y13)," &
"vdda_csi21 : (M22)," &
"vdda_ddr : (H15)," &
"vdda_dss : (N18)," &
"vdda_gem_iva : (P11)," &
"vdda_hdmi : (W18)," &
"vdda_video0 : (AB18)," &
"vdda_video1 : (AA18)," &
"vddram_arm : (V14)," &
"vddram_core0 : (P18)," &
"vddram_core1 : (R11)," &
"vddram_core2 : (L18)," &
"vddram_gem : (M11)," &
"vddram_iva : (N11)," &
"vddrx_pcie : (W10,W9)," &
"vddrx_sata : (U10,U9)," &
"vdds : (R10)," &
"vdds1 : (C10,C13,D4,E8,E9,G13,H12,H13,H14,J10,J11,J13)," &
"vdds2 : (C16,C19,D25,E20,E21,G16,H16,H17,J15,J16,J17,J18)," &
"vddshv : (K20,L21,M20,P20,T20,W26)," &
"vddshv3 : (W19,W20)," &
"vddshv9 : (P7,P9)," &
"vddshv10 : (AA15,AA17,AB14,AB16,AE25,AE4,AF7,K3,M8,N7,P8,T7,U21,U22,V20,W3,Y11,Y16)," &
"vpp : (AC8)," &
"vpp1 : (Y14)," &
"vrefddr0 : (G15)," &
"vrefddr1 : (G14)," &
"vss : (A1,A12,A17,A28,AA14,AA16,AB26,AB3,AD21,AE1,AE2,AE20,AE9,AF10,AF16,AF23,AG1,AG3,AH1,AH28,C22,C7,D20,D9,G26,G3,J12,J14,J19,K11,K13,K14,K15,K16,K17,K19,K26,L13,L16,L22,L8,M15,M17,M19,M21,M9,N12,N15,N16,N20,N21,N3,N8,P13,P15,P17,P19,P21,R12,R14,R16,R2,R21,R22,R8,R9,T13,T17,T18,T19,T21,T22,T26,T3,T8,T9,U12,U14,U18,U20,V11,V17,V19,V21,V7,V9,W12,W16,W17,Y1,Y10,Y12,Y15,Y17,Y18,Y19,Y2)," &
"vssa_avdac : (AA19,AF22)," &
"vssa_csi21 : (N22,N26)," &
"vssa_hdmi : (AF19,V18)," &
"vssa_usb0 : (V12,V13)" ;
-- "vdda_bandgap1 : (L20,M7,R20,U7,V10,W15,Y13)," &
-- "vdda33_usb0otg : (AA13,AF13)," &
-- "vdda33_usb1 : (AA13,AF13)," &
-- "vdda33_usb1otg : (AA13,AF13)," &
-- "vdda_iss_l3l4 : (N18)," &
-- "vdda_sgx : (R13)," &
-- "vdds0 : (L20,M7,R20,U7,V10,W15,Y13)," &
-- "vdds18v : (L20,M7,R20,U7,V10,W15,Y13)," &
-- "vdds18v1 : (L20,M7,R20,U7,V10,W15,Y13)," &
-- "vdds18v2 : (L20,M7,R20,U7,V10,W15,Y13)," &
-- "vdds18v3 : (L20,M7,R20,U7,V10,W15,Y13)," &
-- "vdds18v4 : (L20,M7,R20,U7,V10,W15,Y13)," &
-- "vdds18v5 : (L20,M7,R20,U7,V10,W15,Y13)," &
-- "vdds3 : (L20,M7,R20,U7,V10,W15,Y13)," &
-- "vdds_ldo_arm : (L20,M7,R20,U7,V10,W15,Y13)," &
-- "vdds_ldo_core0 : (L20,M7,R20,U7,V10,W15,Y13)," &
-- "vdds_ldo_core1 : (L20,M7,R20,U7,V10,W15,Y13)," &
-- "vdds_ldo_core2 : (L20,M7,R20,U7,V10,W15,Y13)," &
-- "vdds_ldo_gem : (L20,M7,R20,U7,V10,W15,Y13)," &
-- "vdds_ldo_gem_iva : (L20,M7,R20,U7,V10,W15,Y13)," &
-- "vddshv1 : (K20,L21,M20,P20,T20,W26)," &
-- "vddshv2 : (AA15,AA17,AB14,AB16,AE25,AE4,AF7,K3,M8,N7,P8,T7,U21,U22,V20,W3,Y11,Y16)," &
-- "vddshv5 : (AA15,AA17,AB14,AB16,AE25,AE4,AF7,K3,M8,N7,P8,T7,U21,U22,V20,W3,Y11,Y16)," &
-- "vddshv6 : (AA15,AA17,AB14,AB16,AE25,AE4,AF7,K3,M8,N7,P8,T7,U21,U22,V20,W3,Y11,Y16)," &
-- "vddshv7 : (AA15,AA17,AB14,AB16,AE25,AE4,AF7,K3,M8,N7,P8,T7,U21,U22,V20,W3,Y11,Y16)," &
-- "vddshv8 : (AA15,AA17,AB14,AB16,AE25,AE4,AF7,K3,M8,N7,P8,T7,U21,U22,V20,W3,Y11,Y16)," &
-- "vddtx_pcie : (W10,W9)," &
-- "vddtx_sata : (U10,U9)," &
-- "vssa_audio : (A1,A12,A17,A28,AA14,AA16,AB26,AB3,AD21,AE1,AE2,AE20,AE9,AF10,AF16,AF23,AG1,AH1,AH28,C22,C7,D20,D9,G26,G3,J12,J14,J19,K11,K13,K14,K15,K16,K17,K19,K26,L13,L16,L22,L8,M15,M17,M19,M21,M9,N12,N15,N16,N20,N21,N3,N8,P13,P15,P17,P19,P21,R12,R14,R16,R21,R22,R8,R9,T13,T17,T18,T19,T21,T22,T26,T3,T8,T9,U12,U14,U18,U20,V11,V17,V19,V21,V7,V9,W12,W16,W17,Y1,Y10,Y12,Y15,Y17,Y18,Y19,Y2)," &
-- "vssa_ddr : (A1,A12,A17,A28,AA14,AA16,AB26,AB3,AD21,AE1,AE2,AE20,AE9,AF10,AF16,AF23,AG1,AH1,AH28,C22,C7,D20,D9,G26,G3,J12,J14,J19,K11,K13,K14,K15,K16,K17,K19,K26,L13,L16,L22,L8,M15,M17,M19,M21,M9,N12,N15,N16,N20,N21,N3,N8,P13,P15,P17,P19,P21,R12,R14,R16,R21,R22,R8,R9,T13,T17,T18,T19,T21,T22,T26,T3,T8,T9,U12,U14,U18,U20,V11,V17,V19,V21,V7,V9,W12,W16,W17,Y1,Y10,Y12,Y15,Y17,Y18,Y19,Y2)," &
-- "vssa_dss : (A1,A12,A17,A28,AA14,AA16,AB26,AB3,AD21,AE1,AE2,AE20,AE9,AF10,AF16,AF23,AG1,AH1,AH28,C22,C7,D20,D9,G26,G3,J12,J14,J19,K11,K13,K14,K15,K16,K17,K19,K26,L13,L16,L22,L8,M15,M17,M19,M21,M9,N12,N15,N16,N20,N21,N3,N8,P13,P15,P17,P19,P21,R12,R14,R16,R21,R22,R8,R9,T13,T17,T18,T19,T21,T22,T26,T3,T8,T9,U12,U14,U18,U20,V11,V17,V19,V21,V7,V9,W12,W16,W17,Y1,Y10,Y12,Y15,Y17,Y18,Y19,Y2)," &
-- "vssa_gem_iva : (A1,A12,A17,A28,AA14,AA16,AB26,AB3,AD21,AE1,AE2,AE20,AE9,AF10,AF16,AF23,AG1,AH1,AH28,C22,C7,D20,D9,G26,G3,J12,J14,J19,K11,K13,K14,K15,K16,K17,K19,K26,L13,L16,L22,L8,M15,M17,M19,M21,M9,N12,N15,N16,N20,N21,N3,N8,P13,P15,P17,P19,P21,R12,R14,R16,R21,R22,R8,R9,T13,T17,T18,T19,T21,T22,T26,T3,T8,T9,U12,U14,U18,U20,V11,V17,V19,V21,V7,V9,W12,W16,W17,Y1,Y10,Y12,Y15,Y17,Y18,Y19,Y2)," &
-- "vssa_iss_l3l4 : (A1,A12,A17,A28,AA14,AA16,AB26,AB3,AD21,AE1,AE2,AE20,AE9,AF10,AF16,AF23,AG1,AH1,AH28,C22,C7,D20,D9,G26,G3,J12,J14,J19,K11,K13,K14,K15,K16,K17,K19,K26,L13,L16,L22,L8,M15,M17,M19,M21,M9,N12,N15,N16,N20,N21,N3,N8,P13,P15,P17,P19,P21,R12,R14,R16,R21,R22,R8,R9,T13,T17,T18,T19,T21,T22,T26,T3,T8,T9,U12,U14,U18,U20,V11,V17,V19,V21,V7,V9,W12,W16,W17,Y1,Y10,Y12,Y15,Y17,Y18,Y19,Y2)," &
-- "vssa_sgx : (A1,A12,A17,A28,AA14,AA16,AB26,AB3,AD21,AE1,AE2,AE20,AE9,AF10,AF16,AF23,AG1,AH1,AH28,C22,C7,D20,D9,G26,G3,J12,J14,J19,K11,K13,K14,K15,K16,K17,K19,K26,L13,L16,L22,L8,M15,M17,M19,M21,M9,N12,N15,N16,N20,N21,N3,N8,P13,P15,P17,P19,P21,R12,R14,R16,R21,R22,R8,R9,T13,T17,T18,T19,T21,T22,T26,T3,T8,T9,U12,U14,U18,U20,V11,V17,V19,V21,V7,V9,W12,W16,W17,Y1,Y10,Y12,Y15,Y17,Y18,Y19,Y2)," &
-- "vssa_video0 : (A1,A12,A17,A28,AA14,AA16,AB26,AB3,AD21,AE1,AE2,AE20,AE9,AF10,AF16,AF23,AG1,AH1,AH28,C22,C7,D20,D9,G26,G3,J12,J14,J19,K11,K13,K14,K15,K16,K17,K19,K26,L13,L16,L22,L8,M15,M17,M19,M21,M9,N12,N15,N16,N20,N21,N3,N8,P13,P15,P17,P19,P21,R12,R14,R16,R21,R22,R8,R9,T13,T17,T18,T19,T21,T22,T26,T3,T8,T9,U12,U14,U18,U20,V11,V17,V19,V21,V7,V9,W12,W16,W17,Y1,Y10,Y12,Y15,Y17,Y18,Y19,Y2)," &
-- "vssa_video1 : (A1,A12,A17,A28,AA14,AA16,AB26,AB3,AD21,AE1,AE2,AE20,AE9,AF10,AF16,AF23,AG1,AH1,AH28,C22,C7,D20,D9,G26,G3,J12,J14,J19,K11,K13,K14,K15,K16,K17,K19,K26,L13,L16,L22,L8,M15,M17,M19,M21,M9,N12,N15,N16,N20,N21,N3,N8,P13,P15,P17,P19,P21,R12,R14,R16,R21,R22,R8,R9,T13,T17,T18,T19,T21,T22,T26,T3,T8,T9,U12,U14,U18,U20,V11,V17,V19,V21,V7,V9,W12,W16,W17,Y1,Y10,Y12,Y15,Y17,Y18,Y19,Y2)," &
-- "vssd_pcie : (A1,A12,A17,A28,AA14,AA16,AB26,AB3,AD21,AE1,AE2,AE20,AE9,AF10,AF16,AF23,AG1,AH1,AH28,C22,C7,D20,D9,G26,G3,J12,J14,J19,K11,K13,K14,K15,K16,K17,K19,K26,L13,L16,L22,L8,M15,M17,M19,M21,M9,N12,N15,N16,N20,N21,N3,N8,P13,P15,P17,P19,P21,R12,R14,R16,R21,R22,R8,R9,T13,T17,T18,T19,T21,T22,T26,T3,T8,T9,U12,U14,U18,U20,V11,V17,V19,V21,V7,V9,W12,W16,W17,Y1,Y10,Y12,Y15,Y17,Y18,Y19,Y2)," &
-- "vssd_sata : (A1,A12,A17,A28,AA14,AA16,AB26,AB3,AD21,AE1,AE2,AE20,AE9,AF10,AF16,AF23,AG1,AH1,AH28,C22,C7,D20,D9,G26,G3,J12,J14,J19,K11,K13,K14,K15,K16,K17,K19,K26,L13,L16,L22,L8,M15,M17,M19,M21,M9,N12,N15,N16,N20,N21,N3,N8,P13,P15,P17,P19,P21,R12,R14,R16,R21,R22,R8,R9,T13,T17,T18,T19,T21,T22,T26,T3,T8,T9,U12,U14,U18,U20,V11,V17,V19,V21,V7,V9,W12,W16,W17,Y1,Y10,Y12,Y15,Y17,Y18,Y19,Y2)," &
-- "vsspll_pcie : (A1,A12,A17,A28,AA14,AA16,AB26,AB3,AD21,AE1,AE2,AE20,AE9,AF10,AF16,AF23,AG1,AH1,AH28,C22,C7,D20,D9,G26,G3,J12,J14,J19,K11,K13,K14,K15,K16,K17,K19,K26,L13,L16,L22,L8,M15,M17,M19,M21,M9,N12,N15,N16,N20,N21,N3,N8,P13,P15,P17,P19,P21,R12,R14,R16,R21,R22,R8,R9,T13,T17,T18,T19,T21,T22,T26,T3,T8,T9,U12,U14,U18,U20,V11,V17,V19,V21,V7,V9,W12,W16,W17,Y1,Y10,Y12,Y15,Y17,Y18,Y19,Y2)," &
-- "vsspll_sata : (A1,A12,A17,A28,AA14,AA16,AB26,AB3,AD21,AE1,AE2,AE20,AE9,AF10,AF16,AF23,AG1,AH1,AH28,C22,C7,D20,D9,G26,G3,J12,J14,J19,K11,K13,K14,K15,K16,K17,K19,K26,L13,L16,L22,L8,M15,M17,M19,M21,M9,N12,N15,N16,N20,N21,N3,N8,P13,P15,P17,P19,P21,R12,R14,R16,R21,R22,R8,R9,T13,T17,T18,T19,T21,T22,T26,T3,T8,T9,U12,U14,U18,U20,V11,V17,V19,V21,V7,V9,W12,W16,W17,Y1,Y10,Y12,Y15,Y17,Y18,Y19,Y2)," &
-- "vssrx_pcie : (A1,A12,A17,A28,AA14,AA16,AB26,AB3,AD21,AE1,AE2,AE20,AE9,AF10,AF16,AF23,AG1,AH1,AH28,C22,C7,D20,D9,G26,G3,J12,J14,J19,K11,K13,K14,K15,K16,K17,K19,K26,L13,L16,L22,L8,M15,M17,M19,M21,M9,N12,N15,N16,N20,N21,N3,N8,P13,P15,P17,P19,P21,R12,R14,R16,R21,R22,R8,R9,T13,T17,T18,T19,T21,T22,T26,T3,T8,T9,U12,U14,U18,U20,V11,V17,V19,V21,V7,V9,W12,W16,W17,Y1,Y10,Y12,Y15,Y17,Y18,Y19,Y2)," &
-- "vssrx_sata : (A1,A12,A17,A28,AA14,AA16,AB26,AB3,AD21,AE1,AE2,AE20,AE9,AF10,AF16,AF23,AG1,AH1,AH28,C22,C7,D20,D9,G26,G3,J12,J14,J19,K11,K13,K14,K15,K16,K17,K19,K26,L13,L16,L22,L8,M15,M17,M19,M21,M9,N12,N15,N16,N20,N21,N3,N8,P13,P15,P17,P19,P21,R12,R14,R16,R21,R22,R8,R9,T13,T17,T18,T19,T21,T22,T26,T3,T8,T9,U12,U14,U18,U20,V11,V17,V19,V21,V7,V9,W12,W16,W17,Y1,Y10,Y12,Y15,Y17,Y18,Y19,Y2)," &
-- "vsstx_pcie : (A1,A12,A17,A28,AA14,AA16,AB26,AB3,AD21,AE1,AE2,AE20,AE9,AF10,AF16,AF23,AG1,AH1,AH28,C22,C7,D20,D9,G26,G3,J12,J14,J19,K11,K13,K14,K15,K16,K17,K19,K26,L13,L16,L22,L8,M15,M17,M19,M21,M9,N12,N15,N16,N20,N21,N3,N8,P13,P15,P17,P19,P21,R12,R14,R16,R21,R22,R8,R9,T13,T17,T18,T19,T21,T22,T26,T3,T8,T9,U12,U14,U18,U20,V11,V17,V19,V21,V7,V9,W12,W16,W17,Y1,Y10,Y12,Y15,Y17,Y18,Y19,Y2)," &
-- "vsstx_sata : (A1,A12,A17,A28,AA14,AA16,AB26,AB3,AD21,AE1,AE2,AE20,AE9,AF10,AF16,AF23,AG1,AH1,AH28,C22,C7,D20,D9,G26,G3,J12,J14,J19,K11,K13,K14,K15,K16,K17,K19,K26,L13,L16,L22,L8,M15,M17,M19,M21,M9,N12,N15,N16,N20,N21,N3,N8,P13,P15,P17,P19,P21,R12,R14,R16,R21,R22,R8,R9,T13,T17,T18,T19,T21,T22,T26,T3,T8,T9,U12,U14,U18,U20,V11,V17,V19,V21,V7,V9,W12,W16,W17,Y1,Y10,Y12,Y15,Y17,Y18,Y19,Y2)" ;
-- "vssa_usb1 : (V12,V13)," &
attribute PORT_GROUPING of TMS320CENTAURUS : entity is
"Differential_Voltage ((ddr0_dqs0,ddr0_dqsn0)," &
"(ddr0_dqs1,ddr0_dqsn1)," &
"(ddr0_dqs2,ddr0_dqsn2)," &
"(ddr0_dqs3,ddr0_dqsn3)," &
"(ddr1_dqs0,ddr1_dqsn0)," &
"(ddr1_dqs1,ddr1_dqsn1)," &
"(ddr1_dqs2,ddr1_dqsn2)," &
"(ddr1_dqs3,ddr1_dqsn3)," &
"(ddr1_ck,ddr1_nck)," &
"(ddr0_ck,ddr0_nck)," &
"(mlbp_clk_p,mlbp_clk_n))";
-- *********************************************************
attribute TAP_SCAN_IN of tdi : signal is true;
attribute TAP_SCAN_MODE of tms : signal is true;
attribute TAP_SCAN_OUT of tdo : signal is true;
attribute TAP_SCAN_RESET of trstn : signal is true;
attribute TAP_SCAN_CLOCK of tclk : signal is (20.00e6, BOTH);
attribute COMPLIANCE_PATTERNS of TMS320CENTAURUS: entity is "(porz)(1)";
attribute INSTRUCTION_LENGTH of TMS320CENTAURUS: entity is 6;
attribute INSTRUCTION_OPCODE of TMS320CENTAURUS: entity is
"EXTEST (100100), " &
"IDCODE (000100), " &
"BYPASS (111111), " &
"SAMPLE (011011), " &
"PRELOAD (011100), " &
"PRIVATE (000000, " &
" 011110, " &
" 000001, " &
" 000010, " &
" 000011, " &
" 000101, " &
" 000110, " &
" 000111, " &
" 001000, " &
" 001001, " &
" 001010, " &
" 001011, " &
" 001100, " &
" 001101, " &
" 001110, " &
" 001111, " &
" 010000, " &
" 010001, " &
" 010010, " &
" 010011, " &
" 010100, " &
" 010101, " &
" 010110, " &
" 010111, " &
" 011001, " &
" 011010, " &
" 011101, " &
" 011111, " &
" 100000, " &
" 100001, " &
" 100010, " &
" 100011, " &
" 011000, " &
" 100101, " &
" 100110, " &
" 100111, " &
" 101000, " &
" 101001, " &
" 101010, " &
" 101011, " &
" 101100, " &
" 101101, " &
" 101110, " &
" 101111, " &
" 110000, " &
" 110001, " &
" 110010, " &
" 110011, " &
" 110100, " &
" 110101, " &
" 110110, " &
" 110111, " &
" 111000, " &
" 111001, " &
" 111010, " &
" 111011, " &
" 111100, " &
" 111101, " &
" 111110) " ;
attribute INSTRUCTION_CAPTURE of TMS320CENTAURUS: entity is "XXXX01";
attribute INSTRUCTION_PRIVATE of TMS320CENTAURUS: entity is "PRIVATE";
attribute IDCODE_REGISTER of TMS320CENTAURUS: entity is
"0000" & -- Version number
"1011100011110010" & -- Part number -- CENTAURUS pin package ID
"00000010111" & -- Manufacturer ID -- Texas Instruments
"1"; -- Required by IEEE Std.
attribute REGISTER_ACCESS of TMS320CENTAURUS: entity is
"BOUNDARY (EXTEST, SAMPLE, PRELOAD)," &
"BYPASS (BYPASS ) " ;
attribute BOUNDARY_LENGTH of TMS320CENTAURUS: entity is 1191;
attribute BOUNDARY_REGISTER of TMS320CENTAURUS: entity is
--- num cell port function safe ccell disval rslt
"0 (bc_1, *,internal, X)," &
"1 (bc_1, *, internal, X)," &
"2 (bc_1, *, internal, X )," &
"3 (bc_4, *, internal, X )," &
"4 (bc_1, *, internal, X)," &
"5 (bc_1, *, internal, X)," &
"6 (bc_1, *, internal, X )," &
"7 (bc_4, *, internal, X )," &
"8 (bc_1, *, internal, X)," &
"9 (bc_1, mlbp_clk_p, input, X)," &
"10 (bc_1, ddr1_a13, input, X)," &
"11 (bc_1, ddr1_a13, output3, X, 28, 1, Z)," &
"12 (bc_1, ddr1_a14, input, X)," &
"13 (bc_1, ddr1_a14, output3, X, 28, 1, Z)," &
"14 (bc_1, ddr1_a01, input, X)," &
"15 (bc_1, ddr1_a01, output3, X, 28, 1, Z)," &
"16 (bc_1, ddr1_csn1, input, X)," &
"17 (bc_1, ddr1_csn1, output3, X, 28, 1, Z)," &
"18 (bc_1, ddr1_csn0, input, X)," &
"19 (bc_1, ddr1_csn0, output3, X, 28, 1, Z)," &
"20 (bc_1, ddr1_odt1, input, X)," &
"21 (bc_1, ddr1_odt1, output3, X, 28, 1, Z)," &
"22 (bc_1, ddr1_odt0, input, X)," &
"23 (bc_1, ddr1_odt0, output3, X, 28, 1, Z)," &
"24 (bc_1, ddr1_rst, input, X)," &
"25 (bc_1, ddr1_rst, output3, X, 28, 1, Z)," &
"26 (bc_1, ddr1_cke, input, X)," &
"27 (bc_1, ddr1_cke, output3, X, 28, 1, Z)," &
"28 (bc_1, *, control, 1)," &
"29 (bc_1, ddr1_rasn, input, X)," &
"30 (bc_1, ddr1_rasn, output3, X, 47, 1, Z)," &
"31 (bc_1, ddr1_casn, input, X)," &
"32 (bc_1, ddr1_casn, output3, X, 47, 1, Z)," &
"33 (bc_1, ddr1_a11, input, X)," &
"34 (bc_1, ddr1_a11, output3, X, 47, 1, Z)," &
"35 (bc_1, ddr1_a00, input, X)," &
"36 (bc_1, ddr1_a00, output3, X, 47, 1, Z)," &
"37 (bc_1, ddr1_a10, input, X)," &
"38 (bc_1, ddr1_a10, output3, X, 47, 1, Z)," &
"39 (bc_1, ddr1_ba1, input, X)," &
"40 (bc_1, ddr1_ba1, output3, X, 47, 1, Z)," &
"41 (bc_1, ddr1_a07, input, X)," &
"42 (bc_1, ddr1_a07, output3, X, 47, 1, Z)," &
"43 (bc_1, ddr1_a12, input, X)," &
"44 (bc_1, ddr1_a12, output3, X, 47, 1, Z)," &
"45 (bc_1, ddr1_a02, input, X)," &
"46 (bc_1, ddr1_a02, output3, X, 47, 1, Z)," &
"47 (bc_1, *, control, 1)," &
"48 (bc_1, ddr1_a06, input, X)," &
"49 (bc_1, ddr1_a06, output3, X, 70, 1, Z)," &
"50 (bc_1, ddr1_a09, input, X)," &
"51 (bc_1, ddr1_a09, output3, X, 70, 1, Z)," &
"52 (bc_1, ddr1_a08, input, X)," &
"53 (bc_1, ddr1_a08, output3, X, 70, 1, Z)," &
"54 (bc_1, ddr1_a04, input, X)," &
"55 (bc_1, ddr1_a04, output3, X, 70, 1, Z)," &
"56 (bc_1, ddr1_a03, input, X)," &
"57 (bc_1, ddr1_a03, output3, X, 70, 1, Z)," &
"58 (bc_4, *, internal, X)," &
"59 (bc_4, *, internal, X )," &
"60 (bc_1, ddr1_ck, input, X)," &
"61 (bc_1, ddr1_ck, output3, X, 70, 1, Z)," &
"62 (bc_1, ddr1_a05, input, X)," &
"63 (bc_1, ddr1_a05, output3, X, 70, 1, Z)," &
"64 (bc_1, ddr1_ba0, input, X)," &
"65 (bc_1, ddr1_ba0, output3, X, 70, 1, Z)," &
"66 (bc_1, ddr1_wen, input, X)," &
"67 (bc_1, ddr1_wen, output3, X, 70, 1, Z)," &
"68 (bc_1, ddr1_ba2, input, X)," &
"69 (bc_1, ddr1_ba2, output3, X, 70, 1, Z)," &
"70 (bc_1, *, control, 1)," &
"71 (bc_4, *, internal, X )," &
"72 (bc_4, *, internal, X )," &
"73 (bc_4, *, internal, X )," &
"74 (bc_4, *, internal, X )," &
"75 (bc_4, *, internal, X )," &
"76 (bc_4, *, internal, X )," &
"77 (bc_4, *, internal, X )," &
"78 (bc_4, *, internal, X )," &
"79 (bc_4, *, internal, X )," &
"80 (bc_4, *, internal, X )," &
"81 (bc_4, *, internal, X )," &
"82 (bc_4, *, internal, X )," &
"83 (bc_1, ddr1_dqm3, input, X)," &
"84 (bc_1, ddr1_dqm3, output3, X, 85, 1, Z)," &
"85 (bc_1, *, control, 1)," &
"86 (bc_1, ddr1_dqm2, input, X)," &
"87 (bc_1, ddr1_dqm2, output3, X, 88, 1, Z)," &
"88 (bc_1, *, control, 1)," &
"89 (bc_1, ddr1_dqm1, input, X)," &
"90 (bc_1, ddr1_dqm1, output3, X, 91, 1, Z)," &
"91 (bc_1, *, control, 1)," &
"92 (bc_1, ddr1_dqm0, input, X)," &
"93 (bc_1, ddr1_dqm0, output3, X, 94, 1, Z)," &
"94 (bc_1, *, control, 1)," &
"95 (bc_1, ddr1_dqs3, input, X)," &
"96 (bc_1, ddr1_dqs3, output3, X, 97, 1, Z)," &
"97 (bc_1, *, control, 1)," &
"98 (bc_1, ddr1_dqs2, input, X)," &
"99 (bc_1, ddr1_dqs2, output3, X, 100, 1, Z)," &
"100 (bc_1, *, control, 1)," &
"101 (bc_1, ddr1_dqs1, input, X)," &
"102 (bc_1, ddr1_dqs1, output3, X, 103, 1, Z)," &
"103 (bc_1, *, control, 1)," &
"104 (bc_1, ddr1_dqs0, input, X)," &
"105 (bc_1, ddr1_dqs0, output3, X, 106, 1, Z)," &
"106 (bc_1, *, control, 1)," &
"107 (bc_1, ddr1_d31, input, X)," &
"108 (bc_1, ddr1_d31, output3, X, 109, 1, Z)," &
"109 (bc_1, *, control, 1)," &
"110 (bc_1, ddr1_d30, input, X)," &
"111 (bc_1, ddr1_d30, output3, X, 112, 1, Z)," &
"112 (bc_1, *, control, 1)," &
"113 (bc_1, ddr1_d29, input, X)," &
"114 (bc_1, ddr1_d29, output3, X, 115, 1, Z)," &
"115 (bc_1, *, control, 1)," &
"116 (bc_1, ddr1_d28, input, X)," &
"117 (bc_1, ddr1_d28, output3, X, 118, 1, Z)," &
"118 (bc_1, *, control, 1)," &
"119 (bc_1, ddr1_d27, input, X)," &
"120 (bc_1, ddr1_d27, output3, X, 121, 1, Z)," &
"121 (bc_1, *, control, 1)," &
"122 (bc_1, ddr1_d26, input, X)," &
"123 (bc_1, ddr1_d26, output3, X, 124, 1, Z)," &
"124 (bc_1, *, control, 1)," &
"125 (bc_1, ddr1_d25, input, X)," &
"126 (bc_1, ddr1_d25, output3, X, 127, 1, Z)," &
"127 (bc_1, *, control, 1)," &
"128 (bc_1, ddr1_d24, input, X)," &
"129 (bc_1, ddr1_d24, output3, X, 130, 1, Z)," &
"130 (bc_1, *, control, 1)," &
"131 (bc_1, ddr1_d23, input, X)," &
"132 (bc_1, ddr1_d23, output3, X, 133, 1, Z)," &
"133 (bc_1, *, control, 1)," &
"134 (bc_1, ddr1_d22, input, X)," &
"135 (bc_1, ddr1_d22, output3, X, 136, 1, Z)," &
"136 (bc_1, *, control, 1)," &
"137 (bc_1, ddr1_d21, input, X)," &
"138 (bc_1, ddr1_d21, output3, X, 139, 1, Z)," &
"139 (bc_1, *, control, 1)," &
"140 (bc_1, ddr1_d20, input, X)," &
"141 (bc_1, ddr1_d20, output3, X, 142, 1, Z)," &
"142 (bc_1, *, control, 1)," &
"143 (bc_1, ddr1_d19, input, X)," &
"144 (bc_1, ddr1_d19, output3, X, 145, 1, Z)," &
"145 (bc_1, *, control, 1)," &
"146 (bc_1, ddr1_d18, input, X)," &
"147 (bc_1, ddr1_d18, output3, X, 148, 1, Z)," &
"148 (bc_1, *, control, 1)," &
"149 (bc_1, ddr1_d17, input, X)," &
"150 (bc_1, ddr1_d17, output3, X, 151, 1, Z)," &
"151 (bc_1, *, control, 1)," &
"152 (bc_1, ddr1_d16, input, X)," &
"153 (bc_1, ddr1_d16, output3, X, 154, 1, Z)," &
"154 (bc_1, *, control, 1)," &
"155 (bc_1, ddr1_d15, input, X)," &
"156 (bc_1, ddr1_d15, output3, X, 157, 1, Z)," &
"157 (bc_1, *, control, 1)," &
"158 (bc_1, ddr1_d14, input, X)," &
"159 (bc_1, ddr1_d14, output3, X, 160, 1, Z)," &
"160 (bc_1, *, control, 1)," &
"161 (bc_1, ddr1_d13, input, X)," &
"162 (bc_1, ddr1_d13, output3, X, 163, 1, Z)," &
"163 (bc_1, *, control, 1)," &
"164 (bc_1, ddr1_d12, input, X)," &
"165 (bc_1, ddr1_d12, output3, X, 166, 1, Z)," &
"166 (bc_1, *, control, 1)," &
"167 (bc_1, ddr1_d11, input, X)," &
"168 (bc_1, ddr1_d11, output3, X, 169, 1, Z)," &
"169 (bc_1, *, control, 1)," &
"170 (bc_1, ddr1_d10, input, X)," &
"171 (bc_1, ddr1_d10, output3, X, 172, 1, Z)," &
"172 (bc_1, *, control, 1)," &
"173 (bc_1, ddr1_d09, input, X)," &
"174 (bc_1, ddr1_d09, output3, X, 175, 1, Z)," &
"175 (bc_1, *, control, 1)," &
"176 (bc_1, ddr1_d08, input, X)," &
"177 (bc_1, ddr1_d08, output3, X, 178, 1, Z)," &
"178 (bc_1, *, control, 1)," &
"179 (bc_1, ddr1_d07, input, X)," &
"180 (bc_1, ddr1_d07, output3, X, 181, 1, Z)," &
"181 (bc_1, *, control, 1)," &
"182 (bc_1, ddr1_d06, input, X)," &
"183 (bc_1, ddr1_d06, output3, X, 184, 1, Z)," &
"184 (bc_1, *, control, 1)," &
"185 (bc_1, ddr1_d05, input, X)," &
"186 (bc_1, ddr1_d05, output3, X, 187, 1, Z)," &
"187 (bc_1, *, control, 1)," &
"188 (bc_1, ddr1_d04, input, X)," &
"189 (bc_1, ddr1_d04, output3, X, 190, 1, Z)," &
"190 (bc_1, *, control, 1)," &
"191 (bc_1, ddr1_d03, input, X)," &
"192 (bc_1, ddr1_d03, output3, X, 193, 1, Z)," &
"193 (bc_1, *, control, 1)," &
"194 (bc_1, ddr1_d02, input, X)," &
"195 (bc_1, ddr1_d02, output3, X, 196, 1, Z)," &
"196 (bc_1, *, control, 1)," &
"197 (bc_1, ddr1_d01, input, X)," &
"198 (bc_1, ddr1_d01, output3, X, 199, 1, Z)," &
"199 (bc_1, *, control, 1)," &
"200 (bc_1, ddr1_d00, input, X)," &
"201 (bc_1, ddr1_d00, output3, X, 202, 1, Z)," &
"202 (bc_1, *, control, 1)," &
"203 (bc_1, ddr0_a13, input, X)," &
"204 (bc_1, ddr0_a13, output3, X, 221, 1, Z)," &
"205 (bc_1, ddr0_a14, input, X)," &
"206 (bc_1, ddr0_a14, output3, X, 221, 1, Z)," &
"207 (bc_1, ddr0_a01, input, X)," &
"208 (bc_1, ddr0_a01, output3, X, 221, 1, Z)," &
"209 (bc_1, ddr0_csn1, input, X)," &
"210 (bc_1, ddr0_csn1, output3, X, 221, 1, Z)," &
"211 (bc_1, ddr0_csn0, input, X)," &
"212 (bc_1, ddr0_csn0, output3, X, 221, 1, Z)," &
"213 (bc_1, ddr0_odt1, input, X)," &
"214 (bc_1, ddr0_odt1, output3, X, 221, 1, Z)," &
"215 (bc_1, ddr0_odt0, input, X)," &
"216 (bc_1, ddr0_odt0, output3, X, 221, 1, Z)," &
"217 (bc_1, ddr0_rst, input, X)," &
"218 (bc_1, ddr0_rst, output3, X, 221, 1, Z)," &
"219 (bc_1, ddr0_cke, input, X)," &
"220 (bc_1, ddr0_cke, output3, X, 221, 1, Z)," &
"221 (bc_1, *, control, 1)," &
"222 (bc_1, ddr0_rasn, input, X)," &
"223 (bc_1, ddr0_rasn, output3, X, 240, 1, Z)," &
"224 (bc_1, ddr0_casn, input, X)," &
"225 (bc_1, ddr0_casn, output3, X, 240, 1, Z)," &
"226 (bc_1, ddr0_a11, input, X)," &
"227 (bc_1, ddr0_a11, output3, X, 240, 1, Z)," &
"228 (bc_1, ddr0_a00, input, X)," &
"229 (bc_1, ddr0_a00, output3, X, 240, 1, Z)," &
"230 (bc_1, ddr0_a10, input, X)," &
"231 (bc_1, ddr0_a10, output3, X, 240, 1, Z)," &
"232 (bc_1, ddr0_ba1, input, X)," &
"233 (bc_1, ddr0_ba1, output3, X, 240, 1, Z)," &
"234 (bc_1, ddr0_a07, input, X)," &
"235 (bc_1, ddr0_a07, output3, X, 240, 1, Z)," &
"236 (bc_1, ddr0_a12, input, X)," &
"237 (bc_1, ddr0_a12, output3, X, 240, 1, Z)," &
"238 (bc_1, ddr0_a02, input, X)," &
"239 (bc_1, ddr0_a02, output3, X, 240, 1, Z)," &
"240 (bc_1, *, control, 1)," &
"241 (bc_1, ddr0_a06, input, X)," &
"242 (bc_1, ddr0_a06, output3, X, 263, 1, Z)," &
"243 (bc_1, ddr0_a09, input, X)," &
"244 (bc_1, ddr0_a09, output3, X, 263, 1, Z)," &
"245 (bc_1, ddr0_a08, input, X)," &
"246 (bc_1, ddr0_a08, output3, X, 263, 1, Z)," &
"247 (bc_1, ddr0_a04, input, X)," &
"248 (bc_1, ddr0_a04, output3, X, 263, 1, Z)," &
"249 (bc_1, ddr0_a03, input, X)," &
"250 (bc_1, ddr0_a03, output3, X, 263, 1, Z)," &
"251 (bc_4, *, internal, X)," &
"252 (bc_4, *, internal, X )," &
"253 (bc_1, ddr0_ck, input, X)," &
"254 (bc_1, ddr0_ck, output3, X, 263, 1, Z)," &
"255 (bc_1, ddr0_a05, input, X)," &
"256 (bc_1, ddr0_a05, output3, X, 263, 1, Z)," &
"257 (bc_1, ddr0_ba0, input, X)," &
"258 (bc_1, ddr0_ba0, output3, X, 263, 1, Z)," &
"259 (bc_1, ddr0_wen, input, X)," &
"260 (bc_1, ddr0_wen, output3, X, 263, 1, Z)," &
"261 (bc_1, ddr0_ba2, input, X)," &
"262 (bc_1, ddr0_ba2, output3, X, 263, 1, Z)," &
"263 (bc_1, *, control, 1)," &
"264 (bc_4, *, internal, X )," &
"265 (bc_4, *, internal, X )," &
"266 (bc_4, *, internal, X )," &
"267 (bc_4, *, internal, X )," &
"268 (bc_4, *, internal, X )," &
"269 (bc_4, *, internal, X )," &
"270 (bc_4, *, internal, X )," &
"271 (bc_4, *, internal, X )," &
"272 (bc_4, *, internal, X )," &
"273 (bc_4, *, internal, X )," &
"274 (bc_4, *, internal, X )," &
"275 (bc_4, *, internal, X )," &
"276 (bc_1, ddr0_dqm3, input, X)," &
"277 (bc_1, ddr0_dqm3, output3, X, 278, 1, Z)," &
"278 (bc_1, *, control, 1)," &
"279 (bc_1, ddr0_dqm2, input, X)," &
"280 (bc_1, ddr0_dqm2, output3, X, 281, 1, Z)," &
"281 (bc_1, *, control, 1)," &
"282 (bc_1, ddr0_dqm1, input, X)," &
"283 (bc_1, ddr0_dqm1, output3, X, 284, 1, Z)," &
"284 (bc_1, *, control, 1)," &
"285 (bc_1, ddr0_dqm0, input, X)," &
"286 (bc_1, ddr0_dqm0, output3, X, 287, 1, Z)," &
"287 (bc_1, *, control, 1)," &
"288 (bc_1, ddr0_dqs3, input, X)," &
"289 (bc_1, ddr0_dqs3, output3, X, 290, 1, Z)," &
"290 (bc_1, *, control, 1)," &
"291 (bc_1, ddr0_dqs2, input, X)," &
"292 (bc_1, ddr0_dqs2, output3, X, 293, 1, Z)," &
"293 (bc_1, *, control, 1)," &
"294 (bc_1, ddr0_dqs1, input, X)," &
"295 (bc_1, ddr0_dqs1, output3, X, 296, 1, Z)," &
"296 (bc_1, *, control, 1)," &
"297 (bc_1, ddr0_dqs0, input, X)," &
"298 (bc_1, ddr0_dqs0, output3, X, 299, 1, Z)," &
"299 (bc_1, *, control, 1)," &
"300 (bc_1, ddr0_d31, input, X)," &
"301 (bc_1, ddr0_d31, output3, X, 302, 1, Z)," &
"302 (bc_1, *, control, 1)," &
"303 (bc_1, ddr0_d30, input, X)," &
"304 (bc_1, ddr0_d30, output3, X, 305, 1, Z)," &
"305 (bc_1, *, control, 1)," &
"306 (bc_1, ddr0_d29, input, X)," &
"307 (bc_1, ddr0_d29, output3, X, 308, 1, Z)," &
"308 (bc_1, *, control, 1)," &
"309 (bc_1, ddr0_d28, input, X)," &
"310 (bc_1, ddr0_d28, output3, X, 311, 1, Z)," &
"311 (bc_1, *, control, 1)," &
"312 (bc_1, ddr0_d27, input, X)," &
"313 (bc_1, ddr0_d27, output3, X, 314, 1, Z)," &
"314 (bc_1, *, control, 1)," &
"315 (bc_1, ddr0_d26, input, X)," &
"316 (bc_1, ddr0_d26, output3, X, 317, 1, Z)," &
"317 (bc_1, *, control, 1)," &
"318 (bc_1, ddr0_d25, input, X)," &
"319 (bc_1, ddr0_d25, output3, X, 320, 1, Z)," &
"320 (bc_1, *, control, 1)," &
"321 (bc_1, ddr0_d24, input, X)," &
"322 (bc_1, ddr0_d24, output3, X, 323, 1, Z)," &
"323 (bc_1, *, control, 1)," &
"324 (bc_1, ddr0_d23, input, X)," &
"325 (bc_1, ddr0_d23, output3, X, 326, 1, Z)," &
"326 (bc_1, *, control, 1)," &
"327 (bc_1, ddr0_d22, input, X)," &
"328 (bc_1, ddr0_d22, output3, X, 329, 1, Z)," &
"329 (bc_1, *, control, 1)," &
"330 (bc_1, ddr0_d21, input, X)," &
"331 (bc_1, ddr0_d21, output3, X, 332, 1, Z)," &
"332 (bc_1, *, control, 1)," &
"333 (bc_1, ddr0_d20, input, X)," &
"334 (bc_1, ddr0_d20, output3, X, 335, 1, Z)," &
"335 (bc_1, *, control, 1)," &
"336 (bc_1, ddr0_d19, input, X)," &
"337 (bc_1, ddr0_d19, output3, X, 338, 1, Z)," &
"338 (bc_1, *, control, 1)," &
"339 (bc_1, ddr0_d18, input, X)," &
"340 (bc_1, ddr0_d18, output3, X, 341, 1, Z)," &
"341 (bc_1, *, control, 1)," &
"342 (bc_1, ddr0_d17, input, X)," &
"343 (bc_1, ddr0_d17, output3, X, 344, 1, Z)," &
"344 (bc_1, *, control, 1)," &
"345 (bc_1, ddr0_d16, input, X)," &
"346 (bc_1, ddr0_d16, output3, X, 347, 1, Z)," &
"347 (bc_1, *, control, 1)," &
"348 (bc_1, ddr0_d15, input, X)," &
"349 (bc_1, ddr0_d15, output3, X, 350, 1, Z)," &
"350 (bc_1, *, control, 1)," &
"351 (bc_1, ddr0_d14, input, X)," &
"352 (bc_1, ddr0_d14, output3, X, 353, 1, Z)," &
"353 (bc_1, *, control, 1)," &
"354 (bc_1, ddr0_d13, input, X)," &
"355 (bc_1, ddr0_d13, output3, X, 356, 1, Z)," &
"356 (bc_1, *, control, 1)," &
"357 (bc_1, ddr0_d12, input, X)," &
"358 (bc_1, ddr0_d12, output3, X, 359, 1, Z)," &
"359 (bc_1, *, control, 1)," &
"360 (bc_1, ddr0_d11, input, X)," &
"361 (bc_1, ddr0_d11, output3, X, 362, 1, Z)," &
"362 (bc_1, *, control, 1)," &
"363 (bc_1, ddr0_d10, input, X)," &
"364 (bc_1, ddr0_d10, output3, X, 365, 1, Z)," &
"365 (bc_1, *, control, 1)," &
"366 (bc_1, ddr0_d09, input, X)," &
"367 (bc_1, ddr0_d09, output3, X, 368, 1, Z)," &
"368 (bc_1, *, control, 1)," &
"369 (bc_1, ddr0_d08, input, X)," &
"370 (bc_1, ddr0_d08, output3, X, 371, 1, Z)," &
"371 (bc_1, *, control, 1)," &
"372 (bc_1, ddr0_d07, input, X)," &
"373 (bc_1, ddr0_d07, output3, X, 374, 1, Z)," &
"374 (bc_1, *, control, 1)," &
"375 (bc_1, ddr0_d06, input, X)," &
"376 (bc_1, ddr0_d06, output3, X, 377, 1, Z)," &
"377 (bc_1, *, control, 1)," &
"378 (bc_1, ddr0_d05, input, X)," &
"379 (bc_1, ddr0_d05, output3, X, 380, 1, Z)," &
"380 (bc_1, *, control, 1)," &
"381 (bc_1, ddr0_d04, input, X)," &
"382 (bc_1, ddr0_d04, output3, X, 383, 1, Z)," &
"383 (bc_1, *, control, 1)," &
"384 (bc_1, ddr0_d03, input, X)," &
"385 (bc_1, ddr0_d03, output3, X, 386, 1, Z)," &
"386 (bc_1, *, control, 1)," &
"387 (bc_1, ddr0_d02, input, X)," &
"388 (bc_1, ddr0_d02, output3, X, 389, 1, Z)," &
"389 (bc_1, *, control, 1)," &
"390 (bc_1, ddr0_d01, input, X)," &
"391 (bc_1, ddr0_d01, output3, X, 392, 1, Z)," &
"392 (bc_1, *, control, 1)," &
"393 (bc_1, ddr0_d00, input, X)," &
"394 (bc_1, ddr0_d00, output3, X, 395, 1, Z)," &
"395 (bc_1, *, control, 1)," &
"396 (bc_1, gmii0_txen, input, X)," &
"397 (bc_1, gmii0_txen, output3, X, 398, 1, Z)," &
"398 (bc_1, *, control, 1)," &
"399 (bc_1, gmii0_txd7, input, X)," &
"400 (bc_1, gmii0_txd7, output3, X, 401, 1, Z)," &
"401 (bc_1, *, control, 1)," &
"402 (bc_1, gmii0_txd6, input, X)," &
"403 (bc_1, gmii0_txd6, output3, X, 404, 1, Z)," &
"404 (bc_1, *, control, 1)," &
"405 (bc_1, gmii0_txd5, input, X)," &
"406 (bc_1, gmii0_txd5, output3, X, 407, 1, Z)," &
"407 (bc_1, *, control, 1)," &
"408 (bc_1, gmii0_txd4, input, X)," &
"409 (bc_1, gmii0_txd4, output3, X, 410, 1, Z)," &
"410 (bc_1, *, control, 1)," &
"411 (bc_1, gmii0_txd3, input, X)," &
"412 (bc_1, gmii0_txd3, output3, X, 413, 1, Z)," &
"413 (bc_1, *, control, 1)," &
"414 (bc_1, gmii0_txd2, input, X)," &
"415 (bc_1, gmii0_txd2, output3, X, 416, 1, Z)," &
"416 (bc_1, *, control, 1)," &
"417 (bc_1, gmii0_txd1, input, X)," &
"418 (bc_1, gmii0_txd1, output3, X, 419, 1, Z)," &
"419 (bc_1, *, control, 1)," &
"420 (bc_1, gmii0_txd0, input, X)," &
"421 (bc_1, gmii0_txd0, output3, X, 422, 1, Z)," &
"422 (bc_1, *, control, 1)," &
"423 (bc_1, gmii0_gtxclk, input, X)," &
"424 (bc_1, gmii0_gtxclk, output3, X, 425, 1, Z)," &
"425 (bc_1, *, control, 1)," &
"426 (bc_1, gmii0_rxdv, input, X)," &
"427 (bc_1, gmii0_rxdv, output3, X, 428, 1, Z)," &
"428 (bc_1, *, control, 1)," &
"429 (bc_1, gmii0_rxd7, input, X)," &
"430 (bc_1, gmii0_rxd7, output3, X, 431, 1, Z)," &
"431 (bc_1, *, control, 1)," &
"432 (bc_1, gmii0_rxd6, input, X)," &
"433 (bc_1, gmii0_rxd6, output3, X, 434, 1, Z)," &
"434 (bc_1, *, control, 1)," &
"435 (bc_1, gmii0_rxd5, input, X)," &
"436 (bc_1, gmii0_rxd5, output3, X, 437, 1, Z)," &
"437 (bc_1, *, control, 1)," &
"438 (bc_1, gmii0_rxd4, input, X)," &
"439 (bc_1, gmii0_rxd4, output3, X, 440, 1, Z)," &
"440 (bc_1, *, control, 1)," &
"441 (bc_1, gmii0_rxd3, input, X)," &
"442 (bc_1, gmii0_rxd3, output3, X, 443, 1, Z)," &
"443 (bc_1, *, control, 1)," &
"444 (bc_1, gmii0_rxd2, input, X)," &
"445 (bc_1, gmii0_rxd2, output3, X, 446, 1, Z)," &
"446 (bc_1, *, control, 1)," &
"447 (bc_1, gmii0_rxd1, input, X)," &
"448 (bc_1, gmii0_rxd1, output3, X, 449, 1, Z)," &
"449 (bc_1, *, control, 1)," &
"450 (bc_1, gmii0_rxclk, input, X)," &
"451 (bc_1, gmii0_rxclk, output3, X, 452, 1, Z)," &
"452 (bc_1, *, control, 1)," &
"453 (bc_1, gmii0_rxd0, input, X)," &
"454 (bc_1, gmii0_rxd0, output3, X, 455, 1, Z)," &
"455 (bc_1, *, control, 1)," &
"456 (bc_1, gmii0_rxer, input, X)," &
"457 (bc_1, gmii0_rxer, output3, X, 458, 1, Z)," &
"458 (bc_1, *, control, 1)," &
"459 (bc_1, gmii0_crs, input, X)," &
"460 (bc_1, gmii0_crs, output3, X, 461, 1, Z)," &
"461 (bc_1, *, control, 1)," &
"462 (bc_1, gmii0_col, input, X)," &
"463 (bc_1, gmii0_col, output3, X, 464, 1, Z)," &
"464 (bc_1, *, control, 1)," &
"465 (bc_1, gmii0_txclk, input, X)," &
"466 (bc_1, gmii0_txclk, output3, X, 467, 1, Z)," &
"467 (bc_1, *, control, 1)," &
"468 (bc_1, mdio_d, input, X)," &
"469 (bc_1, mdio_d, output3, X, 470, 1, Z)," &
"470 (bc_1, *, control, 1)," &
"471 (bc_1, mdio_mclk, input, X)," &
"472 (bc_1, mdio_mclk, output3, X, 473, 1, Z)," &
"473 (bc_1, *, control, 1)," &
"474 (bc_1, rmii_refclk, input, X)," &
"475 (bc_1, rmii_refclk, output3, X, 476, 1, Z)," &
"476 (bc_1, *, control, 1)," &
"477 (bc_1, gpmc_cs3, input, X)," &
"478 (bc_1, gpmc_cs3, output3, X, 479, 1, Z)," &
"479 (bc_1, *, control, 1)," &
"480 (bc_1, gpmc_cs4, input, X)," &
"481 (bc_1, gpmc_cs4, output3, X, 482, 1, Z)," &
"482 (bc_1, *, control, 1)," &
"483 (bc_1, mmc2_dat7, input, X)," &
"484 (bc_1, mmc2_dat7, output3, X, 485, 1, Z)," &
"485 (bc_1, *, control, 1)," &
"486 (bc_1, mmc2_dat6, input, X)," &
"487 (bc_1, mmc2_dat6, output3, X, 488, 1, Z)," &
"488 (bc_1, *, control, 1)," &
"489 (bc_1, mmc2_dat5, input, X)," &
"490 (bc_1, mmc2_dat5, output3, X, 491, 1, Z)," &
"491 (bc_1, *, control, 1)," &
"492 (bc_1, mmc2_dat4, input, X)," &
"493 (bc_1, mmc2_dat4, output3, X, 494, 1, Z)," &
"494 (bc_1, *, control, 1)," &
"495 (bc_1, mmc2_dat3, input, X)," &
"496 (bc_1, mmc2_dat3, output3, X, 497, 1, Z)," &
"497 (bc_1, *, control, 1)," &
"498 (bc_1, mmc2_dat2, input, X)," &
"499 (bc_1, mmc2_dat2, output3, X, 500, 1, Z)," &
"500 (bc_1, *, control, 1)," &
"501 (bc_1, mmc2_clk, input, X)," &
"502 (bc_1, mmc2_clk, output3, X, 503, 1, Z)," &
"503 (bc_1, *, control, 1)," &
"504 (bc_1, mmc2_dat1, input, X)," &
"505 (bc_1, mmc2_dat1, output3, X, 506, 1, Z)," &
"506 (bc_1, *, control, 1)," &
"507 (bc_1, mmc2_dat0, input, X)," &
"508 (bc_1, mmc2_dat0, output3, X, 509, 1, Z)," &
"509 (bc_1, *, control, 1)," &
"510 (bc_1, gpmc_cs0, input, X)," &
"511 (bc_1, gpmc_cs0, output3, X, 512, 1, Z)," &
"512 (bc_1, *, control, 1)," &
"513 (bc_1, gpmc_cs1, input, X)," &
"514 (bc_1, gpmc_cs1, output3, X, 515, 1, Z)," &
"515 (bc_1, *, control, 1)," &
"516 (bc_1, gpmc_cs2, input, X)," &
"517 (bc_1, gpmc_cs2, output3, X, 518, 1, Z)," &
"518 (bc_1, *, control, 1)," &
"519 (bc_1, gpmc_clk, input, X)," &
"520 (bc_1, gpmc_clk, output3, X, 521, 1, Z)," &
"521 (bc_1, *, control, 1)," &
"522 (bc_1, gpmc_advn_ale, input, X)," &
"523 (bc_1, gpmc_advn_ale, output3, X, 524, 1, Z)," &
"524 (bc_1, *, control, 1)," &
"525 (bc_1, gpmc_oen_ren, input, X)," &
"526 (bc_1, gpmc_oen_ren, output3, X, 527, 1, Z)," &
"527 (bc_1, *, control, 1)," &
"528 (bc_1, gpmc_wen, input, X)," &
"529 (bc_1, gpmc_wen, output3, X, 530, 1, Z)," &
"530 (bc_1, *, control, 1)," &
"531 (bc_1, gpmc_ben0, input, X)," &
"532 (bc_1, gpmc_ben0, output3, X, 533, 1, Z)," &
"533 (bc_1, *, control, 1)," &
"534 (bc_1, gpmc_ben1, input, X)," &
"535 (bc_1, gpmc_ben1, output3, X, 536, 1, Z)," &
"536 (bc_1, *, control, 1)," &
"537 (bc_1, gpmc_wait0, input, X)," &
"538 (bc_1, gpmc_wait0, output3, X, 539, 1, Z)," &
"539 (bc_1, *, control, 1)," &
"540 (bc_1, gpmc_ad00, input, X)," &
"541 (bc_1, gpmc_ad00, output3, X, 542, 1, Z)," &
"542 (bc_1, *, control, 1)," &
"543 (bc_1, gpmc_ad01, input, X)," &
"544 (bc_1, gpmc_ad01, output3, X, 545, 1, Z)," &
"545 (bc_1, *, control, 1)," &
"546 (bc_1, gpmc_ad02, input, X)," &
"547 (bc_1, gpmc_ad02, output3, X, 548, 1, Z)," &
"548 (bc_1, *, control, 1)," &
"549 (bc_1, gpmc_ad03, input, X)," &
"550 (bc_1, gpmc_ad03, output3, X, 551, 1, Z)," &
"551 (bc_1, *, control, 1)," &
"552 (bc_1, gpmc_ad04, input, X)," &
"553 (bc_1, gpmc_ad04, output3, X, 554, 1, Z)," &
"554 (bc_1, *, control, 1)," &
"555 (bc_1, gpmc_ad05, input, X)," &
"556 (bc_1, gpmc_ad05, output3, X, 557, 1, Z)," &
"557 (bc_1, *, control, 1)," &
"558 (bc_1, gpmc_ad06, input, X)," &
"559 (bc_1, gpmc_ad06, output3, X, 560, 1, Z)," &
"560 (bc_1, *, control, 1)," &
"561 (bc_1, gpmc_ad07, input, X)," &
"562 (bc_1, gpmc_ad07, output3, X, 563, 1, Z)," &
"563 (bc_1, *, control, 1)," &
"564 (bc_1, gpmc_ad08, input, X)," &
"565 (bc_1, gpmc_ad08, output3, X, 566, 1, Z)," &
"566 (bc_1, *, control, 1)," &
"567 (bc_1, gpmc_ad09, input, X)," &
"568 (bc_1, gpmc_ad09, output3, X, 569, 1, Z)," &
"569 (bc_1, *, control, 1)," &
"570 (bc_1, gpmc_ad10, input, X)," &
"571 (bc_1, gpmc_ad10, output3, X, 572, 1, Z)," &
"572 (bc_1, *, control, 1)," &
"573 (bc_1, gpmc_ad11, input, X)," &
"574 (bc_1, gpmc_ad11, output3, X, 575, 1, Z)," &
"575 (bc_1, *, control, 1)," &
"576 (bc_1, gpmc_ad12, input, X)," &
"577 (bc_1, gpmc_ad12, output3, X, 578, 1, Z)," &
"578 (bc_1, *, control, 1)," &
"579 (bc_1, gpmc_ad13, input, X)," &
"580 (bc_1, gpmc_ad13, output3, X, 581, 1, Z)," &
"581 (bc_1, *, control, 1)," &
"582 (bc_1, gpmc_ad14, input, X)," &
"583 (bc_1, gpmc_ad14, output3, X, 584, 1, Z)," &
"584 (bc_1, *, control, 1)," &
"585 (bc_1, gpmc_ad15, input, X)," &
"586 (bc_1, gpmc_ad15, output3, X, 587, 1, Z)," &
"587 (bc_1, *, control, 1)," &
"588 (bc_1, gpmc_a23, input, X)," &
"589 (bc_1, gpmc_a23, output3, X, 590, 1, Z)," &
"590 (bc_1, *, control, 1)," &
"591 (bc_1, gpmc_a22, input, X)," &
"592 (bc_1, gpmc_a22, output3, X, 593, 1, Z)," &
"593 (bc_1, *, control, 1)," &
"594 (bc_1, gpmc_a21, input, X)," &
"595 (bc_1, gpmc_a21, output3, X, 596, 1, Z)," &
"596 (bc_1, *, control, 1)," &
"597 (bc_1, gpmc_a20, input, X)," &
"598 (bc_1, gpmc_a20, output3, X, 599, 1, Z)," &
"599 (bc_1, *, control, 1)," &
"600 (bc_1, gpmc_a19, input, X)," &
"601 (bc_1, gpmc_a19, output3, X, 602, 1, Z)," &
"602 (bc_1, *, control, 1)," &
"603 (bc_1, gpmc_a18, input, X)," &
"604 (bc_1, gpmc_a18, output3, X, 605, 1, Z)," &
"605 (bc_1, *, control, 1)," &
"606 (bc_1, gpmc_a17, input, X)," &
"607 (bc_1, gpmc_a17, output3, X, 608, 1, Z)," &
"608 (bc_1, *, control, 1)," &
"609 (bc_1, gpmc_a16, input, X)," &
"610 (bc_1, gpmc_a16, output3, X, 611, 1, Z)," &
"611 (bc_1, *, control, 1)," &
"612 (bc_1, vout1_b_cb_c2, input, X)," &
"613 (bc_1, vout1_b_cb_c2, output3, X, 614, 1, Z)," &
"614 (bc_1, *, control, 1)," &
"615 (bc_1, vout1_r_cr2, input, X)," &
"616 (bc_1, vout1_r_cr2, output3, X, 617, 1, Z)," &
"617 (bc_1, *, control, 1)," &
"618 (bc_1, vout1_r_cr3, input, X)," &
"619 (bc_1, vout1_r_cr3, output3, X, 620, 1, Z)," &
"620 (bc_1, *, control, 1)," &
"621 (bc_1, vout1_g_y_yc2, input, X)," &
"622 (bc_1, vout1_g_y_yc2, output3, X, 623, 1, Z)," &
"623 (bc_1, *, control, 1)," &
"624 (bc_1, vout1_r_cr9, input, X)," &
"625 (bc_1, vout1_r_cr9, output3, X, 626, 1, Z)," &
"626 (bc_1, *, control, 1)," &
"627 (bc_1, vout1_r_cr8, input, X)," &
"628 (bc_1, vout1_r_cr8, output3, X, 629, 1, Z)," &
"629 (bc_1, *, control, 1)," &
"630 (bc_1, vout1_r_cr7, input, X)," &
"631 (bc_1, vout1_r_cr7, output3, X, 632, 1, Z)," &
"632 (bc_1, *, control, 1)," &
"633 (bc_1, vout1_r_cr6, input, X)," &
"634 (bc_1, vout1_r_cr6, output3, X, 635, 1, Z)," &
"635 (bc_1, *, control, 1)," &
"636 (bc_1, vout1_r_cr5, input, X)," &
"637 (bc_1, vout1_r_cr5, output3, X, 638, 1, Z)," &
"638 (bc_1, *, control, 1)," &
"639 (bc_1, vout1_r_cr4, input, X)," &
"640 (bc_1, vout1_r_cr4, output3, X, 641, 1, Z)," &
"641 (bc_1, *, control, 1)," &
"642 (bc_1, vout1_g_y_yc9, input, X)," &
"643 (bc_1, vout1_g_y_yc9, output3, X, 644, 1, Z)," &
"644 (bc_1, *, control, 1)," &
"645 (bc_1, vout1_g_y_yc8, input, X)," &
"646 (bc_1, vout1_g_y_yc8, output3, X, 647, 1, Z)," &
"647 (bc_1, *, control, 1)," &
"648 (bc_1, vout1_g_y_yc7, input, X)," &
"649 (bc_1, vout1_g_y_yc7, output3, X, 650, 1, Z)," &
"650 (bc_1, *, control, 1)," &
"651 (bc_1, vout1_g_y_yc6, input, X)," &
"652 (bc_1, vout1_g_y_yc6, output3, X, 653, 1, Z)," &
"653 (bc_1, *, control, 1)," &
"654 (bc_1, vout1_g_y_yc5, input, X)," &
"655 (bc_1, vout1_g_y_yc5, output3, X, 656, 1, Z)," &
"656 (bc_1, *, control, 1)," &
"657 (bc_1, vout1_g_y_yc4, input, X)," &
"658 (bc_1, vout1_g_y_yc4, output3, X, 659, 1, Z)," &
"659 (bc_1, *, control, 1)," &
"660 (bc_1, vout1_g_y_yc3, input, X)," &
"661 (bc_1, vout1_g_y_yc3, output3, X, 662, 1, Z)," &
"662 (bc_1, *, control, 1)," &
"663 (bc_1, vout1_b_cb_c9, input, X)," &
"664 (bc_1, vout1_b_cb_c9, output3, X, 665, 1, Z)," &
"665 (bc_1, *, control, 1)," &
"666 (bc_1, vout1_b_cb_c8, input, X)," &
"667 (bc_1, vout1_b_cb_c8, output3, X, 668, 1, Z)," &
"668 (bc_1, *, control, 1)," &
"669 (bc_1, vout1_b_cb_c7, input, X)," &
"670 (bc_1, vout1_b_cb_c7, output3, X, 671, 1, Z)," &
"671 (bc_1, *, control, 1)," &
"672 (bc_1, vout1_b_cb_c6, input, X)," &
"673 (bc_1, vout1_b_cb_c6, output3, X, 674, 1, Z)," &
"674 (bc_1, *, control, 1)," &
"675 (bc_1, vout1_b_cb_c5, input, X)," &
"676 (bc_1, vout1_b_cb_c5, output3, X, 677, 1, Z)," &
"677 (bc_1, *, control, 1)," &
"678 (bc_1, vout1_b_cb_c4, input, X)," &
"679 (bc_1, vout1_b_cb_c4, output3, X, 680, 1, Z)," &
"680 (bc_1, *, control, 1)," &
"681 (bc_1, vout1_b_cb_c3, input, X)," &
"682 (bc_1, vout1_b_cb_c3, output3, X, 683, 1, Z)," &
"683 (bc_1, *, control, 1)," &
"684 (bc_1, vout1_avid, input, X)," &
"685 (bc_1, vout1_avid, output3, X, 686, 1, Z)," &
"686 (bc_1, *, control, 1)," &
"687 (bc_1, vout1_vsync, input, X)," &
"688 (bc_1, vout1_vsync, output3, X, 689, 1, Z)," &
"689 (bc_1, *, control, 1)," &
"690 (bc_1, vout1_hsync, input, X)," &
"691 (bc_1, vout1_hsync, output3, X, 692, 1, Z)," &
"692 (bc_1, *, control, 1)," &
"693 (bc_1, vout1_clk, input, X)," &
"694 (bc_1, vout1_clk, output3, X, 695, 1, Z)," &
"695 (bc_1, *, control, 1)," &
"696 (bc_1, i2c1_scl, input, X)," &
"697 (bc_1, i2c1_scl, output2, 1, 697, 1, Weak1)," &
"698 (bc_4, *, internal, 0)," &
"699 (bc_1, i2c1_sda, input, X)," &
"700 (bc_1, i2c1_sda, output2, 1, 700, 1, Weak1)," &
"701 (bc_4, *, internal, 0)," &
"702 (bc_1, vout1_fid, input, X)," &
"703 (bc_1, vout1_fid, output3, X, 704, 1, Z)," &
"704 (bc_1, *, control, 1)," &
"705 (bc_1, vout1_b_cb_c0, input, X)," &
"706 (bc_1, vout1_b_cb_c0, output3, X, 707, 1, Z)," &
"707 (bc_1, *, control, 1)," &
"708 (bc_1, vout1_b_cb_c1, input, X)," &
"709 (bc_1, vout1_b_cb_c1, output3, X, 710, 1, Z)," &
"710 (bc_1, *, control, 1)," &
"711 (bc_1, vout1_r_cr0, input, X)," &
"712 (bc_1, vout1_r_cr0, output3, X, 713, 1, Z)," &
"713 (bc_1, *, control, 1)," &
"714 (bc_1, vout1_r_cr1, input, X)," &
"715 (bc_1, vout1_r_cr1, output3, X, 716, 1, Z)," &
"716 (bc_1, *, control, 1)," &
"717 (bc_1, vout1_g_y_yc0, input, X)," &
"718 (bc_1, vout1_g_y_yc0, output3, X, 719, 1, Z)," &
"719 (bc_1, *, control, 1)," &
"720 (bc_1, vout1_g_y_yc1, input, X)," &
"721 (bc_1, vout1_g_y_yc1, output3, X, 722, 1, Z)," &
"722 (bc_1, *, control, 1)," &
"723 (bc_1, vout0_fid, input, X)," &
"724 (bc_1, vout0_fid, output3, X, 725, 1, Z)," &
"725 (bc_1, *, control, 1)," &
"726 (bc_1, vin0_fld1, input, X)," &
"727 (bc_1, vin0_fld1, output3, X, 728, 1, Z)," &
"728 (bc_1, *, control, 1)," &
"729 (bc_1, vin0_fld0_mux1, input, X)," &
"730 (bc_1, vin0_fld0_mux1, output3, X, 731, 1, Z)," &
"731 (bc_1, *, control, 1)," &
"732 (bc_1, vin0_de1, input, X)," &
"733 (bc_1, vin0_de1, output3, X, 734, 1, Z)," &
"734 (bc_1, *, control, 1)," &
"735 (bc_1, vin0_de0_mux1, input, X)," &
"736 (bc_1, vin0_de0_mux1, output3, X, 737, 1, Z)," &
"737 (bc_1, *, control, 1)," &
"738 (bc_1, vin0_d23, input, X)," &
"739 (bc_1, vin0_d23, output3, X, 740, 1, Z)," &
"740 (bc_1, *, control, 1)," &
"741 (bc_1, vin0_d22, input, X)," &
"742 (bc_1, vin0_d22, output3, X, 743, 1, Z)," &
"743 (bc_1, *, control, 1)," &
"744 (bc_1, vin0_d21, input, X)," &
"745 (bc_1, vin0_d21, output3, X, 746, 1, Z)," &
"746 (bc_1, *, control, 1)," &
"747 (bc_1, vin0_d20, input, X)," &
"748 (bc_1, vin0_d20, output3, X, 749, 1, Z)," &
"749 (bc_1, *, control, 1)," &
"750 (bc_1, vin0_d19, input, X)," &
"751 (bc_1, vin0_d19, output3, X, 752, 1, Z)," &
"752 (bc_1, *, control, 1)," &
"753 (bc_1, vin0_d18, input, X)," &
"754 (bc_1, vin0_d18, output3, X, 755, 1, Z)," &
"755 (bc_1, *, control, 1)," &
"756 (bc_1, vin0_d17, input, X)," &
"757 (bc_1, vin0_d17, output3, X, 758, 1, Z)," &
"758 (bc_1, *, control, 1)," &
"759 (bc_1, vin0_d16, input, X)," &
"760 (bc_1, vin0_d16, output3, X, 761, 1, Z)," &
"761 (bc_1, *, control, 1)," &
"762 (bc_1, vin0_clk1, input, X)," &
"763 (bc_1, vin0_clk1, output3, X, 764, 1, Z)," &
"764 (bc_1, *, control, 1)," &
"765 (bc_1, vin0_de0_mux0, input, X)," &
"766 (bc_1, vin0_de0_mux0, output3, X, 767, 1, Z)," &
"767 (bc_1, *, control, 1)," &
"768 (bc_1, vin0_fld0_mux0, input, X)," &
"769 (bc_1, vin0_fld0_mux0, output3, X, 770, 1, Z)," &
"770 (bc_1, *, control, 1)," &
"771 (bc_1, vin0_clk0, input, X)," &
"772 (bc_1, vin0_clk0, output3, X, 773, 1, Z)," &
"773 (bc_1, *, control, 1)," &
"774 (bc_1, vin0_hsync0, input, X)," &
"775 (bc_1, vin0_hsync0, output3, X, 776, 1, Z)," &
"776 (bc_1, *, control, 1)," &
"777 (bc_1, vin0_vsync0, input, X)," &
"778 (bc_1, vin0_vsync0, output3, X, 779, 1, Z)," &
"779 (bc_1, *, control, 1)," &
"780 (bc_1, vin0_d15, input, X)," &
"781 (bc_1, vin0_d15, output3, X, 782, 1, Z)," &
"782 (bc_1, *, control, 1)," &
"783 (bc_1, vin0_d14, input, X)," &
"784 (bc_1, vin0_d14, output3, X, 785, 1, Z)," &
"785 (bc_1, *, control, 1)," &
"786 (bc_1, vin0_d13, input, X)," &
"787 (bc_1, vin0_d13, output3, X, 788, 1, Z)," &
"788 (bc_1, *, control, 1)," &
"789 (bc_1, vin0_d12, input, X)," &
"790 (bc_1, vin0_d12, output3, X, 791, 1, Z)," &
"791 (bc_1, *, control, 1)," &
"792 (bc_1, vin0_d11, input, X)," &
"793 (bc_1, vin0_d11, output3, X, 794, 1, Z)," &
"794 (bc_1, *, control, 1)," &
"795 (bc_1, vin0_d10, input, X)," &
"796 (bc_1, vin0_d10, output3, X, 797, 1, Z)," &
"797 (bc_1, *, control, 1)," &
"798 (bc_1, vin0_d9, input, X)," &
"799 (bc_1, vin0_d9, output3, X, 800, 1, Z)," &
"800 (bc_1, *, control, 1)," &
"801 (bc_1, vin0_d8, input, X)," &
"802 (bc_1, vin0_d8, output3, X, 803, 1, Z)," &
"803 (bc_1, *, control, 1)," &
"804 (bc_1, vin0_d7, input, X)," &
"805 (bc_1, vin0_d7, output3, X, 806, 1, Z)," &
"806 (bc_1, *, control, 1)," &
"807 (bc_1, vin0_d6, input, X)," &
"808 (bc_1, vin0_d6, output3, X, 809, 1, Z)," &
"809 (bc_1, *, control, 1)," &
"810 (bc_1, vin0_d5, input, X)," &
"811 (bc_1, vin0_d5, output3, X, 812, 1, Z)," &
"812 (bc_1, *, control, 1)," &
"813 (bc_1, vin0_d4, input, X)," &
"814 (bc_1, vin0_d4, output3, X, 815, 1, Z)," &
"815 (bc_1, *, control, 1)," &
"816 (bc_1, vin0_d3, input, X)," &
"817 (bc_1, vin0_d3, output3, X, 818, 1, Z)," &
"818 (bc_1, *, control, 1)," &
"819 (bc_1, vin0_d2, input, X)," &
"820 (bc_1, vin0_d2, output3, X, 821, 1, Z)," &
"821 (bc_1, *, control, 1)," &
"822 (bc_1, vin0_d1, input, X)," &
"823 (bc_1, vin0_d1, output3, X, 824, 1, Z)," &
"824 (bc_1, *, control, 1)," &
"825 (bc_1, vin0_d0, input, X)," &
"826 (bc_1, vin0_d0, output3, X, 827, 1, Z)," &
"827 (bc_1, *, control, 1)," &
"828 (bc_1, emu1, input, X)," &
"829 (bc_1, emu1, output3, X, 830, 1, Z)," &
"830 (bc_1, *, control, 1)," &
"831 (bc_1, emu0, input, X)," &
"832 (bc_1, emu0, output3, X, 833, 1, Z)," &
"833 (bc_1, *, control, 1)," &
"834 (bc_1, vout0_clk, input, X)," &
"835 (bc_1, vout0_clk, output3, X, 836, 1, Z)," &
"836 (bc_1, *, control, 1)," &
"837 (bc_1, vout0_hsync, input, X)," &
"838 (bc_1, vout0_hsync, output3, X, 839, 1, Z)," &
"839 (bc_1, *, control, 1)," &
"840 (bc_1, vout0_vsync, input, X)," &
"841 (bc_1, vout0_vsync, output3, X, 842, 1, Z)," &
"842 (bc_1, *, control, 1)," &
"843 (bc_1, vout0_avid, input, X)," &
"844 (bc_1, vout0_avid, output3, X, 845, 1, Z)," &
"845 (bc_1, *, control, 1)," &
"846 (bc_1, vout0_b_cb_c2, input, X)," &
"847 (bc_1, vout0_b_cb_c2, output3, X, 848, 1, Z)," &
"848 (bc_1, *, control, 1)," &
"849 (bc_1, vout0_b_cb_c3, input, X)," &
"850 (bc_1, vout0_b_cb_c3, output3, X, 851, 1, Z)," &
"851 (bc_1, *, control, 1)," &
"852 (bc_1, vout0_b_cb_c4, input, X)," &
"853 (bc_1, vout0_b_cb_c4, output3, X, 854, 1, Z)," &
"854 (bc_1, *, control, 1)," &
"855 (bc_1, vout0_b_cb_c5, input, X)," &
"856 (bc_1, vout0_b_cb_c5, output3, X, 857, 1, Z)," &
"857 (bc_1, *, control, 1)," &
"858 (bc_1, vout0_b_cb_c6, input, X)," &
"859 (bc_1, vout0_b_cb_c6, output3, X, 860, 1, Z)," &
"860 (bc_1, *, control, 1)," &
"861 (bc_1, vout0_b_cb_c7, input, X)," &
"862 (bc_1, vout0_b_cb_c7, output3, X, 863, 1, Z)," &
"863 (bc_1, *, control, 1)," &
"864 (bc_1, vout0_b_cb_c8, input, X)," &
"865 (bc_1, vout0_b_cb_c8, output3, X, 866, 1, Z)," &
"866 (bc_1, *, control, 1)," &
"867 (bc_1, vout0_b_cb_c9, input, X)," &
"868 (bc_1, vout0_b_cb_c9, output3, X, 869, 1, Z)," &
"869 (bc_1, *, control, 1)," &
"870 (bc_1, vout0_g_y_yc2, input, X)," &
"871 (bc_1, vout0_g_y_yc2, output3, X, 872, 1, Z)," &
"872 (bc_1, *, control, 1)," &
"873 (bc_1, vout0_g_y_yc3, input, X)," &
"874 (bc_1, vout0_g_y_yc3, output3, X, 875, 1, Z)," &
"875 (bc_1, *, control, 1)," &
"876 (bc_1, vout0_g_y_yc4, input, X)," &
"877 (bc_1, vout0_g_y_yc4, output3, X, 878, 1, Z)," &
"878 (bc_1, *, control, 1)," &
"879 (bc_1, vout0_g_y_yc5, input, X)," &
"880 (bc_1, vout0_g_y_yc5, output3, X, 881, 1, Z)," &
"881 (bc_1, *, control, 1)," &
"882 (bc_1, vout0_g_y_yc6, input, X)," &
"883 (bc_1, vout0_g_y_yc6, output3, X, 884, 1, Z)," &
"884 (bc_1, *, control, 1)," &
"885 (bc_1, vout0_g_y_yc7, input, X)," &
"886 (bc_1, vout0_g_y_yc7, output3, X, 887, 1, Z)," &
"887 (bc_1, *, control, 1)," &
"888 (bc_1, vout0_g_y_yc8, input, X)," &
"889 (bc_1, vout0_g_y_yc8, output3, X, 890, 1, Z)," &
"890 (bc_1, *, control, 1)," &
"891 (bc_1, vout0_g_y_yc9, input, X)," &
"892 (bc_1, vout0_g_y_yc9, output3, X, 893, 1, Z)," &
"893 (bc_1, *, control, 1)," &
"894 (bc_1, vout0_r_cr2, input, X)," &
"895 (bc_1, vout0_r_cr2, output3, X, 896, 1, Z)," &
"896 (bc_1, *, control, 1)," &
"897 (bc_1, vout0_r_cr3, input, X)," &
"898 (bc_1, vout0_r_cr3, output3, X, 899, 1, Z)," &
"899 (bc_1, *, control, 1)," &
"900 (bc_1, vout0_r_cr4, input, X)," &
"901 (bc_1, vout0_r_cr4, output3, X, 902, 1, Z)," &
"902 (bc_1, *, control, 1)," &
"903 (bc_1, vout0_r_cr5, input, X)," &
"904 (bc_1, vout0_r_cr5, output3, X, 905, 1, Z)," &
"905 (bc_1, *, control, 1)," &
"906 (bc_1, vout0_r_cr6, input, X)," &
"907 (bc_1, vout0_r_cr6, output3, X, 908, 1, Z)," &
"908 (bc_1, *, control, 1)," &
"909 (bc_1, vout0_r_cr7, input, X)," &
"910 (bc_1, vout0_r_cr7, output3, X, 911, 1, Z)," &
"911 (bc_1, *, control, 1)," &
"912 (bc_1, vout0_r_cr8, input, X)," &
"913 (bc_1, vout0_r_cr8, output3, X, 914, 1, Z)," &
"914 (bc_1, *, control, 1)," &
"915 (bc_1, vout0_r_cr9, input, X)," &
"916 (bc_1, vout0_r_cr9, output3, X, 917, 1, Z)," &
"917 (bc_1, *, control, 1)," &
"918 (bc_1, usb_drvvbus, input, X)," &
"919 (bc_1, usb_drvvbus, output3, X, 920, 1, Z)," &
"920 (bc_1, *, control, 1)," &
"921 (bc_1, dcan0_tx, input, X)," &
"922 (bc_1, dcan0_tx, output3, X, 923, 1, Z)," &
"923 (bc_1, *, control, 1)," &
"924 (bc_1, uart0_rxd, input, X)," &
"925 (bc_1, uart0_rxd, output3, X, 926, 1, Z)," &
"926 (bc_1, *, control, 1)," &
"927 (bc_1, uart0_txd, input, X)," &
"928 (bc_1, uart0_txd, output3, X, 929, 1, Z)," &
"929 (bc_1, *, control, 1)," &
"930 (bc_1, uart0_ctsn, input, X)," &
"931 (bc_1, uart0_ctsn, output3, X, 932, 1, Z)," &
"932 (bc_1, *, control, 1)," &
"933 (bc_1, uart0_rtsn, input, X)," &
"934 (bc_1, uart0_rtsn, output3, X, 935, 1, Z)," &
"935 (bc_1, *, control, 1)," &
"936 (bc_1, uart0_dcdn, input, X)," &
"937 (bc_1, uart0_dcdn, output3, X, 938, 1, Z)," &
"938 (bc_1, *, control, 1)," &
"939 (bc_1, uart0_dsrn, input, X)," &
"940 (bc_1, uart0_dsrn, output3, X, 941, 1, Z)," &
"941 (bc_1, *, control, 1)," &
"942 (bc_1, uart0_dtrn, input, X)," &
"943 (bc_1, uart0_dtrn, output3, X, 944, 1, Z)," &
"944 (bc_1, *, control, 1)," &
"945 (bc_1, uart0_rin, input, X)," &
"946 (bc_1, uart0_rin, output3, X, 947, 1, Z)," &
"947 (bc_1, *, control, 1)," &
"948 (bc_1, spi0_cs1, input, X)," &
"949 (bc_1, spi0_cs1, output3, X, 950, 1, Z)," &
"950 (bc_1, *, control, 1)," &
"951 (bc_1, dcan0_rx, input, X)," &
"952 (bc_1, dcan0_rx, output3, X, 953, 1, Z)," &
"953 (bc_1, *, control, 1)," &
"954 (bc_1, spi0_cs0, input, X)," &
"955 (bc_1, spi0_cs0, output3, X, 956, 1, Z)," &
"956 (bc_1, *, control, 1)," &
"957 (bc_1, spi0_sclk, input, X)," &
"958 (bc_1, spi0_sclk, output3, X, 959, 1, Z)," &
"959 (bc_1, *, control, 1)," &
"960 (bc_1, spi0_d1, input, X)," &
"961 (bc_1, spi0_d1, output3, X, 962, 1, Z)," &
"962 (bc_1, *, control, 1)," &
"963 (bc_1, spi0_d0, input, X)," &
"964 (bc_1, spi0_d0, output3, X, 965, 1, Z)," &
"965 (bc_1, *, control, 1)," &
"966 (bc_1, spi1_cs0, input, X)," &
"967 (bc_1, spi1_cs0, output3, X, 968, 1, Z)," &
"968 (bc_1, *, control, 1)," &
"969 (bc_1, spi1_sclk, input, X)," &
"970 (bc_1, spi1_sclk, output3, X, 971, 1, Z)," &
"971 (bc_1, *, control, 1)," &
"972 (bc_1, spi1_d1, input, X)," &
"973 (bc_1, spi1_d1, output3, X, 974, 1, Z)," &
"974 (bc_1, *, control, 1)," &
"975 (bc_1, spi1_d0, input, X)," &
"976 (bc_1, spi1_d0, output3, X, 977, 1, Z)," &
"977 (bc_1, *, control, 1)," &
"978 (bc_1, i2c0_scl, input, X)," &
"979 (bc_1, i2c0_scl, output2, 1, 979, 1, Weak1)," &
"980 (bc_4, *, internal, 0)," &
"981 (bc_1, i2c0_sda, input, X)," &
"982 (bc_1, i2c0_sda, output2, 1, 982, 1, Weak1)," &
"983 (bc_4, *, internal, 0)," &
"984 (bc_1, mlbp_dat_p, input, X)," &
"985 (bc_1, mlbp_dat_p, output3, X, 986, 1, Z)," &
"986 (bc_1, *, control, 1)," &
"987 (bc_1, mlbp_dat_n, input, X)," &
"988 (bc_1, mlbp_dat_n, output3, X, 989, 1, Z)," &
"989 (bc_1, *, control, 1)," &
"990 (bc_1, mlbp_sig_p, input, X)," &
"991 (bc_1, mlbp_sig_p, output3, X, 992, 1, Z)," &
"992 (bc_1, *, control, 1)," &
"993 (bc_1, mlbp_sig_n, input, X)," &
"994 (bc_1, mlbp_sig_n, output3, X, 995, 1, Z)," &
"995 (bc_1, *, control, 1)," &
"996 (bc_1, mlb_sig, input, X)," &
"997 (bc_1, mlb_sig, output3, X, 998, 1, Z)," &
"998 (bc_1, *, control, 1)," &
"999 (bc_1, mlb_clk, input, X)," &
"1000 (bc_1, mlb_clk, output3, X, 1004, 1, Z)," &
"1001 (bc_1, *, control, 1)," &
"1002 (bc_1, mlb_dat, input, X)," &
"1003 (bc_1, mlb_dat, output3, X, 1001, 1, Z)," &
"1004 (bc_1, *, control, 1)," &
"1005 (bc_1, osc_wake, input, X)," &
"1006 (bc_1, osc_wake, output3, X, 1007, 1, Z)," &
"1007 (bc_1, *, control, 1)," &
"1008 (bc_1, mmc1_clk, input, X)," &
"1009 (bc_1, mmc1_clk, output3, X, 1010, 1, Z)," &
"1010 (bc_1, *, control, 1)," &
"1011 (bc_1, mmc1_cmd, input, X)," &
"1012 (bc_1, mmc1_cmd, output3, X, 1013, 1, Z)," &
"1013 (bc_1, *, control, 1)," &
"1014 (bc_1, mmc1_dat0, input, X)," &
"1015 (bc_1, mmc1_dat0, output3, X, 1016, 1, Z)," &
"1016 (bc_1, *, control, 1)," &
"1017 (bc_1, mmc1_dat1, input, X)," &
"1018 (bc_1, mmc1_dat1, output3, X, 1019, 1, Z)," &
"1019 (bc_1, *, control, 1)," &
"1020 (bc_1, mmc1_dat2, input, X)," &
"1021 (bc_1, mmc1_dat2, output3, X, 1022, 1, Z)," &
"1022 (bc_1, *, control, 1)," &
"1023 (bc_1, mmc1_dat3, input, X)," &
"1024 (bc_1, mmc1_dat3, output3, X, 1025, 1, Z)," &
"1025 (bc_1, *, control, 1)," &
"1026 (bc_1, mmc0_dat3, input, X)," &
"1027 (bc_1, mmc0_dat3, output3, X, 1028, 1, Z)," &
"1028 (bc_1, *, control, 1)," &
"1029 (bc_1, mmc0_dat2, input, X)," &
"1030 (bc_1, mmc0_dat2, output3, X, 1031, 1, Z)," &
"1031 (bc_1, *, control, 1)," &
"1032 (bc_1, mmc0_dat1, input, X)," &
"1033 (bc_1, mmc0_dat1, output3, X, 1034, 1, Z)," &
"1034 (bc_1, *, control, 1)," &
"1035 (bc_1, mmc0_dat0, input, X)," &
"1036 (bc_1, mmc0_dat0, output3, X, 1037, 1, Z)," &
"1037 (bc_1, *, control, 1)," &
"1038 (bc_1, mmc0_cmd, input, X)," &
"1039 (bc_1, mmc0_cmd, output3, X, 1040, 1, Z)," &
"1040 (bc_1, *, control, 1)," &
"1041 (bc_1, mmc0_clk, input, X)," &
"1042 (bc_1, mmc0_clk, output3, X, 1043, 1, Z)," &
"1043 (bc_1, *, control, 1)," &
"1044 (bc_1, mcasp2_clkx, input, X)," &
"1045 (bc_1, mcasp2_clkx, output3, X, 1046, 1, Z)," &
"1046 (bc_1, *, control, 1)," &
"1047 (bc_1, mcasp2_fsx, input, X)," &
"1048 (bc_1, mcasp2_fsx, output3, X, 1049, 1, Z)," &
"1049 (bc_1, *, control, 1)," &
"1050 (bc_1, mcasp2_axr0, input, X)," &
"1051 (bc_1, mcasp2_axr0, output3, X, 1052, 1, Z)," &
"1052 (bc_1, *, control, 1)," &
"1053 (bc_1, mcasp2_axr1, input, X)," &
"1054 (bc_1, mcasp2_axr1, output3, X, 1055, 1, Z)," &
"1055 (bc_1, *, control, 1)," &
"1056 (bc_1, mcasp2_axr2, input, X)," &
"1057 (bc_1, mcasp2_axr2, output3, X, 1058, 1, Z)," &
"1058 (bc_1, *, control, 1)," &
"1059 (bc_1, mcasp1_axr1, input, X)," &
"1060 (bc_1, mcasp1_axr1, output3, X, 1061, 1, Z)," &
"1061 (bc_1, *, control, 1)," &
"1062 (bc_1, mcasp1_axr0, input, X)," &
"1063 (bc_1, mcasp1_axr0, output3, X, 1064, 1, Z)," &
"1064 (bc_1, *, control, 1)," &
"1065 (bc_1, mcasp1_fsx, input, X)," &
"1066 (bc_1, mcasp1_fsx, output3, X, 1067, 1, Z)," &
"1067 (bc_1, *, control, 1)," &
"1068 (bc_1, mcasp1_aclkx, input, X)," &
"1069 (bc_1, mcasp1_aclkx, output3, X, 1070, 1, Z)," &
"1070 (bc_1, *, control, 1)," &
"1071 (bc_1, mcasp1_axr3, input, X)," &
"1072 (bc_1, mcasp1_axr3, output3, X, 1073, 1, Z)," &
"1073 (bc_1, *, control, 1)," &
"1074 (bc_1, mcasp1_axr2, input, X)," &
"1075 (bc_1, mcasp1_axr2, output3, X, 1076, 1, Z)," &
"1076 (bc_1, *, control, 1)," &
"1077 (bc_1, mcasp1_fsr, input, X)," &
"1078 (bc_1, mcasp1_fsr, output3, X, 1079, 1, Z)," &
"1079 (bc_1, *, control, 1)," &
"1080 (bc_1, mcasp1_clkr, input, X)," &
"1081 (bc_1, mcasp1_clkr, output3, X, 1082, 1, Z)," &
"1082 (bc_1, *, control, 1)," &
"1083 (bc_1, mcasp0_axr3, input, X)," &
"1084 (bc_1, mcasp0_axr3, output3, X, 1085, 1, Z)," &
"1085 (bc_1, *, control, 1)," &
"1086 (bc_1, mcasp0_axr4, input, X)," &
"1087 (bc_1, mcasp0_axr4, output3, X, 1088, 1, Z)," &
"1088 (bc_1, *, control, 1)," &
"1089 (bc_1, mcasp0_axr5, input, X)," &
"1090 (bc_1, mcasp0_axr5, output3, X, 1091, 1, Z)," &
"1091 (bc_1, *, control, 1)," &
"1092 (bc_1, mcasp0_axr6, input, X)," &
"1093 (bc_1, mcasp0_axr6, output3, X, 1094, 1, Z)," &
"1094 (bc_1, *, control, 1)," &
"1095 (bc_1, mcasp0_axr7, input, X)," &
"1096 (bc_1, mcasp0_axr7, output3, X, 1097, 1, Z)," &
"1097 (bc_1, *, control, 1)," &
"1098 (bc_1, mcasp0_axr8, input, X)," &
"1099 (bc_1, mcasp0_axr8, output3, X, 1100, 1, Z)," &
"1100 (bc_1, *, control, 1)," &
"1101 (bc_1, mcasp0_axr9, input, X)," &
"1102 (bc_1, mcasp0_axr9, output3, X, 1103, 1, Z)," &
"1103 (bc_1, *, control, 1)," &
"1104 (bc_1, mcasp0_aclkx, input, X)," &
"1105 (bc_1, mcasp0_aclkx, output3, X, 1106, 1, Z)," &
"1106 (bc_1, *, control, 1)," &
"1107 (bc_1, mcasp0_fsx, input, X)," &
"1108 (bc_1, mcasp0_fsx, output3, X, 1109, 1, Z)," &
"1109 (bc_1, *, control, 1)," &
"1110 (bc_1, mcasp0_clkr, input, X)," &
"1111 (bc_1, mcasp0_clkr, output3, X, 1112, 1, Z)," &
"1112 (bc_1, *, control, 1)," &
"1113 (bc_1, mcasp0_axr2, input, X)," &
"1114 (bc_1, mcasp0_axr2, output3, X, 1115, 1, Z)," &
"1115 (bc_1, *, control, 1)," &
"1116 (bc_1, mcasp0_axr1, input, X)," &
"1117 (bc_1, mcasp0_axr1, output3, X, 1118, 1, Z)," &
"1118 (bc_1, *, control, 1)," &
"1119 (bc_1, mcasp0_axr0, input, X)," &
"1120 (bc_1, mcasp0_axr0, output3, X, 1121, 1, Z)," &
"1121 (bc_1, *, control, 1)," &
"1122 (bc_1, mcasp0_fsr, input, X)," &
"1123 (bc_1, mcasp0_fsr, output3, X, 1124, 1, Z)," &
"1124 (bc_1, *, control, 1)," &
"1125 (bc_1, xref_clk0, input, X)," &
"1126 (bc_1, xref_clk0, output3, X, 1127, 1, Z)," &
"1127 (bc_1, *, control, 1)," &
"1128 (bc_1, xref_clk1, input, X)," &
"1129 (bc_1, xref_clk1, output3, X, 1130, 1, Z)," &
"1130 (bc_1, *, control, 1)," &
"1131 (bc_1, xref_clk2, input, X)," &
"1132 (bc_1, xref_clk2, output3, X, 1133, 1, Z)," &
"1133 (bc_1, *, control, 1)," &
"1134 (bc_1, mcasp2_axr3, input, X)," &
"1135 (bc_1, mcasp2_axr3, output3, X, 1136, 1, Z)," &
"1136 (bc_1, *, control, 1)," &
"1137 (bc_1, mcasp5_clkx, input, X)," &
"1138 (bc_1, mcasp5_clkx, output3, X, 1139, 1, Z)," &
"1139 (bc_1, *, control, 1)," &
"1140 (bc_1, mcasp5_fsx, input, X)," &
"1141 (bc_1, mcasp5_fsx, output3, X, 1142, 1, Z)," &
"1142 (bc_1, *, control, 1)," &
"1143 (bc_1, mcasp5_axr0, input, X)," &
"1144 (bc_1, mcasp5_axr0, output3, X, 1145, 1, Z)," &
"1145 (bc_1, *, control, 1)," &
"1146 (bc_1, mcasp5_axr1, input, X)," &
"1147 (bc_1, mcasp5_axr1, output3, X, 1148, 1, Z)," &
"1148 (bc_1, *, control, 1)," &
"1149 (bc_1, mcasp4_axr1, input, X)," &
"1150 (bc_1, mcasp4_axr1, output3, X, 1151, 1, Z)," &
"1151 (bc_1, *, control, 1)," &
"1152 (bc_1, mcasp4_axr0, input, X)," &
"1153 (bc_1, mcasp4_axr0, output3, X, 1154, 1, Z)," &
"1154 (bc_1, *, control, 1)," &
"1155 (bc_1, mcasp4_fsx, input, X)," &
"1156 (bc_1, mcasp4_fsx, output3, X, 1157, 1, Z)," &
"1157 (bc_1, *, control, 1)," &
"1158 (bc_1, mcasp4_clkx, input, X)," &
"1159 (bc_1, mcasp4_clkx, output3, X, 1160, 1, Z)," &
"1160 (bc_1, *, control, 1)," &
"1161 (bc_1, mcasp3_axr3, input, X)," &
"1162 (bc_1, mcasp3_axr3, output3, X, 1163, 1, Z)," &
"1163 (bc_1, *, control, 1)," &
"1164 (bc_1, mcasp3_axr2, input, X)," &
"1165 (bc_1, mcasp3_axr2, output3, X, 1166, 1, Z)," &
"1166 (bc_1, *, control, 1)," &
"1167 (bc_1, mcasp3_axr1, input, X)," &
"1168 (bc_1, mcasp3_axr1, output3, X, 1169, 1, Z)," &
"1169 (bc_1, *, control, 1)," &
"1170 (bc_1, mcasp3_axr0, input, X)," &
"1171 (bc_1, mcasp3_axr0, output3, X, 1172, 1, Z)," &
"1172 (bc_1, *, control, 1)," &
"1173 (bc_1, mcasp3_fsx, input, X)," &
"1174 (bc_1, mcasp3_fsx, output3, X, 1175, 1, Z)," &
"1175 (bc_1, *, control, 1)," &
"1176 (bc_1, mcasp3_clkx, input, X)," &
"1177 (bc_1, mcasp3_clkx, output3, X, 1178, 1, Z)," &
"1178 (bc_1, *, control, 1)," &
"1179 (bc_1, resetn, input, X)," &
"1180 (bc_1, resetn, output3, X, 1181, 1, Z)," &
"1181 (bc_1, *, control, 1)," &
"1182 (bc_1, nmin, input, X)," &
"1183 (bc_1, nmin, output3, X, 1184, 1, Z)," &
"1184 (bc_1, *, control, 1)," &
"1185 (bc_1, rstoutn, input, X)," &
"1186 (bc_1, rstoutn, output3, X, 1187, 1, Z)," &
"1187 (bc_1, *, control, 1)," &
"1188 (bc_1, clkin32, input, X)," &
"1189 (bc_1, clkin32, output3, X, 1190, 1, Z)," &
"1190 (bc_1, *, control, 1)";
attribute DESIGN_WARNING of TMS320CENTAURUS: entity is
"According to simulation, BSD JTAG TAP may not work correctly unless " &
"device has completed Power on Reset sequence first. If the BSDL tool " &
"does not use trstn pin, please put a 10K Ohm pull up resistor on this pin. " ;
end TMS320CENTAURUS;