-- ***********************************************************************
-- BSDL file for design IDT82V2108
-- Created by Synopsys Version 1999.10 (Sep 02, 1999)
-- Designer:
-- Company: Integrated Device Technology, Inc
-- Date: Thu May 9 19:06:06 2002
-- Revision: C
-- ***********************************************************************
entity IDT82V2108 is
-- This section identifies the default device package selected.
generic (PHYSICAL_PIN_MAP: string:= "QFP128");
-- This section declares all the ports in the design.
port (
ALE : in bit;
TSCCKB_MTSCCKB : in bit;
TSCFS_MTSCFS : in bit;
RSCCK_MRSCCK : in bit;
RSCFS_MRSCFS : in bit;
CSB : in bit;
TSCCKA : in bit;
RDB : in bit;
RSTB : in bit;
TCK : in bit;
TDI : in bit;
TESTSE : in bit;
TMS : in bit;
TRSTB : in bit;
WRB : in bit;
XCK : in bit;
A : in bit_vector (0 to 10);
TSD : in bit_vector (3 to 8);
TSD_MTSD : in bit_vector (1 to 2);
LRCK : in bit_vector (1 to 8);
LRD : in bit_vector (1 to 8);
D : inout bit_vector (0 to 7);
TSFS_TSSIG : inout bit_vector (3 to 8);
TSFS_TSSIG_MTSSIG : inout bit_vector (1 to 2);
RSCK_RSSIG : inout bit_vector (3 to 8);
RSCK_RSSIG_MRSSIG : inout bit_vector (1 to 2);
RSD : inout bit_vector (3 to 8);
RSD_MRSD : inout bit_vector (1 to 2);
INTB : linkage bit;
TDO : out bit;
RSFS : buffer bit_vector (3 to 8);
RSFS_MRSFS : buffer bit_vector (1 to 2);
LTCK : buffer bit_vector (1 to 8);
LTD : buffer bit_vector (1 to 8);
BIAS : linkage bit;
PHA : linkage bit_vector (0 to 3);
PHD : linkage bit_vector (0 to 4);
PLA : linkage bit_vector (0 to 3);
PLD : linkage bit_vector (0 to 4)
);
use STD_1149_1_1994.all;
attribute COMPONENT_CONFORMANCE of IDT82V2108: entity is "STD_1149_1_1993";
attribute PIN_MAP of IDT82V2108: entity is PHYSICAL_PIN_MAP;
-- This section specifies the pin map for each port. This information
-- is extracted from the port-to-pin map file that was read in using
-- the "read_pin_map" command.
constant QFP128: PIN_MAP_STRING :=
"ALE : 53," &
"TSCCKB_MTSCCKB : 122," &
"TSCFS_MTSCFS : 121," &
"RSCCK_MRSCCK : 120," &
"RSCFS_MRSCFS : 119," &
"CSB : 65," &
"TSCCKA : 123," &
"RDB : 67," &
"RSTB : 39," &
"TCK : 126," &
"TDI : 127," &
"TESTSE : 108," &
"TMS : 128," &
"TRSTB : 125," &
"WRB : 66," &
"XCK : 117," &
"A : (54, 55, 56, 57, 58, 59, 60, 61, 62, 63" &
", 64)," &
"TSD : (111, 109, 105, 103, 101, 99)," &
"TSD_MTSD : (115, 113)," &
"LRCK : (2, 4, 6, 8, 32, 34, 36, 38)," &
"LRD : (1, 3, 5, 7, 31, 33, 35, 37)," &
"D : (41, 42, 43, 44, 45, 46, 47, 48)," &
"TSFS_TSSIG : (110, 106, 104, 102, 100, 98)," &
"TSFS_TSSIG_MTSSIG : (114, 112)," &
"RSCK_RSSIG : (88, 83, 80, 77, 72, 69)," &
"RSCK_RSSIG_MRSSIG : (96, 91)," &
"RSD : (89, 84, 81, 78, 73, 70)," &
"RSD_MRSD : (97, 94)," &
"INTB : 40," &
"TDO : 124," &
"RSFS : (87, 82, 79, 76, 71, 68)," &
"RSFS_MRSFS : (95, 90)," &
"LTCK : (10, 12, 14, 16, 23, 25, 27, 29)," &
"LTD : (9, 11, 13, 15, 22, 24, 26, 28)," &
"BIAS : 17," &
"PHA : (18, 49, 74, 107)," &
"PHD : (20, 51, 85, 92, 116)," &
"PLA : (19, 50, 75, 30)," &
"PLD : (21, 52, 86, 93, 118)";
-- This section specifies the TAP ports.
-- For the TAP TCK port, the parameters in the brackets are:
-- First Field : Maximum TCK frequency.
-- Second Field: Allowable states TCK may be stopped in.
attribute TAP_SCAN_CLOCK of TCK : signal is (10.0e6, BOTH);
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_RESET of TRSTB: signal is true;
-- Specifies the number of bits in the instruction register.
attribute INSTRUCTION_LENGTH of IDT82V2108: entity is 3;
-- Specifies the boundary-scan instructions implemented in the
-- design and their opcodes.
attribute INSTRUCTION_OPCODE of IDT82V2108: entity is
"BYPASS (111)," &
"EXTEST (000)," &
"SAMPLE (010)," &
"USER1 (100)," &
"HIGHZ (101)," &
"USER2 (110)," &
"IDCODE (001)," &
"USER3 (011)";
-- Specifies the bit pattern that is loaded into the instruction
-- register when the TAP controller passes through the Capture-IR
-- state. The standard mandates that the two LSBs must be "01".
-- The remaining bits are design specific.
attribute INSTRUCTION_CAPTURE of IDT82V2108: entity is "001";
-- Specifies the bit pattern that is loaded into the DEVICE_ID
-- register during the IDCODE instruction when the TAP controller
-- passes through the Capture-DR state.
attribute IDCODE_REGISTER of IDT82V2108: entity is
"0010" & -- 4-bit version number
"0000010011010000" & -- 16-bit part number
"00000110011" & -- 11-bit identity of the manufacturer
"1"; -- Required by IEEE Std 1149.1
-- This section specifies the test data register placed between TDI
-- and TDO for each implemented instruction.
attribute REGISTER_ACCESS of IDT82V2108: entity is
"BYPASS (BYPASS, USER1, HIGHZ, USER2)," &
"BOUNDARY (EXTEST, SAMPLE)," &
"DEVICE_ID (IDCODE)," &
"UTDR1[8] (USER3)";
-- Specifies the length of the boundary scan register.
attribute BOUNDARY_LENGTH of IDT82V2108: entity is 128;
-- The following list specifies the characteristics of each cell
-- in the boundary scan register from TDI to TDO.
-- The following is a description of the label fields:
-- num : Is the cell number.
-- cell : Is the cell type as defined by the standard.
-- port : Is the design port name. Control cells do not
-- have a port name.
-- function: Is the function of the cell as defined by the
-- standard. Is one of input, output2, output3,
-- bidir, control or controlr.
-- safe : Specifies the value that the BSR cell should be
-- loaded with for safe operation when the software
-- might otherwise choose a random value.
-- ccell : The control cell number. Specifies the control
-- cell that drives the output enable for this port.
-- disval : Specifies the value that is loaded into the
-- control cell to disable the output enable for
-- the corresponding port.
-- rslt : Resulting state. Shows the state of the driver
-- when it is disabled.
attribute BOUNDARY_REGISTER of IDT82V2108: entity is
--
-- num cell port function safe [ccell disval rslt]
--
"127 (BC_1, LRD(1), input, " &
"X), " &
"126 (BC_1, LRCK(1), input, " &
"X), " &
"125 (BC_1, LRD(2), input, " &
"X), " &
"124 (BC_1, LRCK(2), input, " &
"X), " &
"123 (BC_1, LRD(3), input, " &
"X), " &
"122 (BC_1, LRCK(3), input, " &
"X), " &
"121 (BC_1, LRD(4), input, " &
"X), " &
"120 (BC_1, LRCK(4), input, " &
"X), " &
"119 (BC_1, LTD(1), output2, " &
"X), " &
"118 (BC_1, LTCK(1), output2, " &
"X), " &
"117 (BC_1, LTD(2), output2, " &
"X), " &
"116 (BC_1, LTCK(2), output2, " &
"X), " &
"115 (BC_1, LTD(3), output2, " &
"X), " &
"114 (BC_1, LTCK(3), output2, " &
"X), " &
"113 (BC_1, LTD(4), output2, " &
"X), " &
"112 (BC_1, LTCK(4), output2, " &
"X), " &
"111 (BC_1, LTD(5), output2, " &
"X), " &
"110 (BC_1, LTCK(5), output2, " &
"X), " &
"109 (BC_1, LTD(6), output2, " &
"X), " &
"108 (BC_1, LTCK(6), output2, " &
"X), " &
"107 (BC_1, LTD(7), output2, " &
"X), " &
"106 (BC_1, LTCK(7), output2, " &
"X), " &
"105 (BC_1, LTD(8), output2, " &
"X), " &
"104 (BC_1, LTCK(8), output2, " &
"X), " &
"103 (BC_1, LRD(5), input, " &
"X), " &
"102 (BC_1, LRCK(5), input, " &
"X), " &
"101 (BC_1, LRD(6), input, " &
"X), " &
"100 (BC_1, LRCK(6), input, " &
"X), " &
"99 (BC_1, LRD(7), input, " &
"X), " &
"98 (BC_1, LRCK(7), input, " &
"X), " &
"97 (BC_1, LRD(8), input, " &
"X), " &
"96 (BC_1, LRCK(8), input, " &
"X), " &
"95 (BC_1, RSTB, input, " &
"X), " &
"94 (BC_1, *, internal, " &
"X), " &
"93 (BC_2, *, control, " &
"0), " &
"92 (BC_7, D(0), bidir, X, 93, " &
"0, Z), " &
"91 (BC_7, D(1), bidir, X, 93, " &
"0, Z), " &
"90 (BC_7, D(2), bidir, X, 93, " &
"0, Z), " &
"89 (BC_7, D(3), bidir, X, 93, " &
"0, Z), " &
"88 (BC_7, D(4), bidir, X, 93, " &
"0, Z), " &
"87 (BC_7, D(5), bidir, X, 93, " &
"0, Z), " &
"86 (BC_7, D(6), bidir, X, 93, " &
"0, Z), " &
"85 (BC_7, D(7), bidir, X, 93, " &
"0, Z), " &
"84 (BC_1, ALE, input, " &
"X), " &
"83 (BC_1, A(0), input, " &
"X), " &
"82 (BC_1, A(1), input, " &
"X), " &
"81 (BC_1, A(2), input, " &
"X), " &
"80 (BC_1, A(3), input, " &
"X), " &
"79 (BC_1, A(4), input, " &
"X), " &
"78 (BC_1, A(5), input, " &
"X), " &
"77 (BC_1, A(6), input, " &
"X), " &
"76 (BC_1, A(7), input, " &
"X), " &
"75 (BC_1, A(8), input, " &
"X), " &
"74 (BC_1, A(9), input, " &
"X), " &
"73 (BC_1, A(10), input, " &
"X), " &
"72 (BC_1, CSB, input, " &
"X), " &
"71 (BC_1, WRB, input, " &
"X), " &
"70 (BC_1, RDB, input, " &
"X), " &
"69 (BC_1, RSFS(8), output2, " &
"X), " &
"68 (BC_7, RSCK_RSSIG(8), bidir, X, 67, " &
"0, Z), " &
"67 (BC_2, *, control, " &
"0), " &
"66 (BC_7, RSD(8), bidir, X, 65, " &
"0, Z), " &
"65 (BC_2, *, control, " &
"0), " &
"64 (BC_1, RSFS(7), output2, " &
"X), " &
"63 (BC_7, RSCK_RSSIG(7), bidir, X, 62, " &
"0, Z), " &
"62 (BC_2, *, control, " &
"0), " &
"61 (BC_7, RSD(7), bidir, X, 60, " &
"0, Z), " &
"60 (BC_2, *, control, " &
"0), " &
"59 (BC_1, RSFS(6), output2, " &
"X), " &
"58 (BC_7, RSCK_RSSIG(6), bidir, X, 57, " &
"0, Z), " &
"57 (BC_2, *, control, " &
"0), " &
"56 (BC_7, RSD(6), bidir, X, 55, " &
"0, Z), " &
"55 (BC_2, *, control, " &
"0), " &
"54 (BC_1, RSFS(5), output2, " &
"X), " &
"53 (BC_7, RSCK_RSSIG(5), bidir, X, 52, " &
"0, Z), " &
"52 (BC_2, *, control, " &
"0), " &
"51 (BC_7, RSD(5), bidir, X, 50, " &
"0, Z), " &
"50 (BC_2, *, control, " &
"0), " &
"49 (BC_1, RSFS(4), output2, " &
"X), " &
"48 (BC_7, RSCK_RSSIG(4), bidir, X, 47, " &
"0, Z), " &
"47 (BC_2, *, control, " &
"0), " &
"46 (BC_7, RSD(4), bidir, X, 45, " &
"0, Z), " &
"45 (BC_2, *, control, " &
"0), " &
"44 (BC_1, RSFS(3), output2, " &
"X), " &
"43 (BC_7, RSCK_RSSIG(3), bidir, X, 42, " &
"0, Z), " &
"42 (BC_2, *, control, " &
"0), " &
"41 (BC_7, RSD(3), bidir, X, 40, " &
"0, Z), " &
"40 (BC_2, *, control, " &
"0), " &
"39 (BC_1, RSFS_MRSFS(2), output2, " &
"X), " &
"38 (BC_7, RSCK_RSSIG_MRSSIG(2), bidir, X, 37, " &
"0, Z), " &
"37 (BC_2, *, control, " &
"0), " &
"36 (BC_7, RSD_MRSD(2), bidir, X, 35, " &
"0, Z), " &
"35 (BC_2, *, control, " &
"0), " &
"34 (BC_1, RSFS_MRSFS(1), output2, " &
"X), " &
"33 (BC_7, RSCK_RSSIG_MRSSIG(1), bidir, X, 32, " &
"0, Z), " &
"32 (BC_2, *, control, " &
"0), " &
"31 (BC_7, RSD_MRSD(1), bidir, X, 30, " &
"0, Z), " &
"30 (BC_2, *, control, " &
"0), " &
"29 (BC_7, TSFS_TSSIG(8), bidir, X, 28, " &
"0, Z), " &
"28 (BC_2, *, control, " &
"0), " &
"27 (BC_1, TSD(8), input, " &
"X), " &
"26 (BC_7, TSFS_TSSIG(7), bidir, X, 25, " &
"0, Z), " &
"25 (BC_2, *, control, " &
"0), " &
"24 (BC_1, TSD(7), input, " &
"X), " &
"23 (BC_7, TSFS_TSSIG(6), bidir, X, 22, " &
"0, Z), " &
"22 (BC_2, *, control, " &
"0), " &
"21 (BC_1, TSD(6), input, " &
"X), " &
"20 (BC_7, TSFS_TSSIG(5), bidir, X, 19, " &
"0, Z), " &
"19 (BC_2, *, control, " &
"0), " &
"18 (BC_1, TSD(5), input, " &
"X), " &
"17 (BC_7, TSFS_TSSIG(4), bidir, X, 16, " &
"0, Z), " &
"16 (BC_2, *, control, " &
"0), " &
"15 (BC_1, TSD(4), input, " &
"X), " &
"14 (BC_7, TSFS_TSSIG(3), bidir, X, 13, " &
"0, Z), " &
"13 (BC_2, *, control, " &
"0), " &
"12 (BC_1, TSD(3), input, " &
"X), " &
"11 (BC_7, TSFS_TSSIG_MTSSIG(2), bidir, X, 10, " &
"0, Z), " &
"10 (BC_2, *, control, " &
"0), " &
"9 (BC_1, TSD_MTSD(2), input, " &
"X), " &
"8 (BC_7, TSFS_TSSIG_MTSSIG(1), bidir, X, 7, " &
"0, Z), " &
"7 (BC_2, *, control, " &
"0), " &
"6 (BC_1, TSD_MTSD(1), input, " &
"X), " &
"5 (BC_1, XCK, input, " &
"X), " &
"4 (BC_1, RSCFS_MRSCFS, input, " &
"X), " &
"3 (BC_1, RSCCK_MRSCCK, input, " &
"X), " &
"2 (BC_1, TSCFS_MTSCFS, input, " &
"X), " &
"1 (BC_1, TSCCKB_MTSCCKB, input, " &
"X), " &
"0 (BC_1, TSCCKA, input, " &
"X) ";
end IDT82V2108;