-- Boundary Scan Description Language (BSDL) for IDT72T2098Z IC
-- File name : idt72t2098z.bsd
-- Last updated : 07/11/01
-- Documentation : Preliminary data sheet
-- Packages : 208 pin FBGA
entity IDT72T2098Z is
generic (PHYSICAL_PIN_MAP : string:="F208_FBGA");
port(PAFL: out bit;
FF_IR: out bit;
FWFT: in bit;
WCLK: in bit;
WENL: in bit;
WCSL: in bit;
FSEL0: in bit;
FSEL1: in bit;
MRSL: in bit;
PRSL: in bit;
IW: in bit;
OW: in bit;
RSDRL: in bit;
WSDRL: in bit;
D19: in bit;
D18: in bit;
D17: in bit;
D16: in bit;
D15: in bit;
D14: in bit;
D13: in bit;
D12: in bit;
D11: in bit;
D10: in bit;
Q19: out bit;
Q18: out bit;
Q17: out bit;
Q16: out bit;
Q15: out bit;
Q14: out bit;
Q13: out bit;
Q12: out bit;
Q11: out bit;
Q10: out bit;
ERCLK: out bit;
ERENL: out bit;
EF_OR: out bit;
PAEL: out bit;
SO: out bit;
SENOL: in bit;
SENL: in bit;
SCLK: in bit;
SI: in bit;
RCLK: in bit;
RENL: in bit;
RCSL: in bit;
OEL: in bit;
RTL: in bit;
MARK: in bit;
Q9: out bit;
Q8: out bit;
Q7: out bit;
Q6: out bit;
Q5: out bit;
Q4: out bit;
Q3: out bit;
Q2: out bit;
Q1: out bit;
Q0: out bit;
HSTL: in bit;
D9: in bit;
D8: in bit;
D7: in bit;
D6: in bit;
D5: in bit;
D4: in bit;
D3: in bit;
D2: in bit;
D1: in bit;
D0: in bit;
TCK, TMS, TDI, TRSTL: in bit;
TDO: out bit;
VREF: in bit;
VDDQ: linkage bit_vector(1 to 28);
VCC: linkage bit_vector(1 to 20);
GND: linkage bit_vector(1 to 40)
);
use STD_1149_1_1994.all;
attribute COMPONENT_CONFORMANCE of IDT72T2098Z: entity is "STD_1149_1_1993";
attribute PIN_MAP of IDT72T2098Z: entity is PHYSICAL_PIN_MAP;
constant FBGA : PIN_MAP_STRING :=
"D0:C3," &
"D1:A4," &
"D2:B4," &
"D3:C4," &
"D4:A5," &
"D5:B5," &
"D6:C5," &
"D7:A6," &
"D8:B6," &
"D9:A7," &
"D10:R7," &
"D11:T7," &
"D12:R6," &
"D13:T6," &
"D14:R5," &
"D15:T5," &
"D16:R4," &
"D17:T4," &
"D18:P3," &
"D19:R3," &
"Q0:B10," &
"Q1:A10," &
"Q2:B11," &
"Q3:A11," &
"Q4:B12," &
"Q5:A12," &
"Q6:B13," &
"Q7:A13," &
"Q8:B14," &
"Q9:A14," &
"Q10:T14," &
"Q11:R14," &
"Q12:T13," &
"Q13:R13," &
"Q14:T12," &
"Q15:R12," &
"Q16:T11," &
"Q17:R11," &
"Q18:T10," &
"Q19:R10," &
"WCLK:G1," &
"WENL:H1," &
"WCSL:H2," &
"MRSL:J1," &
"PRSL:K3," &
"FSEL1:J2," &
"FSEL0:J3," &
"IW:K1," &
"OW:L3," &
"WSDRL:L1," &
"RSDRL:L2," &
"FWFT:G2," &
"PAFL:G3," &
"FF_IR:H3," &
"EF_OR:M14," &
"PAEL:L15," &
"ERCLK:L16," &
"ERENL:K16," &
"SO:K15," &
"SENL:J15," &
"SENOL:J16," &
"SI:H16," &
"SCLK:H15," &
"OEL:G15," &
"RCLK:G16," &
"RENL:F16," &
"RTL:F15," &
"RCSL:F14," &
"MARK:E14," &
"HSTL:B7," &
"VREF:T3," &
"TCK:F1," &
"TDI:E2," &
"TMS:F2," &
"TRSTL:E3," &
"TDO:F3," &
"VCC:(A1, A2, C6, C7, D4, D5, D6, D7, K4, L4, " &
" M4, N4, N5, N6, N7, P5, P6, P7, T1, T2 )," &
"GND:(A8, A9, B8, B9, C8, C9, D8, D9, E4, G13, " &
" H13, J4, J13, K13, L13, N8, N9, P4, P8, P9, " &
" R8, R9, T8, T9, G7, G8, G9, G10, H7, H8, " &
" H9, H10, J7, J8, J9, J10, K7, K8, K9, K10 )," &
"VDDQ:(A15, A16, C10, C11, C12, C13, D10, D11, D12, D13," &
" E13, F4, F13, G4, G14, H4, H14, J14, K14, L14," &
" N10, N11, N12, N13, P10, P11, P12, P13 )";
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_CLOCK of TCK : signal is (1.0e7, LOW);
attribute TAP_SCAN_RESET of TRSTL : signal is true;
attribute INSTRUCTION_LENGTH of IDT72T2098Z : entity is 4;
attribute INSTRUCTION_OPCODE of IDT72T2098Z : entity is
"SAMPLE (0001)," &
"IDCODE (0010)," &
"HIGHZ (0011)," &
"BYPASS (1111)";
attribute INSTRUCTION_CAPTURE of IDT72T2098Z : entity is "1101";
attribute IDCODE_REGISTER of IDT72T2098Z : entity is
"0000" & -- version
"0000010010101000" & -- part number 04A8
"00000110011" & -- manufacturer's identity
"1"; -- required by 1149.1
attribute REGISTER_ACCESS of IDT72T2098Z : entity is
"Bypass (BYPASS, HIGHZ)," &
"Boundary (SAMPLE)," &
"Device_ID (IDCODE)";
attribute BOUNDARY_LENGTH of IDT72T2098Z: entity is 70;
attribute BOUNDARY_REGISTER of IDT72T2098Z: entity is
--
-- num cell port function safe [ccell disval rslt]
--
"0 (BC_0, PAFL, output2, X),"&
"1 (BC_0, FF_IR, output2, X),"&
"2 (BC_0, FWFT, input, X),"&
"3 (BC_0, WCLK, input, X),"&
"4 (BC_0, WENL, input, X),"&
"5 (BC_0, WCSL, input, X),"&
"6 (BC_0, FSEL0, input, X),"&
"7 (BC_0, FSEL1, input, X),"&
"8 (BC_0, MRSL, input, X),"&
"9 (BC_0, PRSL, input, X),"&
"10 (BC_0, IW, input, X),"&
"11 (BC_0, OW, input, X),"&
"12 (BC_0, RSDRL, input, X),"&
"13 (BC_0, WSDRL, input, X),"&
"14 (BC_0, D19, input, X),"&
"15 (BC_0, D18, input, X),"&
"16 (BC_0, D17, input, X),"&
"17 (BC_0, D16, input, X),"&
"18 (BC_0, D15, input, X),"&
"19 (BC_0, D14, input, X),"&
"20 (BC_0, D13, input, X),"&
"21 (BC_0, D12, input, X),"&
"22 (BC_0, D11, input, X),"&
"23 (BC_0, D10, input, X),"&
"24 (BC_0, Q19, output2, X),"&
"25 (BC_0, Q18, output2, X),"&
"26 (BC_0, Q17, output2, X),"&
"27 (BC_0, Q16, output2, X),"&
"28 (BC_0, Q15, output2, X),"&
"29 (BC_0, Q14, output2, X),"&
"30 (BC_0, Q13, output2, X),"&
"31 (BC_0, Q12, output2, X),"&
"32 (BC_0, Q11, output2, X),"&
"33 (BC_0, Q10, output2, X),"&
"34 (BC_0, ERCLK, output2, X),"&
"35 (BC_0, ERENL, output2, X),"&
"36 (BC_0, EF_OR, output2, X),"&
"37 (BC_0, PAEL, output2, X),"&
"38 (BC_0, SO, output2, X),"&
"39 (BC_0, SENOL, input, X),"&
"40 (BC_0, SENL, input, X),"&
"41 (BC_0, SCLK, input, X),"&
"42 (BC_0, SI, input, X),"&
"43 (BC_0, RCLK, input, X),"&
"44 (BC_0, RENL, input, X),"&
"45 (BC_0, RCSL, input, X),"&
"46 (BC_0, OEL, input, X),"&
"47 (BC_0, RTL, input, X),"&
"48 (BC_0, MARK, input, X),"&
"49 (BC_0, Q9, output2, X),"&
"50 (BC_0, Q8, output2, X),"&
"51 (BC_0, Q7, output2, X),"&
"52 (BC_0, Q6, output2, X),"&
"53 (BC_0, Q5, output2, X),"&
"54 (BC_0, Q4, output2, X),"&
"55 (BC_0, Q3, output2, X),"&
"56 (BC_0, Q2, output2, X),"&
"57 (BC_0, Q1, output2, X),"&
"58 (BC_0, Q0, output2, X),"&
"59 (BC_0, HSTL, input, X),"&
"60 (BC_0, D9, input, X),"&
"61 (BC_0, D8, input, X),"&
"62 (BC_0, D7, input, X),"&
"63 (BC_0, D6, input, X),"&
"64 (BC_0, D5, input, X),"&
"65 (BC_0, D4, input, X),"&
"66 (BC_0, D3, input, X),"&
"67 (BC_0, D2, input, X),"&
"68 (BC_0, D1, input, X),"&
"69 (BC_0, D0, input, X)";
end IDT72T2098Z;
