This BSDL contains syntax errors!
Raza Microelectronics, Inc.
BSDL for the RMI Alchemy� Au1500� Processor
***************************************************************************************************************
-----------------------------------------------------------------------------
-- AU1500.bsdl - IEEE 1149.1 Boundary Scan Description --
-- --
-- DISCLAIMER: This information is for modeling purposes only, and is --
-- not guaranteed. This information may contain technical inaccuracies --
-- or typographical errors. Raza Microelectronics reserves the right --
-- to withdraw this information at any time without notice. --
-- Copyright 2002 Raza Microelectronics, All rights reserved --
-- --
-- ELECTRONICALLY VERIFIED --
-- Rev. 1.0 08/21/2002 --
-- Rev. 1.1 12/04/2002 --
-- Rev. 1.2 04/27/2004 --
-- Rev. 1.2 04/27/2004 --
-- 1. Changed SDCLK vector to out instead of inout--documentation lists --
-- these pins as output-only --
-- Rev. 1.1 12/04/2002 --
-- 1. Removed the attribute PORT_GROUPING for USB pins, it is not needed. --
-- Each pins has its own boundary cell: --
-- attribute PORT_GROUPING of AU1000 : entity is --
-- "Differential_Voltage ( (USBHP, USBHM), (USBDP, USBDM) )"; --
-----------------------------------------------------------------------------
entity AU1500 is
--- Generic Parameter (ref B.8.2) ---
generic (PHYSICAL_PIN_MAP: string:= "BGA_23x23");
--- Logical Port Description (ref B.8.3) ---
port(
SDA : buffer bit_vector (0 to 12);
SDBA : buffer bit_vector (0 to 1);
SDD : inout bit_vector (0 to 31);
SDQM_N : buffer bit_vector (0 to 3);
SDRAS_N : buffer bit;
SDCAS_N : buffer bit;
SDWE_N : buffer bit;
SDCLK : out bit_vector (0 to 2);
SDCS_N : buffer bit_vector (0 to 2);
SDCKE : buffer bit;
RAD : inout bit_vector (0 to 31);
RD : inout bit_vector (0 to 31);
RBEN_N : inout bit_vector (0 to 3);
RWE_N : inout bit;
ROE_N : inout bit;
RCE_N : inout bit_vector (0 to 3);
EWAIT_N : in bit;
PREG_N : inout bit;
PCE_N : inout bit_vector (1 to 2);
POE_N : inout bit;
PWE_N : inout bit;
PIOR_N : inout bit;
PIOW_N : inout bit;
PWAIT_N : in bit;
PIOS16_N : in bit;
LCLK : buffer bit;
LWAIT_N : in bit;
LRD_N : inout bit_vector (0 to 1);
LWR_N : inout bit_vector (0 to 1);
AD : inout bit_vector (0 to 31);
CBE_N : inout bit_vector (0 to 3);
FRAME_N : inout bit;
IRDY_N : inout bit;
TRDY_N : inout bit;
STOP_N : inout bit;
PERR_N : inout bit;
SERR_N : inout bit;
PCIPAR : inout bit;
IDSEL : in bit;
PCILOCK_N : in bit;
PCICLKO : buffer bit;
PCIREQ_N : in bit_vector (0 to 3);
PCIGNT_N : inout bit_vector (0 to 3);
DEVSEL_N : inout bit;
INTA : in bit;
INTB : in bit;
INTC : in bit;
INTD : in bit;
PCICLK : in bit;
PCIRST : in bit;
UHCM : inout bit;
UHCP : inout bit;
UDCM : inout bit;
UDCP : inout bit;
U0TXD : inout bit;
U0RXD : in bit;
U3TXD : inout bit;
U3RXD : in bit;
N0TXCLK : in bit;
N0TXEN : inout bit;
N0TXD : inout bit_vector (0 to 3);
N0RXCLK : in bit;
N0RXDV : in bit;
N0RXD : in bit_vector (0 to 3);
N0CRS : in bit;
N0COL : in bit;
N0MDC : inout bit;
N0MDIO : inout bit;
N1TXCLK : in bit;
N1TXEN : inout bit;
N1TXD : inout bit_vector (0 to 3);
N1RXCLK : in bit;
N1RXDV : in bit;
N1RXD : in bit_vector (0 to 3);
N1CRS : in bit;
N1COL : in bit;
N1MDC : inout bit;
N1MDIO : inout bit;
ACSYNC : inout bit;
ACBCLK : in bit;
ACDO : inout bit;
ACDI : in bit;
ACRST : inout bit;
TRST_N : in bit;
TDI : in bit;
TDO : out bit;
TMS : in bit;
TCK : in bit;
TC : in bit_vector (0 to 3);
TSTEN : in bit;
GPIO : inout bit_vector (0 to 15);
GPIO2 : inout bit_vector (0 to 15);
XTI32 : linkage bit;
XTO32 : linkage bit;
XTI12 : linkage bit;
XTO12 : linkage bit;
RST_N : in bit;
RSTO_N : buffer bit;
ROMSEL : in bit;
ROMSIZ : in bit;
PCICFG : in bit;
PWR_EN : linkage bit;
VDDXOK : in bit;
VDDI : linkage bit_vector (0 to 13);
VDDX : linkage bit_vector (0 to 39);
VSS : linkage bit_vector (0 to 55);
XPWR32 : linkage bit;
XAGND32 : linkage bit;
XPWR12 : linkage bit;
XAGND12 : linkage bit
);
--- Standard Use Statement (ref B.8.4) ---
use STD_1149_1_1994.all;
--- Component Conformance Statement (ref B.8.6) ---
attribute COMPONENT_CONFORMANCE of AU1500: entity is "STD_1149_1_1993";
--- Device Package Pin Mappings (ref B.8.7) ---
attribute PIN_MAP of AU1500 : entity is PHYSICAL_PIN_MAP;
constant BGA_23x23 : PIN_MAP_STRING :=
"SDA: (G4, H3, F1, E1, E2, G3, F5, D1, C1, F3, " &
"F4, E3, E4), " &
"SDBA: (H2, G1), " &
"SDD: (V4, V5, W2, W1, V2, U3, V1, T4, R4, T3, " &
"U1, R3, P6, T1, R2, P4, P3, N6, R1, P2, " &
"P1, N4, N3, N2, N1, L6, M3, L4, M1, M2, " &
"L3, K6), " &
"SDQM_N: (J3, J4, H4, H1), " &
"SDRAS_N: K2, " &
"SDCAS_N: J2, " &
"SDWE_N: K1, " &
"SDCLK: (M4, K4, K3), " &
"SDCS_N: (L1, L2, J6), " &
"SDCKE: J1, " &
"RAD: (C20, A21, C21, C22, B23, A22, D20, D19, A23, E20, " &
"E19, E21, F19, C23, F20, D21, F21, D22, D23, G20, " &
"G21, E22, E23, F23, H21, H20, G23, H23, H22, J21, " &
"J20, J23), " &
"RD: (F13, B12, A13, B13, C13, D13, A14, B14, A15, F14, " &
"D14, C14, B15, F15, B16, C15, D15, A16, A17, A18, " &
"D16, C16, D17, A19, A20, B19, C17, C18, C19, E18, " &
"B20, D18), " &
"RBEN_N: (J22, K22, J18, K21), " &
"RWE_N: K20, " &
"ROE_N: K23, " &
"RCE_N: (L23, L21, K18, L22), " &
"EWAIT_N: A12, " &
"PREG_N: A10, " &
"PCE_N: (B10, A11), " &
"POE_N: B9, " &
"PWE_N: C10, " &
"PIOR_N: A9, " &
"PIOW_N: C9, " &
"PWAIT_N: F10, " &
"PIOS16_N: F9, " &
"LCLK: D12, " &
"LWAIT_N: B11, " &
"LRD_N: (C11, D11), " &
"LWR_N: (F11, C12), " &
"AD: (V23, W23, W22, T21, T20, W21, V21, Y23, U21, Y22, " &
"U20, V19, AA23, Y21, AB23, V20, W18, W19, AC23, AC22, " &
"AA20, Y18, AA19, AB21, AC21, Y17, AA18, AB20, AC20, AB19, " &
"AC19, AA17), " &
"CBE_N: (AC17, AA16, AC16, AA15), " &
"FRAME_N: M20, " &
"IRDY_N: M21, " &
"TRDY_N: P23, " &
"STOP_N: L18, " &
"PERR_N: U23, " &
"SERR_N: R20, " &
"PCIPAR: P18, " &
"IDSEL: AC18, " &
"PCILOCK_N: P22, " &
"PCICLKO: N20, " &
"PCIREQ_N: (N18, R23, R22, R18), " &
"PCIGNT_N: (P21, P20, T23, T22), " &
"DEVSEL_N: N22, " &
"INTA: Y16, " &
"INTB: V15, " &
"INTC: Y15, " &
"INTD: AB16, " &
"PCICLK: N21, " &
"PCIRST: AB15, " &
"UHCM: W20, " &
"UHCP: AA21, " &
"UDCM: Y20, " &
"UDCP: Y19, " &
"U0TXD: M23, " &
"U0RXD: L20, " &
"U3TXD: M22, " &
"U3RXD: N23, " &
"N0TXCLK: AC14, " &
"N0TXEN: AA12, " &
"N0TXD: (AC11, AA11, AC10, Y11), " &
"N0RXCLK: Y13, " &
"N0RXDV: Y12, " &
"N0RXD: (AC13, AB13, V14, V13), " &
"N0CRS: AB14, " &
"N0COL: V11, " &
"N0MDC: AC9, " &
"N0MDIO: Y10, " &
"N1TXCLK: AB11, " &
"N1TXEN: AB9, " &
"N1TXD: (Y9, AA9, V9, Y8), " &
"N1RXCLK: AC7, " &
"N1RXDV: AC6, " &
"N1RXD: (AB10, AA10, AC8, AB8), " &
"N1CRS: V10, " &
"N1COL: AB5, " &
"N1MDC: AC5, " &
"N1MDIO: AC4, " &
"ACSYNC: AA1, " &
"ACBCLK: AA2, " &
"ACDO: Y2, " &
"ACDI: AB1, " &
"ACRST: W3, " &
"TRST_N: D4, " &
"TDI: AA5, " &
"TDO: AB4, " &
"TMS: C3, " &
"TCK: AA8, " &
"TC: (C6, C7, C8, D8), " &
"TSTEN: B1, " &
"GPIO: (E6, D6, A7, D7, A8, B8, D9, D10, AA3, AC2, " &
"AC1, Y3, Y5, Y1, V3, U4), " &
"GPIO2: (AC15, AA14, Y14, AA13, AC12, AB12, AA7, AA6, W6, AA4, " &
"Y7, W5, Y6, AC3, W4, Y4), " &
"XTI32: A3, " &
"XTO32: A2, " &
"XTI12: A5, " &
"XTO12: A4, " &
"RST_N: A6, " &
"RSTO_N: D3, " &
"ROMSEL: C5, " &
"ROMSIZ: D5, " &
"PCICFG: R21, " &
"PWR_EN: E5, " &
"VDDXOK: C4, " &
"VDDI: (L8, M8, N8, H11, T11, H12, T12, H13, T13, T14, " &
"K16, L16, M16, N16), " &
"VDDX: (D2, G2, U2, AB3, B6, G6, H6, R6, T6, U6, " &
"F7, V7, F8, K8, P8, V8, J9, R9, H10, T10, " &
"H14, J15, P15, R15, F16, P16, V16, B17, F17, V17, " &
"G18, H18, T18, U18, AB18, B21, F22, U22, AA22, AB7), " &
"VSS: (C2, F2, T2, AB2, AB6, B7, K9, L9, M9, N9, " &
"P9, J10, K10, L10, M10, N10, P10, R10, J11, K11, " &
"L11, M11, N11, P11, R11, J12, K12, L12, M12, N12, " &
"P12, R12, J13, K13, L13, M13, N13, P13, R13, J14, " &
"K14, L14, M14, N14, P14, R14, K15, L15, M15, N15, " &
"AB17, B18, B22, G22, V22, AB22), " &
"XPWR32: B2, " &
"XAGND32: B3, " &
"XPWR12: B4, " &
"XAGND12: B5";
--- Scan Port Identification (ref B.8.9) ---
attribute TAP_SCAN_CLOCK of TCK : signal is (24.0e6, LOW); -- NOTE: 40MHz is absolute max.
-- TCK frequency must always be less than 1/4 system bus frequency.
-- 24MHz satisfies default boot frequency.
attribute TAP_SCAN_IN of TDI : signal is TRUE;
attribute TAP_SCAN_OUT of TDO : signal is TRUE;
attribute TAP_SCAN_MODE of TMS : signal is TRUE;
attribute TAP_SCAN_RESET of TRST_N : signal is TRUE;
--- Instruction Register Description (ref B.8.11) ---
attribute INSTRUCTION_LENGTH of AU1500 : entity is 5;
attribute INSTRUCTION_OPCODE of AU1500 : entity is
"EXTEST (00000)," &
"IDCODE (00001)," &
"SAMPLE (00010)," &
"HIZ (00101)," &
"CLAMP (00110)," &
"BYPASS (11111)";
attribute INSTRUCTION_CAPTURE of AU1500 : entity is "X0X01";
--- Optional Register Description (ref B.8.12) ---
attribute IDCODE_REGISTER of AU1500 : entity is
"000X" & -- Version
"0000000100000010" & -- Part Number
"00101000111" & -- Manufacturer
"1"; -- Required by IEEE Std 1149.1-1990
--- Register Access Description (ref B.8.13) ---
attribute REGISTER_ACCESS of AU1500 : entity is
"BOUNDARY (EXTEST, SAMPLE), " &
"BYPASS (BYPASS, HIZ, CLAMP)";
--- Boundary-Scan Register Description (ref B.8.14) ---
attribute BOUNDARY_LENGTH of AU1500 : entity is 744;
attribute BOUNDARY_REGISTER of AU1500 : entity is
"743 (BC_4, GPIO2(8), INPUT, x), " &
"742 (BC_2, *, control, 0), " &
"741 (BC_1, GPIO2(8), OUTPUT3, x, 742, 0, Z), " &
"740 (BC_4, GPIO2(9), INPUT, x), " &
"739 (BC_2, *, control, 0), " &
"738 (BC_1, GPIO2(9), OUTPUT3, x, 739, 0, Z), " &
"737 (BC_4, GPIO2(10), INPUT, x), " &
"736 (BC_2, *, control, 0), " &
"735 (BC_1, GPIO2(10), OUTPUT3, x, 736, 0, Z), " &
"734 (BC_4, GPIO2(11), INPUT, x), " &
"733 (BC_2, *, control, 0), " &
"732 (BC_1, GPIO2(11), OUTPUT3, x, 733, 0, Z), " &
"731 (BC_4, GPIO2(12), INPUT, x), " &
"730 (BC_2, *, control, 0), " &
"729 (BC_1, GPIO2(12), OUTPUT3, x, 730, 0, Z), " &
"728 (BC_4, GPIO2(13), INPUT, x), " &
"727 (BC_2, *, control, 0), " &
"726 (BC_1, GPIO2(13), OUTPUT3, x, 727, 0, Z), " &
"725 (BC_4, GPIO2(14), INPUT, x), " &
"724 (BC_2, *, control, 0), " &
"723 (BC_1, GPIO2(14), OUTPUT3, x, 724, 0, Z), " &
"722 (BC_4, GPIO2(15), INPUT, x), " &
"721 (BC_2, *, control, 0), " &
"720 (BC_1, GPIO2(15), OUTPUT3, x, 721, 0, Z), " &
"719 (BC_4, GPIO(8), INPUT, x), " &
"718 (BC_2, *, control, 0), " &
"717 (BC_1, GPIO(8), OUTPUT3, x, 718, 0, Z), " &
"716 (BC_4, GPIO(9), INPUT, x), " &
"715 (BC_2, *, control, 0), " &
"714 (BC_1, GPIO(9), OUTPUT3, x, 715, 0, Z), " &
"713 (BC_4, GPIO(10), INPUT, x), " &
"712 (BC_2, *, control, 0), " &
"711 (BC_1, GPIO(10), OUTPUT3, x, 712, 0, Z), " &
"710 (BC_4, GPIO(11), INPUT, x), " &
"709 (BC_2, *, control, 0), " &
"708 (BC_1, GPIO(11), OUTPUT3, x, 709, 0, Z), " &
"707 (BC_4, GPIO(12), INPUT, x), " &
"706 (BC_2, *, control, 0), " &
"705 (BC_1, GPIO(12), OUTPUT3, x, 706, 0, Z), " &
"704 (BC_4, ACDI, INPUT, x), " &
"703 (BC_4, ACRST, INPUT, x), " &
"702 (BC_2, *, control, 0), " &
"701 (BC_1, ACRST, OUTPUT3, x, 702, 0, Z), " &
"700 (BC_4, ACBCLK, INPUT, x), " &
"699 (BC_4, ACSYNC, INPUT, x), " &
"698 (BC_2, *, control, 0), " &
"697 (BC_1, ACSYNC, OUTPUT3, x, 698, 0, Z), " &
"696 (BC_4, ACDO, INPUT, x), " &
"695 (BC_2, *, control, 0), " &
"694 (BC_1, ACDO, OUTPUT3, x, 695, 0, Z), " &
"693 (BC_4, GPIO(13), INPUT, x), " &
"692 (BC_2, *, control, 0), " &
"691 (BC_1, GPIO(13), OUTPUT3, x, 692, 0, Z), " &
"690 (BC_4, GPIO(14), INPUT, x), " &
"689 (BC_2, *, control, 0), " &
"688 (BC_1, GPIO(14), OUTPUT3, x, 689, 0, Z), " &
"687 (BC_4, GPIO(15), INPUT, x), " &
"686 (BC_2, *, control, 0), " &
"685 (BC_1, GPIO(15), OUTPUT3, x, 686, 0, Z), " &
"684 (BC_4, SDD(0), INPUT, x), " &
"683 (BC_2, *, control, 0), " &
"682 (BC_1, SDD(0), OUTPUT3, x, 683, 0, Z), " &
"681 (BC_4, SDD(1), INPUT, x), " &
"680 (BC_2, *, control, 0), " &
"679 (BC_1, SDD(1), OUTPUT3, x, 680, 0, Z), " &
"678 (BC_4, SDD(2), INPUT, x), " &
"677 (BC_2, *, control, 0), " &
"676 (BC_1, SDD(2), OUTPUT3, x, 677, 0, Z), " &
"675 (BC_4, SDD(3), INPUT, x), " &
"674 (BC_2, *, control, 0), " &
"673 (BC_1, SDD(3), OUTPUT3, x, 674, 0, Z), " &
"672 (BC_4, SDD(4), INPUT, x), " &
"671 (BC_2, *, control, 0), " &
"670 (BC_1, SDD(4), OUTPUT3, x, 671, 0, Z), " &
"669 (BC_4, SDD(5), INPUT, x), " &
"668 (BC_2, *, control, 0), " &
"667 (BC_1, SDD(5), OUTPUT3, x, 668, 0, Z), " &
"666 (BC_4, SDD(6), INPUT, x), " &
"665 (BC_2, *, control, 0), " &
"664 (BC_1, SDD(6), OUTPUT3, x, 665, 0, Z), " &
"663 (BC_4, SDD(7), INPUT, x), " &
"662 (BC_2, *, control, 0), " &
"661 (BC_1, SDD(7), OUTPUT3, x, 662, 0, Z), " &
"660 (BC_4, SDD(8), INPUT, x), " &
"659 (BC_2, *, control, 0), " &
"658 (BC_1, SDD(8), OUTPUT3, x, 659, 0, Z), " &
"657 (BC_4, SDD(9), INPUT, x), " &
"656 (BC_2, *, control, 0), " &
"655 (BC_1, SDD(9), OUTPUT3, x, 656, 0, Z), " &
"654 (BC_4, SDD(10), INPUT, x), " &
"653 (BC_2, *, control, 0), " &
"652 (BC_1, SDD(10), OUTPUT3, x, 653, 0, Z), " &
"651 (BC_4, SDD(11), INPUT, x), " &
"650 (BC_2, *, control, 0), " &
"649 (BC_1, SDD(11), OUTPUT3, x, 650, 0, Z), " &
"648 (BC_4, SDD(12), INPUT, x), " &
"647 (BC_2, *, control, 0), " &
"646 (BC_1, SDD(12), OUTPUT3, x, 647, 0, Z), " &
"645 (BC_4, SDD(13), INPUT, x), " &
"644 (BC_2, *, control, 0), " &
"643 (BC_1, SDD(13), OUTPUT3, x, 644, 0, Z), " &
"642 (BC_4, SDD(14), INPUT, x), " &
"641 (BC_2, *, control, 0), " &
"640 (BC_1, SDD(14), OUTPUT3, x, 641, 0, Z), " &
"639 (BC_4, SDD(15), INPUT, x), " &
"638 (BC_2, *, control, 0), " &
"637 (BC_1, SDD(15), OUTPUT3, x, 638, 0, Z), " &
"636 (BC_4, SDD(16), INPUT, x), " &
"635 (BC_2, *, control, 0), " &
"634 (BC_1, SDD(16), OUTPUT3, x, 635, 0, Z), " &
"633 (BC_4, SDD(17), INPUT, x), " &
"632 (BC_2, *, control, 0), " &
"631 (BC_1, SDD(17), OUTPUT3, x, 632, 0, Z), " &
"630 (BC_4, SDD(18), INPUT, x), " &
"629 (BC_2, *, control, 0), " &
"628 (BC_1, SDD(18), OUTPUT3, x, 629, 0, Z), " &
"627 (BC_4, SDD(19), INPUT, x), " &
"626 (BC_2, *, control, 0), " &
"625 (BC_1, SDD(19), OUTPUT3, x, 626, 0, Z), " &
"624 (BC_4, SDD(20), INPUT, x), " &
"623 (BC_2, *, control, 0), " &
"622 (BC_1, SDD(20), OUTPUT3, x, 623, 0, Z), " &
"621 (BC_4, SDD(21), INPUT, x), " &
"620 (BC_2, *, control, 0), " &
"619 (BC_1, SDD(21), OUTPUT3, x, 620, 0, Z), " &
"618 (BC_4, SDD(22), INPUT, x), " &
"617 (BC_2, *, control, 0), " &
"616 (BC_1, SDD(22), OUTPUT3, x, 617, 0, Z), " &
"615 (BC_4, SDD(23), INPUT, x), " &
"614 (BC_2, *, control, 0), " &
"613 (BC_1, SDD(23), OUTPUT3, x, 614, 0, Z), " &
"612 (BC_4, SDD(24), INPUT, x), " &
"611 (BC_2, *, control, 0), " &
"610 (BC_1, SDD(24), OUTPUT3, x, 611, 0, Z), " &
"609 (BC_1, *, internal, x), " &
"608 (BC_2, *, control, 0), " &
"607 (BC_1, SDCLK(0), OUTPUT3, x, 608, 0, Z), " &
"606 (BC_4, SDD(25), INPUT, x), " &
"605 (BC_2, *, control, 0), " &
"604 (BC_1, SDD(25), OUTPUT3, x, 605, 0, Z), " &
"603 (BC_4, SDD(26), INPUT, x), " &
"602 (BC_2, *, control, 0), " &
"601 (BC_1, SDD(26), OUTPUT3, x, 602, 0, Z), " &
"600 (BC_4, SDD(27), INPUT, x), " &
"599 (BC_2, *, control, 0), " &
"598 (BC_1, SDD(27), OUTPUT3, x, 599, 0, Z), " &
"597 (BC_4, SDD(28), INPUT, x), " &
"596 (BC_2, *, control, 0), " &
"595 (BC_1, SDD(28), OUTPUT3, x, 596, 0, Z), " &
"594 (BC_4, SDD(29), INPUT, x), " &
"593 (BC_2, *, control, 0), " &
"592 (BC_1, SDD(29), OUTPUT3, x, 593, 0, Z), " &
"591 (BC_4, SDD(30), INPUT, x), " &
"590 (BC_2, *, control, 0), " &
"589 (BC_1, SDD(30), OUTPUT3, x, 590, 0, Z), " &
"588 (BC_4, SDD(31), INPUT, x), " &
"587 (BC_2, *, control, 0), " &
"586 (BC_1, SDD(31), OUTPUT3, x, 587, 0, Z), " &
"585 (BC_1, SDCS_N(0), OUTPUT2, x), " &
"584 (BC_1, SDCS_N(1), OUTPUT2, x), " &
"583 (BC_1, *, internal, x), " &
"582 (BC_2, *, control, 0), " &
"581 (BC_1, SDCLK(1), OUTPUT3, x, 582, 0, Z), " &
"580 (BC_1, *, internal, x), " &
"579 (BC_2, *, control, 0), " &
"578 (BC_1, SDCLK(2), OUTPUT3, x, 579, 0, Z), " &
"577 (BC_1, SDCS_N(2), OUTPUT2, x), " &
"576 (BC_1, SDWE_N, OUTPUT2, x), " &
"575 (BC_1, SDRAS_N, OUTPUT2, x), " &
"574 (BC_1, SDCKE, OUTPUT2, x), " &
"573 (BC_1, SDCAS_N, OUTPUT2, x), " &
"572 (BC_1, SDQM_N(0), OUTPUT2, x), " &
"571 (BC_1, SDQM_N(1), OUTPUT2, x), " &
"570 (BC_1, SDQM_N(2), OUTPUT2, x), " &
"569 (BC_1, SDQM_N(3), OUTPUT2, x), " &
"568 (BC_1, SDBA(0), OUTPUT2, x), " &
"567 (BC_1, SDBA(1), OUTPUT2, x), " &
"566 (BC_1, SDA(0), OUTPUT2, x), " &
"565 (BC_1, SDA(1), OUTPUT2, x), " &
"564 (BC_1, SDA(2), OUTPUT2, x), " &
"563 (BC_1, SDA(3), OUTPUT2, x), " &
"562 (BC_1, SDA(4), OUTPUT2, x), " &
"561 (BC_1, SDA(5), OUTPUT2, x), " &
"560 (BC_1, SDA(6), OUTPUT2, x), " &
"559 (BC_1, SDA(7), OUTPUT2, x), " &
"558 (BC_1, SDA(8), OUTPUT2, x), " &
"557 (BC_1, SDA(9), OUTPUT2, x), " &
"556 (BC_1, SDA(10), OUTPUT2, x), " &
"555 (BC_1, SDA(11), OUTPUT2, x), " &
"554 (BC_1, SDA(12), OUTPUT2, x), " &
"553 (BC_1, RSTO_N, OUTPUT2, x), " &
"552 (BC_4, VDDXOK, INPUT, x), " &
"551 (BC_4, TSTEN, INPUT, x), " &
"550 (BC_4, ROMSEL, INPUT, x), " &
"549 (BC_4, ROMSIZ, INPUT, x), " &
"548 (BC_4, RST_N, INPUT, x), " &
"547 (BC_4, GPIO(0), INPUT, x), " &
"546 (BC_2, *, control, 0), " &
"545 (BC_1, GPIO(0), OUTPUT3, x, 546, 0, Z), " &
"544 (BC_4, GPIO(1), INPUT, x), " &
"543 (BC_2, *, control, 0), " &
"542 (BC_1, GPIO(1), OUTPUT3, x, 543, 0, Z), " &
"541 (BC_4, TC(0), INPUT, x), " &
"540 (BC_4, GPIO(2), INPUT, x), " &
"539 (BC_2, *, control, 0), " &
"538 (BC_1, GPIO(2), OUTPUT3, x, 539, 0, Z), " &
"537 (BC_4, GPIO(3), INPUT, x), " &
"536 (BC_2, *, control, 0), " &
"535 (BC_1, GPIO(3), OUTPUT3, x, 536, 0, Z), " &
"534 (BC_4, TC(1), INPUT, x), " &
"533 (BC_4, TC(2), INPUT, x), " &
"532 (BC_4, GPIO(4), INPUT, x), " &
"531 (BC_2, *, control, 0), " &
"530 (BC_1, GPIO(4), OUTPUT3, x, 531, 0, Z), " &
"529 (BC_4, GPIO(5), INPUT, x), " &
"528 (BC_2, *, control, 0), " &
"527 (BC_1, GPIO(5), OUTPUT3, x, 528, 0, Z), " &
"526 (BC_4, TC(3), INPUT, x), " &
"525 (BC_4, PIOS16_N, INPUT, x), " &
"524 (BC_4, PIOW_N, INPUT, x), " &
"523 (BC_2, *, control, 0), " &
"522 (BC_1, PIOW_N, OUTPUT3, x, 523, 0, Z), " &
"521 (BC_4, PIOR_N, INPUT, x), " &
"520 (BC_2, *, control, 0), " &
"519 (BC_1, PIOR_N, OUTPUT3, x, 520, 0, Z), " &
"518 (BC_4, GPIO(6), INPUT, x), " &
"517 (BC_2, *, control, 0), " &
"516 (BC_1, GPIO(6), OUTPUT3, x, 517, 0, Z), " &
"515 (BC_4, GPIO(7), INPUT, x), " &
"514 (BC_2, *, control, 0), " &
"513 (BC_1, GPIO(7), OUTPUT3, x, 514, 0, Z), " &
"512 (BC_4, PWE_N, INPUT, x), " &
"511 (BC_2, *, control, 0), " &
"510 (BC_1, PWE_N, OUTPUT3, x, 511, 0, Z), " &
"509 (BC_4, POE_N, INPUT, x), " &
"508 (BC_2, *, control, 0), " &
"507 (BC_1, POE_N, OUTPUT3, x, 508, 0, Z), " &
"506 (BC_4, PREG_N, INPUT, x), " &
"505 (BC_2, *, control, 0), " &
"504 (BC_1, PREG_N, OUTPUT3, x, 505, 0, Z), " &
"503 (BC_4, PWAIT_N, INPUT, x), " &
"502 (BC_4, PCE_N(1), INPUT, x), " &
"501 (BC_2, *, control, 0), " &
"500 (BC_1, PCE_N(1), OUTPUT3, x, 501, 0, Z), " &
"499 (BC_4, PCE_N(2), INPUT, x), " &
"498 (BC_2, *, control, 0), " &
"497 (BC_1, PCE_N(2), OUTPUT3, x, 498, 0, Z), " &
"496 (BC_4, LRD_N(0), INPUT, x), " &
"495 (BC_2, *, control, 0), " &
"494 (BC_1, LRD_N(0), OUTPUT3, x, 495, 0, Z), " &
"493 (BC_4, LRD_N(1), INPUT, x), " &
"492 (BC_2, *, control, 0), " &
"491 (BC_1, LRD_N(1), OUTPUT3, x, 492, 0, Z), " &
"490 (BC_4, LWR_N(0), INPUT, x), " &
"489 (BC_2, *, control, 0), " &
"488 (BC_1, LWR_N(0), OUTPUT3, x, 489, 0, Z), " &
"487 (BC_4, LWAIT_N, INPUT, x), " &
"486 (BC_4, EWAIT_N, INPUT, x), " &
"485 (BC_1, LCLK, OUTPUT2, x), " &
"484 (BC_4, LWR_N(1), INPUT, x), " &
"483 (BC_2, *, control, 0), " &
"482 (BC_1, LWR_N(1), OUTPUT3, x, 483, 0, Z), " &
"481 (BC_4, RD(0), INPUT, x), " &
"480 (BC_2, *, control, 0), " &
"479 (BC_1, RD(0), OUTPUT3, x, 480, 0, Z), " &
"478 (BC_4, RD(1), INPUT, x), " &
"477 (BC_2, *, control, 0), " &
"476 (BC_1, RD(1), OUTPUT3, x, 477, 0, Z), " &
"475 (BC_4, RD(2), INPUT, x), " &
"474 (BC_2, *, control, 0), " &
"473 (BC_1, RD(2), OUTPUT3, x, 474, 0, Z), " &
"472 (BC_4, RD(3), INPUT, x), " &
"471 (BC_2, *, control, 0), " &
"470 (BC_1, RD(3), OUTPUT3, x, 471, 0, Z), " &
"469 (BC_4, RD(4), INPUT, x), " &
"468 (BC_2, *, control, 0), " &
"467 (BC_1, RD(4), OUTPUT3, x, 468, 0, Z), " &
"466 (BC_4, RD(5), INPUT, x), " &
"465 (BC_2, *, control, 0), " &
"464 (BC_1, RD(5), OUTPUT3, x, 465, 0, Z), " &
"463 (BC_4, RD(6), INPUT, x), " &
"462 (BC_2, *, control, 0), " &
"461 (BC_1, RD(6), OUTPUT3, x, 462, 0, Z), " &
"460 (BC_4, RD(7), INPUT, x), " &
"459 (BC_2, *, control, 0), " &
"458 (BC_1, RD(7), OUTPUT3, x, 459, 0, Z), " &
"457 (BC_4, RD(8), INPUT, x), " &
"456 (BC_2, *, control, 0), " &
"455 (BC_1, RD(8), OUTPUT3, x, 456, 0, Z), " &
"454 (BC_4, RD(9), INPUT, x), " &
"453 (BC_2, *, control, 0), " &
"452 (BC_1, RD(9), OUTPUT3, x, 453, 0, Z), " &
"451 (BC_4, RD(10), INPUT, x), " &
"450 (BC_2, *, control, 0), " &
"449 (BC_1, RD(10), OUTPUT3, x, 450, 0, Z), " &
"448 (BC_4, RD(11), INPUT, x), " &
"447 (BC_2, *, control, 0), " &
"446 (BC_1, RD(11), OUTPUT3, x, 447, 0, Z), " &
"445 (BC_4, RD(12), INPUT, x), " &
"444 (BC_2, *, control, 0), " &
"443 (BC_1, RD(12), OUTPUT3, x, 444, 0, Z), " &
"442 (BC_4, RD(13), INPUT, x), " &
"441 (BC_2, *, control, 0), " &
"440 (BC_1, RD(13), OUTPUT3, x, 441, 0, Z), " &
"439 (BC_4, RD(14), INPUT, x), " &
"438 (BC_2, *, control, 0), " &
"437 (BC_1, RD(14), OUTPUT3, x, 438, 0, Z), " &
"436 (BC_4, RD(15), INPUT, x), " &
"435 (BC_2, *, control, 0), " &
"434 (BC_1, RD(15), OUTPUT3, x, 435, 0, Z), " &
"433 (BC_4, RD(16), INPUT, x), " &
"432 (BC_2, *, control, 0), " &
"431 (BC_1, RD(16), OUTPUT3, x, 432, 0, Z), " &
"430 (BC_4, RD(17), INPUT, x), " &
"429 (BC_2, *, control, 0), " &
"428 (BC_1, RD(17), OUTPUT3, x, 429, 0, Z), " &
"427 (BC_4, RD(18), INPUT, x), " &
"426 (BC_2, *, control, 0), " &
"425 (BC_1, RD(18), OUTPUT3, x, 426, 0, Z), " &
"424 (BC_4, RD(19), INPUT, x), " &
"423 (BC_2, *, control, 0), " &
"422 (BC_1, RD(19), OUTPUT3, x, 423, 0, Z), " &
"421 (BC_4, RD(20), INPUT, x), " &
"420 (BC_2, *, control, 0), " &
"419 (BC_1, RD(20), OUTPUT3, x, 420, 0, Z), " &
"418 (BC_4, RD(21), INPUT, x), " &
"417 (BC_2, *, control, 0), " &
"416 (BC_1, RD(21), OUTPUT3, x, 417, 0, Z), " &
"415 (BC_4, RD(22), INPUT, x), " &
"414 (BC_2, *, control, 0), " &
"413 (BC_1, RD(22), OUTPUT3, x, 414, 0, Z), " &
"412 (BC_4, RD(23), INPUT, x), " &
"411 (BC_2, *, control, 0), " &
"410 (BC_1, RD(23), OUTPUT3, x, 411, 0, Z), " &
"409 (BC_4, RD(24), INPUT, x), " &
"408 (BC_2, *, control, 0), " &
"407 (BC_1, RD(24), OUTPUT3, x, 408, 0, Z), " &
"406 (BC_4, RD(25), INPUT, x), " &
"405 (BC_2, *, control, 0), " &
"404 (BC_1, RD(25), OUTPUT3, x, 405, 0, Z), " &
"403 (BC_4, RD(26), INPUT, x), " &
"402 (BC_2, *, control, 0), " &
"401 (BC_1, RD(26), OUTPUT3, x, 402, 0, Z), " &
"400 (BC_4, RD(27), INPUT, x), " &
"399 (BC_2, *, control, 0), " &
"398 (BC_1, RD(27), OUTPUT3, x, 399, 0, Z), " &
"397 (BC_4, RD(28), INPUT, x), " &
"396 (BC_2, *, control, 0), " &
"395 (BC_1, RD(28), OUTPUT3, x, 396, 0, Z), " &
"394 (BC_4, RD(29), INPUT, x), " &
"393 (BC_2, *, control, 0), " &
"392 (BC_1, RD(29), OUTPUT3, x, 393, 0, Z), " &
"391 (BC_4, RD(30), INPUT, x), " &
"390 (BC_2, *, control, 0), " &
"389 (BC_1, RD(30), OUTPUT3, x, 390, 0, Z), " &
"388 (BC_4, RD(31), INPUT, x), " &
"387 (BC_2, *, control, 0), " &
"386 (BC_1, RD(31), OUTPUT3, x, 387, 0, Z), " &
"385 (BC_4, RAD(0), INPUT, x), " &
"384 (BC_2, *, control, 0), " &
"383 (BC_1, RAD(0), OUTPUT3, x, 384, 0, Z), " &
"382 (BC_4, RAD(1), INPUT, x), " &
"381 (BC_2, *, control, 0), " &
"380 (BC_1, RAD(1), OUTPUT3, x, 381, 0, Z), " &
"379 (BC_4, RAD(2), INPUT, x), " &
"378 (BC_2, *, control, 0), " &
"377 (BC_1, RAD(2), OUTPUT3, x, 378, 0, Z), " &
"376 (BC_4, RAD(3), INPUT, x), " &
"375 (BC_2, *, control, 0), " &
"374 (BC_1, RAD(3), OUTPUT3, x, 375, 0, Z), " &
"373 (BC_4, RAD(4), INPUT, x), " &
"372 (BC_2, *, control, 0), " &
"371 (BC_1, RAD(4), OUTPUT3, x, 372, 0, Z), " &
"370 (BC_4, RAD(5), INPUT, x), " &
"369 (BC_2, *, control, 0), " &
"368 (BC_1, RAD(5), OUTPUT3, x, 369, 0, Z), " &
"367 (BC_4, RAD(6), INPUT, x), " &
"366 (BC_2, *, control, 0), " &
"365 (BC_1, RAD(6), OUTPUT3, x, 366, 0, Z), " &
"364 (BC_4, RAD(7), INPUT, x), " &
"363 (BC_2, *, control, 0), " &
"362 (BC_1, RAD(7), OUTPUT3, x, 363, 0, Z), " &
"361 (BC_4, RAD(8), INPUT, x), " &
"360 (BC_2, *, control, 0), " &
"359 (BC_1, RAD(8), OUTPUT3, x, 360, 0, Z), " &
"358 (BC_4, RAD(9), INPUT, x), " &
"357 (BC_2, *, control, 0), " &
"356 (BC_1, RAD(9), OUTPUT3, x, 357, 0, Z), " &
"355 (BC_4, RAD(10), INPUT, x), " &
"354 (BC_2, *, control, 0), " &
"353 (BC_1, RAD(10), OUTPUT3, x, 354, 0, Z), " &
"352 (BC_4, RAD(11), INPUT, x), " &
"351 (BC_2, *, control, 0), " &
"350 (BC_1, RAD(11), OUTPUT3, x, 351, 0, Z), " &
"349 (BC_4, RAD(12), INPUT, x), " &
"348 (BC_2, *, control, 0), " &
"347 (BC_1, RAD(12), OUTPUT3, x, 348, 0, Z), " &
"346 (BC_4, RAD(13), INPUT, x), " &
"345 (BC_2, *, control, 0), " &
"344 (BC_1, RAD(13), OUTPUT3, x, 345, 0, Z), " &
"343 (BC_4, RAD(14), INPUT, x), " &
"342 (BC_2, *, control, 0), " &
"341 (BC_1, RAD(14), OUTPUT3, x, 342, 0, Z), " &
"340 (BC_4, RAD(15), INPUT, x), " &
"339 (BC_2, *, control, 0), " &
"338 (BC_1, RAD(15), OUTPUT3, x, 339, 0, Z), " &
"337 (BC_4, RAD(16), INPUT, x), " &
"336 (BC_2, *, control, 0), " &
"335 (BC_1, RAD(16), OUTPUT3, x, 336, 0, Z), " &
"334 (BC_4, RAD(17), INPUT, x), " &
"333 (BC_2, *, control, 0), " &
"332 (BC_1, RAD(17), OUTPUT3, x, 333, 0, Z), " &
"331 (BC_4, RAD(18), INPUT, x), " &
"330 (BC_2, *, control, 0), " &
"329 (BC_1, RAD(18), OUTPUT3, x, 330, 0, Z), " &
"328 (BC_4, RAD(19), INPUT, x), " &
"327 (BC_2, *, control, 0), " &
"326 (BC_1, RAD(19), OUTPUT3, x, 327, 0, Z), " &
"325 (BC_4, RAD(20), INPUT, x), " &
"324 (BC_2, *, control, 0), " &
"323 (BC_1, RAD(20), OUTPUT3, x, 324, 0, Z), " &
"322 (BC_4, RAD(21), INPUT, x), " &
"321 (BC_2, *, control, 0), " &
"320 (BC_1, RAD(21), OUTPUT3, x, 321, 0, Z), " &
"319 (BC_4, RAD(22), INPUT, x), " &
"318 (BC_2, *, control, 0), " &
"317 (BC_1, RAD(22), OUTPUT3, x, 318, 0, Z), " &
"316 (BC_4, RAD(23), INPUT, x), " &
"315 (BC_2, *, control, 0), " &
"314 (BC_1, RAD(23), OUTPUT3, x, 315, 0, Z), " &
"313 (BC_4, RAD(24), INPUT, x), " &
"312 (BC_2, *, control, 0), " &
"311 (BC_1, RAD(24), OUTPUT3, x, 312, 0, Z), " &
"310 (BC_4, RAD(25), INPUT, x), " &
"309 (BC_2, *, control, 0), " &
"308 (BC_1, RAD(25), OUTPUT3, x, 309, 0, Z), " &
"307 (BC_4, RAD(26), INPUT, x), " &
"306 (BC_2, *, control, 0), " &
"305 (BC_1, RAD(26), OUTPUT3, x, 306, 0, Z), " &
"304 (BC_4, RAD(27), INPUT, x), " &
"303 (BC_2, *, control, 0), " &
"302 (BC_1, RAD(27), OUTPUT3, x, 303, 0, Z), " &
"301 (BC_4, RAD(28), INPUT, x), " &
"300 (BC_2, *, control, 0), " &
"299 (BC_1, RAD(28), OUTPUT3, x, 300, 0, Z), " &
"298 (BC_4, RAD(29), INPUT, x), " &
"297 (BC_2, *, control, 0), " &
"296 (BC_1, RAD(29), OUTPUT3, x, 297, 0, Z), " &
"295 (BC_4, RAD(30), INPUT, x), " &
"294 (BC_2, *, control, 0), " &
"293 (BC_1, RAD(30), OUTPUT3, x, 294, 0, Z), " &
"292 (BC_4, RAD(31), INPUT, x), " &
"291 (BC_2, *, control, 0), " &
"290 (BC_1, RAD(31), OUTPUT3, x, 291, 0, Z), " &
"289 (BC_4, RBEN_N(0), INPUT, x), " &
"288 (BC_2, *, control, 0), " &
"287 (BC_1, RBEN_N(0), OUTPUT3, x, 288, 0, Z), " &
"286 (BC_4, RBEN_N(1), INPUT, x), " &
"285 (BC_2, *, control, 0), " &
"284 (BC_1, RBEN_N(1), OUTPUT3, x, 285, 0, Z), " &
"283 (BC_4, RBEN_N(2), INPUT, x), " &
"282 (BC_2, *, control, 0), " &
"281 (BC_1, RBEN_N(2), OUTPUT3, x, 282, 0, Z), " &
"280 (BC_4, RBEN_N(3), INPUT, x), " &
"279 (BC_2, *, control, 0), " &
"278 (BC_1, RBEN_N(3), OUTPUT3, x, 279, 0, Z), " &
"277 (BC_4, RWE_N, INPUT, x), " &
"276 (BC_2, *, control, 0), " &
"275 (BC_1, RWE_N, OUTPUT3, x, 276, 0, Z), " &
"274 (BC_4, ROE_N, INPUT, x), " &
"273 (BC_2, *, control, 0), " &
"272 (BC_1, ROE_N, OUTPUT3, x, 273, 0, Z), " &
"271 (BC_4, RCE_N(0), INPUT, x), " &
"270 (BC_2, *, control, 0), " &
"269 (BC_1, RCE_N(0), OUTPUT3, x, 270, 0, Z), " &
"268 (BC_4, RCE_N(1), INPUT, x), " &
"267 (BC_2, *, control, 0), " &
"266 (BC_1, RCE_N(1), OUTPUT3, x, 267, 0, Z), " &
"265 (BC_4, RCE_N(2), INPUT, x), " &
"264 (BC_2, *, control, 0), " &
"263 (BC_1, RCE_N(2), OUTPUT3, x, 264, 0, Z), " &
"262 (BC_4, U0RXD, INPUT, x), " &
"261 (BC_4, RCE_N(3), INPUT, x), " &
"260 (BC_2, *, control, 0), " &
"259 (BC_1, RCE_N(3), OUTPUT3, x, 260, 0, Z), " &
"258 (BC_4, U0TXD, INPUT, x), " &
"257 (BC_2, *, control, 0), " &
"256 (BC_1, U0TXD, OUTPUT3, x, 257, 0, Z), " &
"255 (BC_4, U3TXD, INPUT, x), " &
"254 (BC_2, *, control, 0), " &
"253 (BC_1, U3TXD, OUTPUT3, x, 254, 0, Z), " &
"252 (BC_4, U3RXD, INPUT, x), " &
"251 (BC_4, DEVSEL_N, INPUT, x), " &
"250 (BC_2, *, control, 0), " &
"249 (BC_1, DEVSEL_N, OUTPUT3, x, 250, 0, Z), " &
"248 (BC_4, STOP_N, INPUT, x), " &
"247 (BC_2, *, control, 0), " &
"246 (BC_1, STOP_N, OUTPUT3, x, 247, 0, Z), " &
"245 (BC_4, FRAME_N, INPUT, x), " &
"244 (BC_2, *, control, 0), " &
"243 (BC_1, FRAME_N, OUTPUT3, x, 244, 0, Z), " &
"242 (BC_4, IRDY_N, INPUT, x), " &
"241 (BC_2, *, control, 0), " &
"240 (BC_1, IRDY_N, OUTPUT3, x, 241, 0, Z), " &
"239 (BC_4, TRDY_N, INPUT, x), " &
"238 (BC_2, *, control, 0), " &
"237 (BC_1, TRDY_N, OUTPUT3, x, 238, 0, Z), " &
"236 (BC_4, PCILOCK_N, INPUT, x), " &
"235 (BC_4, PCICLK, INPUT, x), " &
"234 (BC_1, PCICLKO, OUTPUT2, x), " &
"233 (BC_4, PCIREQ_N(0), INPUT, x), " &
"232 (BC_4, PCIPAR, INPUT, x), " &
"231 (BC_2, *, control, 0), " &
"230 (BC_1, PCIPAR, OUTPUT3, x, 231, 0, Z), " &
"229 (BC_4, PCIREQ_N(1), INPUT, x), " &
"228 (BC_4, PCIREQ_N(2), INPUT, x), " &
"227 (BC_4, PCIGNT_N(0), INPUT, x), " &
"226 (BC_2, *, control, 0), " &
"225 (BC_1, PCIGNT_N(0), OUTPUT3, x, 226, 0, Z), " &
"224 (BC_4, PCIGNT_N(1), INPUT, x), " &
"223 (BC_2, *, control, 0), " &
"222 (BC_1, PCIGNT_N(1), OUTPUT3, x, 223, 0, Z), " &
"221 (BC_4, PCIREQ_N(3), INPUT, x), " &
"220 (BC_4, PCIGNT_N(2), INPUT, x), " &
"219 (BC_2, *, control, 0), " &
"218 (BC_1, PCIGNT_N(2), OUTPUT3, x, 219, 0, Z), " &
"217 (BC_4, PCIGNT_N(3), INPUT, x), " &
"216 (BC_2, *, control, 0), " &
"215 (BC_1, PCIGNT_N(3), OUTPUT3, x, 216, 0, Z), " &
"214 (BC_4, PERR_N, INPUT, x), " &
"213 (BC_2, *, control, 0), " &
"212 (BC_1, PERR_N, OUTPUT3, x, 213, 0, Z), " &
"211 (BC_4, SERR_N, INPUT, x), " &
"210 (BC_2, *, control, 0), " &
"209 (BC_1, SERR_N, OUTPUT3, x, 210, 0, Z), " &
"208 (BC_4, PCICFG, INPUT, x), " &
"207 (BC_4, AD(0), INPUT, x), " &
"206 (BC_2, *, control, 0), " &
"205 (BC_1, AD(0), OUTPUT3, x, 206, 0, Z), " &
"204 (BC_4, AD(1), INPUT, x), " &
"203 (BC_2, *, control, 0), " &
"202 (BC_1, AD(1), OUTPUT3, x, 203, 0, Z), " &
"201 (BC_4, AD(2), INPUT, x), " &
"200 (BC_2, *, control, 0), " &
"199 (BC_1, AD(2), OUTPUT3, x, 200, 0, Z), " &
"198 (BC_4, AD(3), INPUT, x), " &
"197 (BC_2, *, control, 0), " &
"196 (BC_1, AD(3), OUTPUT3, x, 197, 0, Z), " &
"195 (BC_4, AD(4), INPUT, x), " &
"194 (BC_2, *, control, 0), " &
"193 (BC_1, AD(4), OUTPUT3, x, 194, 0, Z), " &
"192 (BC_4, AD(5), INPUT, x), " &
"191 (BC_2, *, control, 0), " &
"190 (BC_1, AD(5), OUTPUT3, x, 191, 0, Z), " &
"189 (BC_4, AD(6), INPUT, x), " &
"188 (BC_2, *, control, 0), " &
"187 (BC_1, AD(6), OUTPUT3, x, 188, 0, Z), " &
"186 (BC_4, AD(7), INPUT, x), " &
"185 (BC_2, *, control, 0), " &
"184 (BC_1, AD(7), OUTPUT3, x, 185, 0, Z), " &
"183 (BC_4, AD(8), INPUT, x), " &
"182 (BC_2, *, control, 0), " &
"181 (BC_1, AD(8), OUTPUT3, x, 182, 0, Z), " &
"180 (BC_4, AD(9), INPUT, x), " &
"179 (BC_2, *, control, 0), " &
"178 (BC_1, AD(9), OUTPUT3, x, 179, 0, Z), " &
"177 (BC_4, AD(10), INPUT, x), " &
"176 (BC_2, *, control, 0), " &
"175 (BC_1, AD(10), OUTPUT3, x, 176, 0, Z), " &
"174 (BC_4, AD(11), INPUT, x), " &
"173 (BC_2, *, control, 0), " &
"172 (BC_1, AD(11), OUTPUT3, x, 173, 0, Z), " &
"171 (BC_4, AD(12), INPUT, x), " &
"170 (BC_2, *, control, 0), " &
"169 (BC_1, AD(12), OUTPUT3, x, 170, 0, Z), " &
"168 (BC_4, AD(13), INPUT, x), " &
"167 (BC_2, *, control, 0), " &
"166 (BC_1, AD(13), OUTPUT3, x, 167, 0, Z), " &
"165 (BC_4, AD(14), INPUT, x), " &
"164 (BC_2, *, control, 0), " &
"163 (BC_1, AD(14), OUTPUT3, x, 164, 0, Z), " &
"162 (BC_4, AD(15), INPUT, x), " &
"161 (BC_2, *, control, 0), " &
"160 (BC_1, AD(15), OUTPUT3, x, 161, 0, Z), " &
"159 (BC_4, AD(16), INPUT, x), " &
"158 (BC_2, *, control, 0), " &
"157 (BC_1, AD(16), OUTPUT3, x, 158, 0, Z), " &
"156 (BC_4, AD(17), INPUT, x), " &
"155 (BC_2, *, control, 0), " &
"154 (BC_1, AD(17), OUTPUT3, x, 155, 0, Z), " &
"153 (BC_4, UHCP, INPUT, x), " &
"152 (BC_4, UHCM, INPUT, x), " &
"151 (BC_2, *, control, 0), " &
"150 (BC_1, UHCM, OUTPUT3, x, 151, 0, Z), " &
"149 (BC_1, UHCP, OUTPUT3, x, 151, 0, Z), " &
"148 (BC_4, UDCP, INPUT, x), " &
"147 (BC_4, UDCM, INPUT, x), " &
"146 (BC_2, *, control, 0), " &
"145 (BC_1, UDCM, OUTPUT3, x, 146, 0, Z), " &
"144 (BC_1, UDCP, OUTPUT3, x, 146, 0, Z), " &
"143 (BC_4, AD(18), INPUT, x), " &
"142 (BC_2, *, control, 0), " &
"141 (BC_1, AD(18), OUTPUT3, x, 142, 0, Z), " &
"140 (BC_4, AD(19), INPUT, x), " &
"139 (BC_2, *, control, 0), " &
"138 (BC_1, AD(19), OUTPUT3, x, 139, 0, Z), " &
"137 (BC_4, AD(20), INPUT, x), " &
"136 (BC_2, *, control, 0), " &
"135 (BC_1, AD(20), OUTPUT3, x, 136, 0, Z), " &
"134 (BC_4, AD(21), INPUT, x), " &
"133 (BC_2, *, control, 0), " &
"132 (BC_1, AD(21), OUTPUT3, x, 133, 0, Z), " &
"131 (BC_4, AD(22), INPUT, x), " &
"130 (BC_2, *, control, 0), " &
"129 (BC_1, AD(22), OUTPUT3, x, 130, 0, Z), " &
"128 (BC_4, AD(23), INPUT, x), " &
"127 (BC_2, *, control, 0), " &
"126 (BC_1, AD(23), OUTPUT3, x, 127, 0, Z), " &
"125 (BC_4, AD(24), INPUT, x), " &
"124 (BC_2, *, control, 0), " &
"123 (BC_1, AD(24), OUTPUT3, x, 124, 0, Z), " &
"122 (BC_4, AD(25), INPUT, x), " &
"121 (BC_2, *, control, 0), " &
"120 (BC_1, AD(25), OUTPUT3, x, 121, 0, Z), " &
"119 (BC_4, AD(26), INPUT, x), " &
"118 (BC_2, *, control, 0), " &
"117 (BC_1, AD(26), OUTPUT3, x, 118, 0, Z), " &
"116 (BC_4, AD(27), INPUT, x), " &
"115 (BC_2, *, control, 0), " &
"114 (BC_1, AD(27), OUTPUT3, x, 115, 0, Z), " &
"113 (BC_4, AD(28), INPUT, x), " &
"112 (BC_2, *, control, 0), " &
"111 (BC_1, AD(28), OUTPUT3, x, 112, 0, Z), " &
"110 (BC_4, AD(29), INPUT, x), " &
"109 (BC_2, *, control, 0), " &
"108 (BC_1, AD(29), OUTPUT3, x, 109, 0, Z), " &
"107 (BC_4, AD(30), INPUT, x), " &
"106 (BC_2, *, control, 0), " &
"105 (BC_1, AD(30), OUTPUT3, x, 106, 0, Z), " &
"104 (BC_4, AD(31), INPUT, x), " &
"103 (BC_2, *, control, 0), " &
"102 (BC_1, AD(31), OUTPUT3, x, 103, 0, Z), " &
"101 (BC_4, IDSEL, INPUT, x), " &
"100 (BC_4, CBE_N(0), INPUT, x), " &
"99 (BC_2, *, control, 0), " &
"98 (BC_1, CBE_N(0), OUTPUT3, x, 99, 0, Z), " &
"97 (BC_4, CBE_N(1), INPUT, x), " &
"96 (BC_2, *, control, 0), " &
"95 (BC_1, CBE_N(1), OUTPUT3, x, 96, 0, Z), " &
"94 (BC_4, INTA, INPUT, x), " &
"93 (BC_4, CBE_N(2), INPUT, x), " &
"92 (BC_2, *, control, 0), " &
"91 (BC_1, CBE_N(2), OUTPUT3, x, 92, 0, Z), " &
"90 (BC_4, CBE_N(3), INPUT, x), " &
"89 (BC_2, *, control, 0), " &
"88 (BC_1, CBE_N(3), OUTPUT3, x, 89, 0, Z), " &
"87 (BC_4, INTB, INPUT, x), " &
"86 (BC_4, INTC, INPUT, x), " &
"85 (BC_4, INTD, INPUT, x), " &
"84 (BC_4, GPIO2(0), INPUT, x), " &
"83 (BC_2, *, control, 0), " &
"82 (BC_1, GPIO2(0), OUTPUT3, x, 83, 0, Z), " &
"81 (BC_4, PCIRST, INPUT, x), " &
"80 (BC_4, N0TXCLK, INPUT, x), " &
"79 (BC_4, GPIO2(1), INPUT, x), " &
"78 (BC_2, *, control, 0), " &
"77 (BC_1, GPIO2(1), OUTPUT3, x, 78, 0, Z), " &
"76 (BC_4, GPIO2(2), INPUT, x), " &
"75 (BC_2, *, control, 0), " &
"74 (BC_1, GPIO2(2), OUTPUT3, x, 75, 0, Z), " &
"73 (BC_4, N0CRS, INPUT, x), " &
"72 (BC_4, N0RXD(0), INPUT, x), " &
"71 (BC_4, N0RXD(1), INPUT, x), " &
"70 (BC_4, GPIO2(3), INPUT, x), " &
"69 (BC_2, *, control, 0), " &
"68 (BC_1, GPIO2(3), OUTPUT3, x, 69, 0, Z), " &
"67 (BC_4, N0RXD(2), INPUT, x), " &
"66 (BC_4, N0RXD(3), INPUT, x), " &
"65 (BC_4, GPIO2(4), INPUT, x), " &
"64 (BC_2, *, control, 0), " &
"63 (BC_1, GPIO2(4), OUTPUT3, x, 64, 0, Z), " &
"62 (BC_4, GPIO2(5), INPUT, x), " &
"61 (BC_2, *, control, 0), " &
"60 (BC_1, GPIO2(5), OUTPUT3, x, 61, 0, Z), " &
"59 (BC_4, N0RXCLK, INPUT, x), " &
"58 (BC_4, N0RXDV, INPUT, x), " &
"57 (BC_4, N0TXEN, INPUT, x), " &
"56 (BC_2, *, control, 0), " &
"55 (BC_1, N0TXEN, OUTPUT3, x, 56, 0, Z), " &
"54 (BC_4, N0TXD(0), INPUT, x), " &
"53 (BC_2, *, control, 0), " &
"52 (BC_1, N0TXD(0), OUTPUT3, x, 53, 0, Z), " &
"51 (BC_4, N0COL, INPUT, x), " &
"50 (BC_4, N1TXCLK, INPUT, x), " &
"49 (BC_4, N0TXD(1), INPUT, x), " &
"48 (BC_2, *, control, 0), " &
"47 (BC_1, N0TXD(1), OUTPUT3, x, 48, 0, Z), " &
"46 (BC_4, N0TXD(2), INPUT, x), " &
"45 (BC_2, *, control, 0), " &
"44 (BC_1, N0TXD(2), OUTPUT3, x, 45, 0, Z), " &
"43 (BC_4, N0TXD(3), INPUT, x), " &
"42 (BC_2, *, control, 0), " &
"41 (BC_1, N0TXD(3), OUTPUT3, x, 42, 0, Z), " &
"40 (BC_4, N1CRS, INPUT, x), " &
"39 (BC_4, N1RXD(0), INPUT, x), " &
"38 (BC_4, N0MDC, INPUT, x), " &
"37 (BC_2, *, control, 0), " &
"36 (BC_1, N0MDC, OUTPUT3, x, 37, 0, Z), " &
"35 (BC_4, N0MDIO, INPUT, x), " &
"34 (BC_2, *, control, 0), " &
"33 (BC_1, N0MDIO, OUTPUT3, x, 34, 0, Z), " &
"32 (BC_4, N1RXD(1), INPUT, x), " &
"31 (BC_4, N1TXEN, INPUT, x), " &
"30 (BC_2, *, control, 0), " &
"29 (BC_1, N1TXEN, OUTPUT3, x, 30, 0, Z), " &
"28 (BC_4, N1RXD(2), INPUT, x), " &
"27 (BC_4, N1RXD(3), INPUT, x), " &
"26 (BC_4, N1TXD(0), INPUT, x), " &
"25 (BC_2, *, control, 0), " &
"24 (BC_1, N1TXD(0), OUTPUT3, x, 25, 0, Z), " &
"23 (BC_4, N1TXD(1), INPUT, x), " &
"22 (BC_2, *, control, 0), " &
"21 (BC_1, N1TXD(1), OUTPUT3, x, 22, 0, Z), " &
"20 (BC_4, N1RXCLK, INPUT, x), " &
"19 (BC_4, N1RXDV, INPUT, x), " &
"18 (BC_4, N1TXD(2), INPUT, x), " &
"17 (BC_2, *, control, 0), " &
"16 (BC_1, N1TXD(2), OUTPUT3, x, 17, 0, Z), " &
"15 (BC_4, N1TXD(3), INPUT, x), " &
"14 (BC_2, *, control, 0), " &
"13 (BC_1, N1TXD(3), OUTPUT3, x, 14, 0, Z), " &
"12 (BC_4, N1MDC, INPUT, x), " &
"11 (BC_2, *, control, 0), " &
"10 (BC_1, N1MDC, OUTPUT3, x, 11, 0, Z), " &
"9 (BC_4, N1COL, INPUT, x), " &
"8 (BC_4, N1MDIO, INPUT, x), " &
"7 (BC_2, *, control, 0), " &
"6 (BC_1, N1MDIO, OUTPUT3, x, 7, 0, Z), " &
"5 (BC_4, GPIO2(6), INPUT, x), " &
"4 (BC_2, *, control, 0), " &
"3 (BC_1, GPIO2(6), OUTPUT3, x, 4, 0, Z), " &
"2 (BC_4, GPIO2(7), INPUT, x), " &
"1 (BC_2, *, control, 0), " &
"0 (BC_1, GPIO2(7), OUTPUT3, x, 1, 0, Z)";
end AU1500;