BSDL Files Library for JTAG

The only free public library that contains thousands of BSDL (Boundary Scan Description Language) models to use with BScan/JTAG tools

BSDL model: Tsi384

-- ***************************************************************
--      Company:  Integrated Device Technology,Inc.
--
--      Document number: 35E1000_BS003_02
--
--      Title: BSDL file of Tsi384
--      Generated by : Anjaneya Reddy
--
--      Release status: formal issue
--      Security level: client use
--      BSDL Version 2001
--      Group ownership: DFT         Revision Date: 
--      Released by  :      Anjaneya 
--      Revision History:
--              Jan 12, 2007       :   initial release.
--	        Aprl 4, 2007       :   update ID version to '1' for A1.
--              September 25, 2007 :   Updated ID version to '2' for A2 and 
--                                     set acjt_lvl, tx_lvl bits in IR bits.  
--              February 29, 2008  :   Updated ID version to '3' for A3 
--              September 2, 2009  :   Updated with IDT formatting
--              
--      BSDL Syntax Checker ->  passed on February 29, 2008
--
--           
--           
-- ***************************************************************
--
-- Generated by boundaryScanGenerate 4.2b-Build20051027.004 on 10/15/06 16:14:24
-- BSDL Version 2001
-- 
-- In Instruction Register the bits [63:19] are termed as userBits[44:0].
-- The default acjt_lvl[4:0] which is userBits[11:7] is set to 5'h0A, and
-- tx_lvl[4:0] which is userbits[17:13] is set to 5'h00
-- and userBits[12] set to 1'b1.



entity Tsi384 is 
    generic (PHYSICAL_PIN_MAP : string := "PBGA_256_17");

    port (
        -- Port List
        PCIE_REFCLK_n        : linkage  bit;
        PCIE_REFCLK_p        : linkage  bit;
        VDDA_PCIE            : linkage  bit;
        VDD_PCIE             : linkage  bit;
        PCIE_TXD_p           : out      bit_vector( 3 downto 0 );
        PCIE_TXD_n           : out      bit_vector( 3 downto 0 );
        PCIE_RXD_p           : in       bit_vector( 3 downto 0 );
        PCIE_RXD_n           : in       bit_vector( 3 downto 0 );
        PCIE_PERSTn          : inout    bit;
        PCI_CLKO             : inout    bit_vector( 4 downto 0 );
        PCI_SEL100           : inout    bit;
        PCI_INTDn            : inout    bit;
        PCI_INTAn            : inout    bit;
        PCI_INTBn            : inout    bit;
        PCI_INTCn            : inout    bit;
        PCI_GNTn             : inout    bit_vector( 3 downto 0 );
        PCI_CLK              : inout    bit;
        PCI_REQn             : inout    bit_vector( 3 downto 0 );
        PCI_RSTn             : inout    bit;
        PCI_PMEn             : inout    bit;
        PCI_AD               : inout    bit_vector( 63 downto 0 );
        PCI_CBEn             : inout    bit_vector( 7 downto 0 );
        PCIE_LANE_VALIDn     : out      bit_vector( 3 downto 0 );
        SR_CSn               : inout    bit;
        SR_CLK               : inout    bit;
        SR_DOUT              : inout    bit;
        SR_DIN               : inout    bit;
        PCI_PAR64            : inout    bit;
        PCI_FRAMEn           : inout    bit;
        PCI_IRDYn            : inout    bit;
        PCI_PCIXCAP_PU       : inout    bit;
        PCI_DEVSELn          : inout    bit;
        PCI_TRDYn            : inout    bit;
        PCI_PCIXCAP          : inout    bit;
        PCI_STOPn            : inout    bit;
        PCI_PERRn            : inout    bit;
        PCI_PAR              : inout    bit;
        PCI_SERRn            : inout    bit;
        PCI_M66EN            : inout    bit;
        PCI_ACK64n           : inout    bit;
        PCI_REQ64n           : inout    bit;
        PWRUP_CLK_MST        : linkage  bit;
        JTAG_TDO             : out      bit;
        JTAG_TDI             : in       bit;
        JTAG_TCK             : in       bit;
        PWRUP_EN_ARB         : linkage  bit;
        JTAG_TMS             : in       bit;
        JTAG_TRSTn           : in       bit;
        TEST_BCE             : in  bit;
        PWRUP_PLL_BYPASSn    : linkage  bit;
        TEST_ON              : in  bit;
        PWRUP_EXT_CLK_SEL    : linkage  bit;
        TEST_BIDR_CTL        : in  bit;
        VDD                  : linkage  bit;
        VDD_PCI              : linkage  bit;
        VSS                  : linkage  bit;
        VDDA_PLL             : linkage  bit;
        VSSA_PLL             : linkage  bit);

    use STD_1149_1_2001.all;
    use STD_1149_6_2003.all;
    use LVS_BSCAN_CELLS.all;

    attribute COMPONENT_CONFORMANCE of Tsi384: entity is "STD_1149_1_2001";

    --Pin mappings

    attribute PIN_MAP of Tsi384: entity is PHYSICAL_PIN_MAP;

    constant PBGA_256_17: PIN_MAP_STRING := 
    "PCIE_REFCLK_n        : R3  , " &
    "PCIE_REFCLK_p        : T3  , " &
    "VDDA_PCIE            : P4  , " &
    "VDD_PCIE             : P8  , " &
    "PCIE_TXD_p           :(R11  , " &  -- PCIE_TXD_p[3]
                           "R9  , " &  -- PCIE_TXD_p[2]
                           "R7  , " &  -- PCIE_TXD_p[1]
                           "R5 ), " &  -- PCIE_TXD_p[0]
    "PCIE_TXD_n           :(T11  , " &  -- PCIE_TXD_n[3]
                           "T9  , " &  -- PCIE_TXD_n[2]
                           "T7  , " &  -- PCIE_TXD_n[1]
                           "T5 ), " &  -- PCIE_TXD_n[0]
    "PCIE_RXD_p           :(N11  , " &  -- PCIE_RXD_p[3]
                           "N9  , " &  -- PCIE_RXD_p[2]
                           "N7  , " &  -- PCIE_RXD_p[1]
                           "N5 ), " &  -- PCIE_RXD_p[0]
    "PCIE_RXD_n           :(M11  , " &  -- PCIE_RXD_n[3]
                           "M9  , " &  -- PCIE_RXD_n[2]
                           "M7  , " &  -- PCIE_RXD_n[1]
                           "M5 ), " &  -- PCIE_RXD_n[0]
    "PCIE_PERSTn          : T1  , " &
    "PCI_CLKO             :(N3   , " &  -- PCI_CLKO[4]
                           "L1   , " &  -- PCI_CLKO[3]
                           "L2   , " &  -- PCI_CLKO[2]
                           "K1   , " &  -- PCI_CLKO[1]
                           "K3  ), " &  -- PCI_CLKO[0]
    "PCI_SEL100           : M4  , " &
    "PCI_INTDn            : M2   , " &
    "PCI_INTAn            : L3   , " &
    "PCI_INTBn            : M1   , " &
    "PCI_INTCn            : K4   , " &
    "PCI_GNTn             :(J3   , " &  -- PCI_GNTn[3]
                           "J4   , " &  -- PCI_GNTn[2]
                           "H3   , " &  -- PCI_GNTn[1]
                           "G3  ), " &  -- PCI_GNTn[0]
    "PCI_CLK              : J1   , " &
    "PCI_REQn             :(H1   , " &  -- PCI_REQn[3]
                           "H2   , " &  -- PCI_REQn[2]
                           "G1   , " &  -- PCI_REQn[1]
                           "G2  ), " &  -- PCI_REQn[0]
    "PCI_RSTn             : H4   , " &
    "PCI_PMEn             : G4   , " &
    "PCI_AD               :(A15    , " &  -- PCI_AD[63]
                           "C15    , " &  -- PCI_AD[62]
                           "A16    , " &  -- PCI_AD[61]
                           "D14    , " &  -- PCI_AD[60]
                           "B16    , " &  -- PCI_AD[59]
                           "D15    , " &  -- PCI_AD[58]
                           "C16    , " &  -- PCI_AD[57]
                           "E13   , " &  -- PCI_AD[56]
                           "D16   , " &  -- PCI_AD[55]
                           "E14   , " &  -- PCI_AD[54]
                           "E15   , " &  -- PCI_AD[53]
                           "F13   , " &  -- PCI_AD[52]
                           "E16   , " &  -- PCI_AD[51]
                           "F14   , " &  -- PCI_AD[50]
                           "F16   , " &  -- PCI_AD[49]
                           "G13   , " &  -- PCI_AD[48]
                           "G16   , " &  -- PCI_AD[47]
                           "G14   , " &  -- PCI_AD[46]
                           "H15   , " &  -- PCI_AD[45]
                           "H13   , " &  -- PCI_AD[44]
                           "H16   , " &  -- PCI_AD[43]
                           "H14   , " &  -- PCI_AD[42]
                           "J15   , " &  -- PCI_AD[41]
                           "J13   , " &  -- PCI_AD[40]
                           "J16   , " &  -- PCI_AD[39]
                           "J14   , " &  -- PCI_AD[38]
                           "K15   , " &  -- PCI_AD[37]
                           "K13   , " &  -- PCI_AD[36]
                           "K16   , " &  -- PCI_AD[35]
                           "K14   , " &  -- PCI_AD[34]
                           "L16   , " &  -- PCI_AD[33]
                           "L14   , " &  -- PCI_AD[32]
                           "F1   , " &  -- PCI_AD[31]
                           "F3   , " &  -- PCI_AD[30]
                           "E1   , " &  -- PCI_AD[29]
                           "F4   , " &  -- PCI_AD[28]
                           "D1   , " &  -- PCI_AD[27]
                           "E3   , " &  -- PCI_AD[26]
                           "D2   , " &  -- PCI_AD[25]
                           "D3   , " &  -- PCI_AD[24]
                           "B1   , " &  -- PCI_AD[23]
                           "C2   , " &  -- PCI_AD[22]
                           "A1   , " &  -- PCI_AD[21]
                           "C3   , " &  -- PCI_AD[20]
                           "A2   , " &  -- PCI_AD[19]
                           "D4   , " &  -- PCI_AD[18]
                           "B3   , " &  -- PCI_AD[17]
                           "C4   , " &  -- PCI_AD[16]
                           "C7   , " &  -- PCI_AD[15]
                           "A7   , " &  -- PCI_AD[14]
                           "D8   , " &  -- PCI_AD[13]
                           "A8   , " &  -- PCI_AD[12]
                           "C8   , " &  -- PCI_AD[11]
                           "A9   , " &  -- PCI_AD[10]
                           "D9   , " &  -- PCI_AD[9]
                           "B10   , " &  -- PCI_AD[8]
                           "A10   , " &  -- PCI_AD[7]
                           "C10   , " &  -- PCI_AD[6]
                           "B11   , " &  -- PCI_AD[5]
                           "D11   , " &  -- PCI_AD[4]
                           "A11   , " &  -- PCI_AD[3]
                           "C11   , " &  -- PCI_AD[2]
                           "A12   , " &  -- PCI_AD[1]
                           "C12  ), " &  -- PCI_AD[0]
    "PCI_CBEn             :(C13   , " &  -- PCI_CBEn[7]
                           "A14   , " &  -- PCI_CBEn[6]
                           "D13   , " &  -- PCI_CBEn[5]
                           "B14   , " &  -- PCI_CBEn[4]
                           "C1   , " &  -- PCI_CBEn[3]
                           "A3   , " &  -- PCI_CBEn[2]
                           "B7   , " &  -- PCI_CBEn[1]
                           "D10  ), " &  -- PCI_CBEn[0]
    "PCIE_LANE_VALIDn     :(R16  , " &  -- PCIE_LANE_VALIDn[3]
                           "T16  , " &  -- PCIE_LANE_VALIDn[2]
                           "R15  , " &  -- PCIE_LANE_VALIDn[1]
                           "T15 ), " &  -- PCIE_LANE_VALIDn[0]
    "SR_CSn               : N15  , " &
    "SR_CLK               : M14  , " &
    "SR_DOUT              : N16  , " &
    "SR_DIN               : M16  , " &
    "PCI_PAR64            : C14  , " &
    "PCI_FRAMEn           : D5  , " &
    "PCI_IRDYn            : B4  , " &
    "PCI_PCIXCAP_PU       : C5  , " &
    "PCI_DEVSELn          : A4  , " &
    "PCI_TRDYn            : D6  , " &
    "PCI_PCIXCAP          : A5  , " &
    "PCI_STOPn            : C6  , " &
    "PCI_PERRn            : B6  , " &
    "PCI_PAR              : D7  , " &
    "PCI_SERRn            : A6  , " &
    "PCI_M66EN            : B9  , " &
    "PCI_ACK64n           : A13  , " &
    "PCI_REQ64n           : D12  , " &
    "PWRUP_CLK_MST        : L4   , " &
    "JTAG_TDO             : N1  , " &
    "JTAG_TDI             : N2  , " &
    "JTAG_TCK             : P1  , " &
    "PWRUP_EN_ARB         : L5  , " &
    "JTAG_TMS             : P2  , " &
    "JTAG_TRSTn           : R1  , " &
    "TEST_BCE             : R2  , " &
    "PWRUP_PLL_BYPASSn    : P3  , " &
    "TEST_ON              : T2  , " &
    "PWRUP_EXT_CLK_SEL    : N6  , " &
    "TEST_BIDR_CTL        : P16  , " &
    "VDD                  : E6    , " &
    "VDD_PCI              : E7   , " &
    "VSS                  : F6   , " &
    "VDDA_PLL             : M8  , " &
    "VSSA_PLL             : N4    " ;

    attribute PORT_GROUPING of Tsi384 : entity is 
        "Differential_Current ( (PCIE_TXD_p(1), PCIE_TXD_n(1)), " &
                                "(PCIE_RXD_p(1), PCIE_RXD_n(1)), " &
                                "(PCIE_TXD_p(0), PCIE_TXD_n(0)), " &
                                "(PCIE_RXD_p(0), PCIE_RXD_n(0)), " &
                                "(PCIE_TXD_p(2), PCIE_TXD_n(2)), " &
                                "(PCIE_RXD_p(2), PCIE_RXD_n(2)), " &
                                "(PCIE_TXD_p(3), PCIE_TXD_n(3)), " &
                                "(PCIE_RXD_p(3), PCIE_RXD_n(3))) " ;
 
 
 
   attribute TAP_SCAN_RESET of JTAG_TRSTn                   : signal is true;
   attribute TAP_SCAN_IN    of JTAG_TDI                     : signal is true;
   attribute TAP_SCAN_MODE  of JTAG_TMS                     : signal is true;
   attribute TAP_SCAN_OUT   of JTAG_TDO                     : signal is true;
   attribute TAP_SCAN_CLOCK of JTAG_TCK                     : signal is (1.0000000000000000000e+07, BOTH);

    attribute COMPLIANCE_PATTERNS of Tsi384 : entity is 
        "(TEST_BIDR_CTL, TEST_ON, TEST_BCE) (111)"; 
 
 
   attribute INSTRUCTION_LENGTH of Tsi384: entity is 54;
 
   attribute INSTRUCTION_OPCODE of Tsi384: entity is
      "IDCODE       (111111111111111111111111111111111111111111111111111110)," &
      "BYPASS       (000000000000000000000000000000000000000000000000000000, 111111111111111111111111111111111111111111111111111111)," &
      "EXTEST       (111111111111111111111101010111111111111111111111101000)," &
      "EXTEST_PULSE (111111111111111111111101010111111111101111111111101000)," &
      "EXTEST_TRAIN (111111111111111111111101010111111111011111111111101000)," &
      "SAMPLE       (111111111111111111111101010111111111111111111111111000)," &
      "PRELOAD      (111111111111111111111101010111111111111111111111111000)," &
      "CLAMP        (111111111111111111111101010111111111111111111111101111) " ;
 
   attribute INSTRUCTION_CAPTURE of Tsi384: entity is "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx01";
 
   attribute IDCODE_REGISTER of Tsi384: entity is
      "0011"             & -- version
      "0000001110000100" & -- part number
      "00010110011"      & -- manufacturer's identity
      "1";                   -- required by 1149.1
 
   attribute REGISTER_ACCESS of Tsi384: entity is
      "BOUNDARY     ( EXTEST_PULSE, EXTEST_TRAIN )," &
      "BOUNDARY     ( SAMPLE, PRELOAD )," &
      "BYPASS       ( CLAMP, BYPASS ) " ;


    --Boundary scan definition
    attribute BOUNDARY_LENGTH of Tsi384: entity is 237;

    attribute BOUNDARY_REGISTER of Tsi384: entity is 
    -- num  cell         port               function       safe     [ccell disval  rslt]
    "  236  (BC_1       , *                , control      , 0   )                          ,"&
    "  235  (AC_1       , PCIE_TXD_p(1)    , output3      , X    ,   236    , 0     , Z   ),"&
    "  234  (BC_4       , PCIE_RXD_p(1)    , observe_only , X   )                          ,"&
    "  233  (BC_4       , PCIE_RXD_n(1)    , observe_only , X   )                          ,"&
    "  232  (BC_1       , *                , control      , 0   )                          ,"&
    "  231  (AC_1       , PCIE_TXD_p(0)    , output3      , X    ,   232    , 0     , Z   ),"&
    "  230  (BC_4       , PCIE_RXD_p(0)    , observe_only , X   )                          ,"&
    "  229  (BC_4       , PCIE_RXD_n(0)    , observe_only , X   )                          ,"&
    "  228  (BC_1       , *                , control      , 0   )                          ,"&
    "  227  (AC_1       , PCIE_TXD_p(2)    , output3      , X    ,   228    , 0     , Z   ),"&
    "  226  (BC_4       , PCIE_RXD_p(2)    , observe_only , X   )                          ,"&
    "  225  (BC_4       , PCIE_RXD_n(2)    , observe_only , X   )                          ,"&
    "  224  (BC_1       , *                , control      , 0   )                          ,"&
    "  223  (AC_1       , PCIE_TXD_p(3)    , output3      , X    ,   224    , 0     , Z   ),"&
    "  222  (BC_4       , PCIE_RXD_p(3)    , observe_only , X   )                          ,"&
    "  221  (BC_4       , PCIE_RXD_n(3)    , observe_only , X   )                          ,"&
    "  220  (BC_2       , *                , control      , 0   )                          ,"&
    "  219  (LV_BC_7    , PCIE_PERSTn      , bidir        , X    ,   220    , 0     , Z   ),"&
    "  218  (BC_2       , *                , control      , 0   )                          ,"&
    "  217  (LV_BC_7    , PCI_CLKO(4)      , bidir        , X    ,   218    , 0     , Z   ),"&
    "  216  (LV_BC_7    , PCI_SEL100       , bidir        , X    ,   220    , 0     , Z   ),"&
    "  215  (BC_2       , *                , control      , 0   )                          ,"&
    "  214  (LV_BC_7    , PCI_INTDn        , bidir        , X    ,   215    , 0     , Z   ),"&
    "  213  (LV_BC_7    , PCI_INTAn        , bidir        , X    ,   215    , 0     , Z   ),"&
    "  212  (LV_BC_7    , PCI_INTBn        , bidir        , X    ,   215    , 0     , Z   ),"&
    "  211  (BC_2       , *                , control      , 0   )                          ,"&
    "  210  (LV_BC_7    , PCI_CLKO(2)      , bidir        , X    ,   211    , 0     , Z   ),"&
    "  209  (LV_BC_7    , PCI_INTCn        , bidir        , X    ,   215    , 0     , Z   ),"&
    "  208  (BC_2       , *                , control      , 0   )                          ,"&
    "  207  (LV_BC_7    , PCI_CLKO(3)      , bidir        , X    ,   208    , 0     , Z   ),"&
    "  206  (BC_2       , *                , control      , 0   )                          ,"&
    "  205  (LV_BC_7    , PCI_CLKO(0)      , bidir        , X    ,   206    , 0     , Z   ),"&
    "  204  (BC_2       , *                , control      , 0   )                          ,"&
    "  203  (LV_BC_7    , PCI_CLKO(1)      , bidir        , X    ,   204    , 0     , Z   ),"&
    "  202  (BC_2       , *                , control      , 0   )                          ,"&
    "  201  (LV_BC_7    , PCI_GNTn(2)      , bidir        , X    ,   202    , 0     , Z   ),"&
    "  200  (BC_2       , *                , control      , 0   )                          ,"&
    "  199  (LV_BC_7    , PCI_GNTn(3)      , bidir        , X    ,   200    , 0     , Z   ),"&
    "  198  (LV_BC_7    , PCI_CLK          , bidir        , X    ,   220    , 0     , Z   ),"&
    "  197  (LV_BC_7    , PCI_REQn(3)      , bidir        , X    ,   220    , 0     , Z   ),"&
    "  196  (BC_2       , *                , control      , 0   )                          ,"&
    "  195  (LV_BC_7    , PCI_REQn(2)      , bidir        , X    ,   196    , 0     , Z   ),"&
    "  194  (BC_2       , *                , control      , 0   )                          ,"&
    "  193  (LV_BC_7    , PCI_GNTn(1)      , bidir        , X    ,   194    , 0     , Z   ),"&
    "  192  (BC_2       , *                , control      , 0   )                          ,"&
    "  191  (LV_BC_7    , PCI_RSTn         , bidir        , X    ,   192    , 0     , Z   ),"&
    "  190  (LV_BC_7    , PCI_REQn(1)      , bidir        , X    ,   196    , 0     , Z   ),"&
    "  189  (BC_2       , *                , control      , 0   )                          ,"&
    "  188  (LV_BC_7    , PCI_REQn(0)      , bidir        , X    ,   189    , 0     , Z   ),"&
    "  187  (BC_2       , *                , control      , 0   )                          ,"&
    "  186  (LV_BC_7    , PCI_GNTn(0)      , bidir        , X    ,   187    , 0     , Z   ),"&
    "  185  (LV_BC_7    , PCI_PMEn         , bidir        , X    ,   196    , 0     , Z   ),"&
    "  184  (BC_2       , *                , control      , 0   )                          ,"&
    "  183  (LV_BC_7    , PCI_AD(31)       , bidir        , X    ,   184    , 0     , Z   ),"&
    "  182  (BC_2       , *                , control      , 0   )                          ,"&
    "  181  (LV_BC_7    , PCI_AD(30)       , bidir        , X    ,   182    , 0     , Z   ),"&
    "  180  (BC_2       , *                , control      , 0   )                          ,"&
    "  179  (LV_BC_7    , PCI_AD(29)       , bidir        , X    ,   180    , 0     , Z   ),"&
    "  178  (BC_2       , *                , control      , 0   )                          ,"&
    "  177  (LV_BC_7    , PCI_AD(28)       , bidir        , X    ,   178    , 0     , Z   ),"&
    "  176  (BC_2       , *                , control      , 0   )                          ,"&
    "  175  (LV_BC_7    , PCI_AD(27)       , bidir        , X    ,   176    , 0     , Z   ),"&
    "  174  (BC_2       , *                , control      , 0   )                          ,"&
    "  173  (LV_BC_7    , PCI_AD(26)       , bidir        , X    ,   174    , 0     , Z   ),"&
    "  172  (BC_2       , *                , control      , 0   )                          ,"&
    "  171  (LV_BC_7    , PCI_AD(25)       , bidir        , X    ,   172    , 0     , Z   ),"&
    "  170  (BC_2       , *                , control      , 0   )                          ,"&
    "  169  (LV_BC_7    , PCI_CBEn(3)      , bidir        , X    ,   170    , 0     , Z   ),"&
    "  168  (BC_2       , *                , control      , 0   )                          ,"&
    "  167  (LV_BC_7    , PCI_AD(24)       , bidir        , X    ,   168    , 0     , Z   ),"&
    "  166  (BC_2       , *                , control      , 0   )                          ,"&
    "  165  (LV_BC_7    , PCI_AD(22)       , bidir        , X    ,   166    , 0     , Z   ),"&
    "  164  (BC_2       , *                , control      , 0   )                          ,"&
    "  163  (LV_BC_7    , PCI_AD(23)       , bidir        , X    ,   164    , 0     , Z   ),"&
    "  162  (BC_2       , *                , control      , 0   )                          ,"&
    "  161  (LV_BC_7    , PCI_AD(20)       , bidir        , X    ,   162    , 0     , Z   ),"&
    "  160  (BC_2       , *                , control      , 0   )                          ,"&
    "  159  (BC_2       , PCIE_LANE_VALIDn(0) , output3      , X    ,   160    , 0     , Z   ),"&
    "  158  (BC_2       , PCIE_LANE_VALIDn(2) , output3      , X    ,   160    , 0     , Z   ),"&
    "  157  (BC_2       , PCIE_LANE_VALIDn(1) , output3      , X    ,   160    , 0     , Z   ),"&
    "  156  (BC_2       , PCIE_LANE_VALIDn(3) , output3      , X    ,   160    , 0     , Z   ),"&
    "  155  (BC_2       , *                , control      , 0   )                          ,"&
    "  154  (LV_BC_7    , SR_CSn           , bidir        , X    ,   155    , 0     , Z   ),"&
    "  153  (BC_2       , *                , control      , 0   )                          ,"&
    "  152  (LV_BC_7    , SR_CLK           , bidir        , X    ,   153    , 0     , Z   ),"&
    "  151  (BC_2       , *                , control      , 0   )                          ,"&
    "  150  (LV_BC_7    , SR_DOUT          , bidir        , X    ,   151    , 0     , Z   ),"&
    "  149  (BC_2       , *                , control      , 0   )                          ,"&
    "  148  (LV_BC_7    , SR_DIN           , bidir        , X    ,   149    , 0     , Z   ),"&
    "  147  (BC_2       , *                , control      , 0   )                          ,"&
    "  146  (LV_BC_7    , PCI_AD(32)       , bidir        , X    ,   147    , 0     , Z   ),"&
    "  145  (BC_2       , *                , control      , 0   )                          ,"&
    "  144  (LV_BC_7    , PCI_AD(33)       , bidir        , X    ,   145    , 0     , Z   ),"&
    "  143  (BC_2       , *                , control      , 0   )                          ,"&
    "  142  (LV_BC_7    , PCI_AD(36)       , bidir        , X    ,   143    , 0     , Z   ),"&
    "  141  (BC_2       , *                , control      , 0   )                          ,"&
    "  140  (LV_BC_7    , PCI_AD(34)       , bidir        , X    ,   141    , 0     , Z   ),"&
    "  139  (BC_2       , *                , control      , 0   )                          ,"&
    "  138  (LV_BC_7    , PCI_AD(37)       , bidir        , X    ,   139    , 0     , Z   ),"&
    "  137  (BC_2       , *                , control      , 0   )                          ,"&
    "  136  (LV_BC_7    , PCI_AD(35)       , bidir        , X    ,   137    , 0     , Z   ),"&
    "  135  (BC_2       , *                , control      , 0   )                          ,"&
    "  134  (LV_BC_7    , PCI_AD(41)       , bidir        , X    ,   135    , 0     , Z   ),"&
    "  133  (BC_2       , *                , control      , 0   )                          ,"&
    "  132  (LV_BC_7    , PCI_AD(40)       , bidir        , X    ,   133    , 0     , Z   ),"&
    "  131  (BC_2       , *                , control      , 0   )                          ,"&
    "  130  (LV_BC_7    , PCI_AD(38)       , bidir        , X    ,   131    , 0     , Z   ),"&
    "  129  (BC_2       , *                , control      , 0   )                          ,"&
    "  128  (LV_BC_7    , PCI_AD(39)       , bidir        , X    ,   129    , 0     , Z   ),"&
    "  127  (BC_2       , *                , control      , 0   )                          ,"&
    "  126  (LV_BC_7    , PCI_AD(43)       , bidir        , X    ,   127    , 0     , Z   ),"&
    "  125  (BC_2       , *                , control      , 0   )                          ,"&
    "  124  (LV_BC_7    , PCI_AD(45)       , bidir        , X    ,   125    , 0     , Z   ),"&
    "  123  (BC_2       , *                , control      , 0   )                          ,"&
    "  122  (LV_BC_7    , PCI_AD(42)       , bidir        , X    ,   123    , 0     , Z   ),"&
    "  121  (BC_2       , *                , control      , 0   )                          ,"&
    "  120  (LV_BC_7    , PCI_AD(44)       , bidir        , X    ,   121    , 0     , Z   ),"&
    "  119  (BC_2       , *                , control      , 0   )                          ,"&
    "  118  (LV_BC_7    , PCI_AD(47)       , bidir        , X    ,   119    , 0     , Z   ),"&
    "  117  (BC_2       , *                , control      , 0   )                          ,"&
    "  116  (LV_BC_7    , PCI_AD(46)       , bidir        , X    ,   117    , 0     , Z   ),"&
    "  115  (BC_2       , *                , control      , 0   )                          ,"&
    "  114  (LV_BC_7    , PCI_AD(49)       , bidir        , X    ,   115    , 0     , Z   ),"&
    "  113  (BC_2       , *                , control      , 0   )                          ,"&
    "  112  (LV_BC_7    , PCI_AD(48)       , bidir        , X    ,   113    , 0     , Z   ),"&
    "  111  (BC_2       , *                , control      , 0   )                          ,"&
    "  110  (LV_BC_7    , PCI_AD(50)       , bidir        , X    ,   111    , 0     , Z   ),"&
    "  109  (BC_2       , *                , control      , 0   )                          ,"&
    "  108  (LV_BC_7    , PCI_AD(51)       , bidir        , X    ,   109    , 0     , Z   ),"&
    "  107  (BC_2       , *                , control      , 0   )                          ,"&
    "  106  (LV_BC_7    , PCI_AD(53)       , bidir        , X    ,   107    , 0     , Z   ),"&
    "  105  (BC_2       , *                , control      , 0   )                          ,"&
    "  104  (LV_BC_7    , PCI_AD(52)       , bidir        , X    ,   105    , 0     , Z   ),"&
    "  103  (BC_2       , *                , control      , 0   )                          ,"&
    "  102  (LV_BC_7    , PCI_AD(55)       , bidir        , X    ,   103    , 0     , Z   ),"&
    "  101  (BC_2       , *                , control      , 0   )                          ,"&
    "  100  (LV_BC_7    , PCI_AD(54)       , bidir        , X    ,   101    , 0     , Z   ),"&
    "  99   (BC_2       , *                , control      , 0   )                          ,"&
    "  98   (LV_BC_7    , PCI_AD(58)       , bidir        , X    ,   99     , 0     , Z   ),"&
    "  97   (BC_2       , *                , control      , 0   )                          ,"&
    "  96   (LV_BC_7    , PCI_AD(57)       , bidir        , X    ,   97     , 0     , Z   ),"&
    "  95   (BC_2       , *                , control      , 0   )                          ,"&
    "  94   (LV_BC_7    , PCI_AD(56)       , bidir        , X    ,   95     , 0     , Z   ),"&
    "  93   (BC_2       , *                , control      , 0   )                          ,"&
    "  92   (LV_BC_7    , PCI_AD(60)       , bidir        , X    ,   93     , 0     , Z   ),"&
    "  91   (BC_2       , *                , control      , 0   )                          ,"&
    "  90   (LV_BC_7    , PCI_AD(62)       , bidir        , X    ,   91     , 0     , Z   ),"&
    "  89   (BC_2       , *                , control      , 0   )                          ,"&
    "  88   (LV_BC_7    , PCI_AD(59)       , bidir        , X    ,   89     , 0     , Z   ),"&
    "  87   (BC_2       , *                , control      , 0   )                          ,"&
    "  86   (LV_BC_7    , PCI_PAR64        , bidir        , X    ,   87     , 0     , Z   ),"&
    "  85   (BC_2       , *                , control      , 0   )                          ,"&
    "  84   (LV_BC_7    , PCI_AD(18)       , bidir        , X    ,   85     , 0     , Z   ),"&
    "  83   (BC_2       , *                , control      , 0   )                          ,"&
    "  82   (LV_BC_7    , PCI_AD(21)       , bidir        , X    ,   83     , 0     , Z   ),"&
    "  81   (BC_2       , *                , control      , 0   )                          ,"&
    "  80   (LV_BC_7    , PCI_AD(19)       , bidir        , X    ,   81     , 0     , Z   ),"&
    "  79   (BC_2       , *                , control      , 0   )                          ,"&
    "  78   (LV_BC_7    , PCI_AD(17)       , bidir        , X    ,   79     , 0     , Z   ),"&
    "  77   (BC_2       , *                , control      , 0   )                          ,"&
    "  76   (LV_BC_7    , PCI_AD(16)       , bidir        , X    ,   77     , 0     , Z   ),"&
    "  75   (BC_2       , *                , control      , 0   )                          ,"&
    "  74   (LV_BC_7    , PCI_FRAMEn       , bidir        , X    ,   75     , 0     , Z   ),"&
    "  73   (BC_2       , *                , control      , 0   )                          ,"&
    "  72   (LV_BC_7    , PCI_CBEn(2)      , bidir        , X    ,   73     , 0     , Z   ),"&
    "  71   (BC_2       , *                , control      , 0   )                          ,"&
    "  70   (LV_BC_7    , PCI_IRDYn        , bidir        , X    ,   71     , 0     , Z   ),"&
    "  69   (BC_2       , *                , control      , 0   )                          ,"&
    "  68   (LV_BC_7    , PCI_PCIXCAP_PU   , bidir        , X    ,   69     , 0     , Z   ),"&
    "  67   (BC_2       , *                , control      , 0   )                          ,"&
    "  66   (LV_BC_7    , PCI_DEVSELn      , bidir        , X    ,   67     , 0     , Z   ),"&
    "  65   (BC_2       , *                , control      , 0   )                          ,"&
    "  64   (LV_BC_7    , PCI_TRDYn        , bidir        , X    ,   65     , 0     , Z   ),"&
    "  63   (BC_2       , *                , control      , 0   )                          ,"&
    "  62   (LV_BC_7    , PCI_PCIXCAP      , bidir        , X    ,   63     , 0     , Z   ),"&
    "  61   (BC_2       , *                , control      , 0   )                          ,"&
    "  60   (LV_BC_7    , PCI_STOPn        , bidir        , X    ,   61     , 0     , Z   ),"&
    "  59   (BC_2       , *                , internal     , X   )                          ,"&
    "  58   (BC_2       , *                , internal     , X   )                          ,"&
    "  57   (BC_2       , *                , control      , 0   )                          ,"&
    "  56   (LV_BC_7    , PCI_PERRn        , bidir        , X    ,   57     , 0     , Z   ),"&
    "  55   (BC_2       , *                , control      , 0   )                          ,"&
    "  54   (LV_BC_7    , PCI_PAR          , bidir        , X    ,   55     , 0     , Z   ),"&
    "  53   (LV_BC_7    , PCI_SERRn        , bidir        , X    ,   63     , 0     , Z   ),"&
    "  52   (BC_2       , *                , control      , 0   )                          ,"&
    "  51   (LV_BC_7    , PCI_AD(15)       , bidir        , X    ,   52     , 0     , Z   ),"&
    "  50   (BC_2       , *                , control      , 0   )                          ,"&
    "  49   (LV_BC_7    , PCI_CBEn(1)      , bidir        , X    ,   50     , 0     , Z   ),"&
    "  48   (BC_2       , *                , control      , 0   )                          ,"&
    "  47   (LV_BC_7    , PCI_AD(14)       , bidir        , X    ,   48     , 0     , Z   ),"&
    "  46   (BC_2       , *                , control      , 0   )                          ,"&
    "  45   (LV_BC_7    , PCI_AD(13)       , bidir        , X    ,   46     , 0     , Z   ),"&
    "  44   (BC_2       , *                , control      , 0   )                          ,"&
    "  43   (LV_BC_7    , PCI_AD(11)       , bidir        , X    ,   44     , 0     , Z   ),"&
    "  42   (BC_2       , *                , control      , 0   )                          ,"&
    "  41   (LV_BC_7    , PCI_AD(12)       , bidir        , X    ,   42     , 0     , Z   ),"&
    "  40   (BC_2       , *                , control      , 0   )                          ,"&
    "  39   (LV_BC_7    , PCI_AD(10)       , bidir        , X    ,   40     , 0     , Z   ),"&
    "  38   (LV_BC_7    , PCI_M66EN        , bidir        , X    ,   63     , 0     , Z   ),"&
    "  37   (BC_2       , *                , control      , 0   )                          ,"&
    "  36   (LV_BC_7    , PCI_AD(9)        , bidir        , X    ,   37     , 0     , Z   ),"&
    "  35   (BC_2       , *                , control      , 0   )                          ,"&
    "  34   (LV_BC_7    , PCI_AD(7)        , bidir        , X    ,   35     , 0     , Z   ),"&
    "  33   (BC_2       , *                , control      , 0   )                          ,"&
    "  32   (LV_BC_7    , PCI_AD(8)        , bidir        , X    ,   33     , 0     , Z   ),"&
    "  31   (BC_2       , *                , control      , 0   )                          ,"&
    "  30   (LV_BC_7    , PCI_AD(6)        , bidir        , X    ,   31     , 0     , Z   ),"&
    "  29   (BC_2       , *                , control      , 0   )                          ,"&
    "  28   (LV_BC_7    , PCI_AD(3)        , bidir        , X    ,   29     , 0     , Z   ),"&
    "  27   (BC_2       , *                , control      , 0   )                          ,"&
    "  26   (LV_BC_7    , PCI_CBEn(0)      , bidir        , X    ,   27     , 0     , Z   ),"&
    "  25   (BC_2       , *                , control      , 0   )                          ,"&
    "  24   (LV_BC_7    , PCI_AD(5)        , bidir        , X    ,   25     , 0     , Z   ),"&
    "  23   (BC_2       , *                , control      , 0   )                          ,"&
    "  22   (LV_BC_7    , PCI_AD(2)        , bidir        , X    ,   23     , 0     , Z   ),"&
    "  21   (BC_2       , *                , control      , 0   )                          ,"&
    "  20   (LV_BC_7    , PCI_AD(1)        , bidir        , X    ,   21     , 0     , Z   ),"&
    "  19   (BC_2       , *                , control      , 0   )                          ,"&
    "  18   (LV_BC_7    , PCI_AD(4)        , bidir        , X    ,   19     , 0     , Z   ),"&
    "  17   (BC_2       , *                , control      , 0   )                          ,"&
    "  16   (LV_BC_7    , PCI_ACK64n       , bidir        , X    ,   17     , 0     , Z   ),"&
    "  15   (BC_2       , *                , control      , 0   )                          ,"&
    "  14   (LV_BC_7    , PCI_AD(0)        , bidir        , X    ,   15     , 0     , Z   ),"&
    "  13   (BC_2       , *                , control      , 0   )                          ,"&
    "  12   (LV_BC_7    , PCI_CBEn(6)      , bidir        , X    ,   13     , 0     , Z   ),"&
    "  11   (BC_2       , *                , control      , 0   )                          ,"&
    "  10   (LV_BC_7    , PCI_REQ64n       , bidir        , X    ,   11     , 0     , Z   ),"&
    "  9    (BC_2       , *                , control      , 0   )                          ,"&
    "  8    (LV_BC_7    , PCI_CBEn(7)      , bidir        , X    ,   9      , 0     , Z   ),"&
    "  7    (BC_2       , *                , control      , 0   )                          ,"&
    "  6    (LV_BC_7    , PCI_CBEn(4)      , bidir        , X    ,   7      , 0     , Z   ),"&
    "  5    (BC_2       , *                , control      , 0   )                          ,"&
    "  4    (LV_BC_7    , PCI_AD(63)       , bidir        , X    ,   5      , 0     , Z   ),"&
    "  3    (BC_2       , *                , control      , 0   )                          ,"&
    "  2    (LV_BC_7    , PCI_AD(61)       , bidir        , X    ,   3      , 0     , Z   ),"&
    "  1    (BC_2       , *                , control      , 0   )                          ,"&
    "  0    (LV_BC_7    , PCI_CBEn(5)      , bidir        , X    ,   1      , 0     , Z   ) ";

    attribute AIO_COMPONENT_CONFORMANCE of Tsi384: entity is "STD_1149_6_2003";


    attribute AIO_Pin_Behavior of Tsi384: entity is 
        "PCIE_TXD_p(0);" &
        "PCIE_TXD_p(1);" &
        "PCIE_TXD_p(2);" &
        "PCIE_TXD_p(3);" &
        "PCIE_RXD_p(1)[234]       : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
        "PCIE_RXD_p(0)[230]       : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
        "PCIE_RXD_p(2)[226]       : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
        "PCIE_RXD_p(3)[222]       : LP_Time=2.30e-07 HP_Time=7.00e-06";
end Tsi384;
-- VHDL package to be uploaded
--package LVS_BSCAN_CELLS is
--    use STD_1149_1_2001.all;
--        constant LV_BC_7: CELL_INFO;
--
--end LVS_BSCAN_CELLS;
--package body LVS_BSCAN_CELLS is
--    use STD_1149_1_2001.all;
--        constant LV_BC_7: CELL_INFO := 
--           ((BIDIR_IN, EXTEST,  PI),  (BIDIR_OUT, EXTEST,  PO),
--           (BIDIR_IN, SAMPLE,  PI),  (BIDIR_OUT, SAMPLE,  PI),
--           (BIDIR_IN, INTEST,  X),  (BIDIR_OUT, INTEST,  PI));
--
--end LVS_BSCAN_CELLS;