-- M O T O R O L A S S D T J T A G S O F T W A R E
-- BSDL File Generated: Tues Jun 27 09:08:16 2000
--
-- Revision History:
--
entity DSP56F807VF80 is
generic (PHYSICAL_PIN_MAP : string := "VF"); -- 160MAPBGA
port ( TRST_B: in bit;
TDO: out bit;
TDI: in bit;
TMS: in bit;
TCK: in bit;
A0: inout bit;
A1: inout bit;
A2: inout bit;
A3: inout bit;
A4: inout bit;
A5: inout bit;
A6: inout bit;
A7: inout bit;
POWER_I01: linkage bit;
A8: inout bit;
A9: inout bit;
A10: inout bit;
A11: inout bit;
A12: inout bit;
A13: inout bit;
A14: inout bit;
A15: inout bit;
GROUND_IO1: linkage bit;
PS_B: inout bit;
DS_B: inout bit;
WR_B: inout bit;
RD_B: inout bit;
D0: inout bit;
D1: inout bit;
D2: inout bit;
D3: inout bit;
D4: inout bit;
D5: inout bit;
D6: inout bit;
D7: inout bit;
D8: inout bit;
D9: inout bit;
D10: inout bit;
POWER_IO2: linkage bit;
D11: inout bit;
D12: inout bit;
D13: inout bit;
D14: inout bit;
D15: inout bit;
MPIOB0: inout bit;
MPIOB1: inout bit;
MPIOB2: inout bit;
MPIOB3: inout bit;
MPIOB4: inout bit;
MPIOB5: inout bit;
MPIOB6: inout bit;
MPIOB7: inout bit;
GROUND_IO2: linkage bit;
MPIOD0: inout bit;
MPIOD1: inout bit;
MPIOD2: inout bit;
MPIOD3: inout bit;
MPIOD4: inout bit;
MPIOD5: inout bit;
TXD1: inout bit;
RXD1: inout bit;
PWMB0: out bit;
PWMB1: out bit;
PWMB2: out bit;
PWMB3: out bit;
PWMB4: out bit;
PWMB5: out bit;
POWER_IO3: linkage bit;
ISB0: in bit;
VCAPC1: linkage bit;
ISB1: in bit;
ISB2: in bit;
VPP2: linkage bit;
IREQA_B: in bit;
IREQB_B: in bit;
FAULTB0: in bit;
FAULTB1: in bit;
FAULTB2: in bit;
FAULTB3: in bit;
PWMA0: out bit;
GROUND_IO3: linkage bit;
PWMA1: out bit;
PWMA2: out bit;
PWMA3: out bit;
PWMA4: out bit;
PWMA5: out bit;
FAULTA0: in bit;
FAULTA1: in bit;
FAULTA2: in bit;
FAULTA3: in bit;
XBOOT: in bit;
VSSA_AREG1: linkage bit;
VDDA_AREG1: linkage bit;
POWER_IO7: linkage bit;
GROUND_IO8: linkage bit;
GROUND_IO7: linkage bit;
XTAL: linkage bit;
EXTAL: linkage bit;
POWER_IO4: linkage bit;
GROUND_IO4: linkage bit;
VDDA_CORE1: linkage bit;
RSTO_B: out bit;
RESET_B: in bit;
VRH: linkage bit;
VDDA_ADC2: linkage bit;
VSSA_ADC2: linkage bit;
ANA0: linkage bit;
ANA1: linkage bit;
ANA2: linkage bit;
ANA3: linkage bit;
ANA4: linkage bit;
ANA5: linkage bit;
ANA6: linkage bit;
ANA7: linkage bit;
VRH2: linkage bit;
VDDA_ADC1: linkage bit;
VSSA_ADC1: linkage bit;
ANA8: linkage bit;
ANA9: linkage bit;
ANA10: linkage bit;
ANA11: linkage bit;
ANA12: linkage bit;
ANA13: linkage bit;
ANA14: linkage bit;
ANA15: linkage bit;
DE_B: out bit;
GROUND_IO9: linkage bit;
ISA0: in bit;
ISA1: in bit;
ISA2: in bit;
TD0: inout bit;
TD1: inout bit;
TD2: inout bit;
TD3: inout bit;
TC0: inout bit;
TC1: inout bit;
TCS: linkage bit;
VCAPC2: linkage bit;
MSCAN_TX: out bit;
POWER_IO6: linkage bit;
GROUND_IO6: linkage bit;
MSCAN_RX: in bit;
SS_B: inout bit;
SCLK: inout bit;
MISO: inout bit;
MOSI: inout bit;
PHA0: inout bit;
PHB0: inout bit;
INDX0: inout bit;
HOME0: inout bit;
PHA1: inout bit;
PHB1: inout bit;
POWER_IO5: linkage bit;
INDX1: inout bit;
HOME1: inout bit;
VPP: linkage bit;
GROUND_IO5: linkage bit;
CLKO: out bit;
TXD0: inout bit;
RXD0: inout bit);
use STD_1149_1_1994.all;
attribute COMPONENT_CONFORMANCE of DSP56F807VF80 : entity is "STD_1149_1_1993";
attribute PIN_MAP of DSP56F807VF80 : entity is PHYSICAL_PIN_MAP;
constant VF : PIN_MAP_STRING :=
"A0: C3, " &
"A1: B2, " &
"A2: D3, " &
"A3: C2, " &
"A4: B1, " &
"A5: D2, " &
"A6: C1, " &
"A7: D1, " &
"POWER_I01: E3, " &
"A8: E2, " &
"A9: E1, " &
"A10: F3, " &
"A11: F2, " &
"A12: F1, " &
"A13: G3, " &
"A14: G2, " &
"A15: G1, " &
"GROUND_IO1: F4, " &
"PS_B: G4, " &
"DS_B: H4, " &
"WR_B: J4, " &
"RD_B: K4, " &
"D0: H3, " &
"D1: H1, " &
"D2: H2, " &
"D3: J3, " &
"D4: J1, " &
"D5: J2, " &
"D6: K3, " &
"D7: K1, " &
"D8: L1, " &
"D9: K2, " &
"D10: L3, " &
"POWER_IO2: M1, " &
"D11: L2, " &
"D12: N1, " &
"D13: M2, " &
"D14: N2, " &
"D15: M3, " &
"MPIOB0: L4, " &
"MPIOB1: P1, " &
"MPIOB2: N3, " &
"MPIOB3: P2, " &
"MPIOB4: P3, " &
"MPIOB5: N4, " &
"MPIOB6: P4, " &
"MPIOB7: M4, " &
"GROUND_IO2: L5, " &
"MPIOD0: N5, " &
"MPIOD1: P5, " &
"MPIOD2: K5, " &
"MPIOD3: N6, " &
"MPIOD4: L6, " &
"MPIOD5: K6, " &
"TXD1: P6, " &
"RXD1: N7, " &
"PWMB0: L7, " &
"PWMB1: P7, " &
"PWMB2: K7, " &
"PWMB3: L8, " &
"PWMB4: K8, " &
"PWMB5: P8, " &
"POWER_IO3: L9, " &
"ISB0: N8, " &
"VCAPC1: K10, " &
"ISB1: K9, " &
"ISB2: P9, " &
"VPP2: L10, " &
"IREQA_B: N9, " &
"IREQB_B: P10, " &
"FAULTB0: P11, " &
"FAULTB1: N10, " &
"FAULTB2: L11, " &
"FAULTB3: M11, " &
"PWMA0: P12, " &
"GROUND_IO3: N11, " &
"PWMA1: P13, " &
"PWMA2: N12, " &
"PWMA3: N13, " &
"PWMA4: M12, " &
"PWMA5: P14, " &
"FAULTA0: M13, " &
"FAULTA1: L12, " &
"FAULTA2: N14, " &
"FAULTA3: L13, " &
"XBOOT: M14, " &
"VSSA_AREG1: K12, " &
"VDDA_AREG1: K13, " &
"POWER_IO7: L14, " &
"GROUND_IO8: K11, " &
"GROUND_IO7: K14, " &
"XTAL: J13, " &
"EXTAL: J12, " &
"POWER_IO4: J14, " &
"GROUND_IO4: J11, " &
"VDDA_CORE1: H13, " &
"RSTO_B: H12, " &
"RESET_B: H14, " &
"VRH: H11, " &
"VDDA_ADC2: G12, " &
"VSSA_ADC2: G11, " &
"ANA0: G14, " &
"ANA1: F11, " &
"ANA2: G13, " &
"ANA3: F12, " &
"ANA4: F14, " &
"ANA5: E11, " &
"ANA6: F13, " &
"ANA7: E12, " &
"VRH2: E14, " &
"VDDA_ADC1: E13, " &
"VSSA_ADC1: D14, " &
"ANA8: D11, " &
"ANA9: D12, " &
"ANA10: D13, " &
"ANA11: C14, " &
"ANA12: C13, " &
"ANA13: C11, " &
"ANA14: B14, " &
"ANA15: C12, " &
"DE_B: B13, " &
"GROUND_IO9: A14, " &
"ISA0: B12, " &
"ISA1: A13, " &
"ISA2: A12, " &
"TD0: B11, " &
"TD1: A11, " &
"TD2: D10, " &
"TD3: B10, " &
"TC0: A10, " &
"TC1: E10, " &
"TRST_B: D9, " &
"TCS: B9, " &
"TCK: E9, " &
"TMS: A9, " &
"TDI: D8, " &
"TDO: B8, " &
"VCAPC2: A8, " &
"MSCAN_TX: E8, " &
"POWER_IO6: D7, " &
"GROUND_IO6: E7, " &
"MSCAN_RX: D6, " &
"SS_B: A7, " &
"SCLK: E5, " &
"MISO: B7, " &
"MOSI: A6, " &
"PHA0: E6, " &
"PHB0: D5, " &
"INDX0: B6, " &
"HOME0: A5, " &
"PHA1: E4, " &
"PHB1: B5, " &
"POWER_IO5: A4, " &
"INDX1: D4, " &
"HOME1: C4, " &
"VPP: B4, " &
"GROUND_IO5: A3, " &
"CLKO: A2, " &
"TXD0: B3, " &
"RXD0: A1";
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_RESET of TRST_B : signal is true;
attribute TAP_SCAN_CLOCK of TCK : signal is (10.0e6, BOTH);
attribute INSTRUCTION_LENGTH of DSP56F807VF80 : entity is 4;
attribute INSTRUCTION_OPCODE of DSP56F807VF80 : entity is
"EXTEST (0000)," &
"SAMPLE (0001)," &
"IDCODE (0010)," &
"CLAMP (0101)," &
"HIGHZ (0100)," &
"EXTEST_PULLUP (0011)," &
"ENABLE_ONCE (0110)," &
"DEBUG_REQUEST (0111)," &
"BYPASS (1111)";
attribute INSTRUCTION_CAPTURE of DSP56F807VF80 : entity is "XX01";
attribute INSTRUCTION_PRIVATE of DSP56F807VF80 : entity is
"ENABLE_ONCE, DEBUG_REQUEST ";
attribute IDCODE_REGISTER of DSP56F807VF80 : entity is
"00000001111100100111000000011101";
attribute REGISTER_ACCESS of DSP56F807VF80 : entity is
"BOUNDARY (EXTEST_PULLUP)," &
"BYPASS (ENABLE_ONCE," & "DEBUG_REQUEST)";
attribute BOUNDARY_LENGTH of DSP56F807VF80 : entity is 338;
attribute BOUNDARY_REGISTER of DSP56F807VF80 : entity is
-- num cell port func safe [ccell dis rslt]
"337 (BC_1, A0, input, X)," &
"336 (BC_1, A0, output3, X, 335, 1, Z)," &
"335 (BC_1, *, control, 1)," &
"334 (BC_1, *, internal, 1)," &
"333 (BC_1, A1, input, X)," &
"332 (BC_1, A1, output3, X, 331, 1, Z)," &
"331 (BC_1, *, control, 1)," &
"330 (BC_1, *, internal, 1)," &
"329 (BC_1, A2, input, X)," &
"328 (BC_1, A2, output3, X, 327, 1, Z)," &
"327 (BC_1, *, control, 1)," &
"326 (BC_1, *, internal, 1)," &
"325 (BC_1, A3, input, X)," &
"324 (BC_1, A3, output3, X, 323, 1, Z)," &
"323 (BC_1, *, control, 1)," &
"322 (BC_1, *, internal, 1)," &
"321 (BC_1, A4, input, X)," &
"320 (BC_1, A4, output3, X, 319, 1, Z)," &
"319 (BC_1, *, control, 1)," &
"318 (BC_1, *, internal, 1)," &
-- num cell port func safe [ccell dis rslt]
"317 (BC_1, A5, input, X)," &
"316 (BC_1, A5, output3, X, 315, 1, Z)," &
"315 (BC_1, *, control, 1)," &
"314 (BC_1, *, internal, 1)," &
"313 (BC_1, A6, input, X)," &
"312 (BC_1, A6, output3, X, 311, 1, Z)," &
"311 (BC_1, *, control, 1)," &
"310 (BC_1, *, internal, 1)," &
"309 (BC_1, A7, input, X)," &
"308 (BC_1, A7, output3, X, 307, 1, Z)," &
"307 (BC_1, *, control, 1)," &
"306 (BC_1, *, internal, 1)," &
"305 (BC_1, A8, input, X)," &
"304 (BC_1, A8, output3, X, 303, 1, Z)," &
"303 (BC_1, *, control, 1)," &
"302 (BC_1, *, internal, 1)," &
"301 (BC_1, A9, input, X)," &
"300 (BC_1, A9, output3, X, 299, 1, Z)," &
"299 (BC_1, *, control, 1)," &
"298 (BC_1, *, internal, 1)," &
-- num cell port func safe [ccell dis rslt]
"297 (BC_1, A10, input, X)," &
"296 (BC_1, A10, output3, X, 295, 1, Z)," &
"295 (BC_1, *, control, 1)," &
"294 (BC_1, *, internal, 1)," &
"293 (BC_1, A11, input, X)," &
"292 (BC_1, A11, output3, X, 291, 1, Z)," &
"291 (BC_1, *, control, 1)," &
"290 (BC_1, *, internal, 1)," &
"289 (BC_1, A12, input, X)," &
"288 (BC_1, A12, output3, X, 287, 1, Z)," &
"287 (BC_1, *, control, 1)," &
"286 (BC_1, *, internal, 1)," &
"285 (BC_1, A13, input, X)," &
"284 (BC_1, A13, output3, X, 283, 1, Z)," &
"283 (BC_1, *, control, 1)," &
"282 (BC_1, *, internal, 1)," &
"281 (BC_1, A14, input, X)," &
"280 (BC_1, A14, output3, X, 279, 1, Z)," &
"279 (BC_1, *, control, 1)," &
"278 (BC_1, *, internal, 1)," &
-- num cell port func safe [ccell dis rslt]
"277 (BC_1, A15, input, X)," &
"276 (BC_1, A15, output3, X, 275, 1, Z)," &
"275 (BC_1, *, control, 1)," &
"274 (BC_1, *, internal, 1)," &
"273 (BC_1, PS_B, input, X)," &
"272 (BC_1, PS_B, output3, X, 271, 1, Z)," &
"271 (BC_1, *, control, 1)," &
"270 (BC_1, *, internal, 1)," &
"269 (BC_1, DS_B, input, X)," &
"268 (BC_1, DS_B, output3, X, 267, 1, Z)," &
"267 (BC_1, *, control, 1)," &
"266 (BC_1, *, internal, 1)," &
"265 (BC_1, WR_B, input, X)," &
"264 (BC_1, WR_B, output3, X, 263, 1, Z)," &
"263 (BC_1, *, control, 1)," &
"262 (BC_1, *, internal, 1)," &
"261 (BC_1, RD_B, input, X)," &
"260 (BC_1, RD_B, output3, X, 259, 1, Z)," &
"259 (BC_1, *, control, 1)," &
"258 (BC_1, *, internal, 1)," &
-- num cell port func safe [ccell dis rslt]
"257 (BC_1, D0, input, X)," &
"256 (BC_1, D0, output3, X, 255, 1, Z)," &
"255 (BC_1, *, control, 1)," &
"254 (BC_1, *, internal, 1)," &
"253 (BC_1, D1, input, X)," &
"252 (BC_1, D1, output3, X, 251, 1, Z)," &
"251 (BC_1, *, control, 1)," &
"250 (BC_1, *, internal, 1)," &
"249 (BC_1, D2, input, X)," &
"248 (BC_1, D2, output3, X, 247, 1, Z)," &
"247 (BC_1, *, control, 1)," &
"246 (BC_1, *, internal, 1)," &
"245 (BC_1, D3, input, X)," &
"244 (BC_1, D3, output3, X, 243, 1, Z)," &
"243 (BC_1, *, control, 1)," &
"242 (BC_1, *, internal, 1)," &
"241 (BC_1, D4, input, X)," &
"240 (BC_1, D4, output3, X, 239, 1, Z)," &
"239 (BC_1, *, control, 1)," &
"238 (BC_1, *, internal, 1)," &
-- num cell port func safe [ccell dis rslt]
"237 (BC_1, D5, input, X)," &
"236 (BC_1, D5, output3, X, 235, 1, Z)," &
"235 (BC_1, *, control, 1)," &
"234 (BC_1, *, internal, 1)," &
"233 (BC_1, D6, input, X)," &
"232 (BC_1, D6, output3, X, 231, 1, Z)," &
"231 (BC_1, *, control, 1)," &
"230 (BC_1, *, internal, 1)," &
"229 (BC_1, D7, input, X)," &
"228 (BC_1, D7, output3, X, 227, 1, Z)," &
"227 (BC_1, *, control, 1)," &
"226 (BC_1, *, internal, 1)," &
"225 (BC_1, D8, input, X)," &
"224 (BC_1, D8, output3, X, 223, 1, Z)," &
"223 (BC_1, *, control, 1)," &
"222 (BC_1, *, internal, 1)," &
"221 (BC_1, D9, input, X)," &
"220 (BC_1, D9, output3, X, 219, 1, Z)," &
"219 (BC_1, *, control, 1)," &
"218 (BC_1, *, internal, 1)," &
-- num cell port func safe [ccell dis rslt]
"217 (BC_1, D10, input, X)," &
"216 (BC_1, D10, output3, X, 215, 1, Z)," &
"215 (BC_1, *, control, 1)," &
"214 (BC_1, *, internal, 1)," &
"213 (BC_1, D11, input, X)," &
"212 (BC_1, D11, output3, X, 211, 1, Z)," &
"211 (BC_1, *, control, 1)," &
"210 (BC_1, *, internal, 1)," &
"209 (BC_1, D12, input, X)," &
"208 (BC_1, D12, output3, X, 207, 1, Z)," &
"207 (BC_1, *, control, 1)," &
"206 (BC_1, *, internal, 1)," &
"205 (BC_1, D13, input, X)," &
"204 (BC_1, D13, output3, X, 203, 1, Z)," &
"203 (BC_1, *, control, 1)," &
"202 (BC_1, *, internal, 1)," &
"201 (BC_1, D14, input, X)," &
"200 (BC_1, D14, output3, X, 199, 1, Z)," &
"199 (BC_1, *, control, 1)," &
"198 (BC_1, *, internal, 1)," &
-- num cell port func safe [ccell dis rslt]
"197 (BC_1, D15, input, X)," &
"196 (BC_1, D15, output3, X, 195, 1, Z)," &
"195 (BC_1, *, control, 1)," &
"194 (BC_1, *, internal, 1)," &
"193 (BC_1, MPIOB0, input, X)," &
"192 (BC_1, MPIOB0, output3, X, 191, 1, Z)," &
"191 (BC_1, *, control, 1)," &
"190 (BC_1, *, internal, 1)," &
"189 (BC_1, MPIOB1, input, X)," &
"188 (BC_1, MPIOB1, output3, X, 187, 1, Z)," &
"187 (BC_1, *, control, 1)," &
"186 (BC_1, *, internal, 1)," &
"185 (BC_1, MPIOB2, input, X)," &
"184 (BC_1, MPIOB2, output3, X, 183, 1, Z)," &
"183 (BC_1, *, control, 1)," &
"182 (BC_1, *, internal, 1)," &
"181 (BC_1, MPIOB3, input, X)," &
"180 (BC_1, MPIOB3, output3, X, 179, 1, Z)," &
"179 (BC_1, *, control, 1)," &
"178 (BC_1, *, internal, 0)," &
-- num cell port func safe [ccell dis rslt]
"177 (BC_1, MPIOB4, input, X)," &
"176 (BC_1, MPIOB4, output3, X, 175, 1, Z)," &
"175 (BC_1, *, control, 1)," &
"174 (BC_1, *, internal, 1)," &
"173 (BC_1, MPIOB5, input, X)," &
"172 (BC_1, MPIOB5, output3, X, 171, 1, Z)," &
"171 (BC_1, *, control, 1)," &
"170 (BC_1, *, internal, 1)," &
"169 (BC_1, MPIOB6, input, X)," &
"168 (BC_1, MPIOB6, output3, X, 167, 1, Z)," &
"167 (BC_1, *, control, 1)," &
"166 (BC_1, *, internal, 1)," &
"165 (BC_1, MPIOB7, input, X)," &
"164 (BC_1, MPIOB7, output3, X, 163, 1, Z)," &
"163 (BC_1, *, control, 1)," &
"162 (BC_1, *, internal, 1)," &
"161 (BC_1, MPIOD0, input, X)," &
"160 (BC_1, MPIOD0, output3, X, 159, 1, Z)," &
"159 (BC_1, *, control, 1)," &
"158 (BC_1, *, internal, 1)," &
-- num cell port func safe [ccell dis rslt]
"157 (BC_1, MPIOD1, input, X)," &
"156 (BC_1, MPIOD1, output3, X, 155, 1, Z)," &
"155 (BC_1, *, control, 1)," &
"154 (BC_1, *, internal, 1)," &
"153 (BC_1, MPIOD2, input, X)," &
"152 (BC_1, MPIOD2, output3, X, 151, 1, Z)," &
"151 (BC_1, *, control, 1)," &
"150 (BC_1, *, internal, 1)," &
"149 (BC_1, MPIOD3, input, X)," &
"148 (BC_1, MPIOD3, output3, X, 147, 1, Z)," &
"147 (BC_1, *, control, 1)," &
"146 (BC_1, *, internal, 1)," &
"145 (BC_1, MPIOD4, input, X)," &
"144 (BC_1, MPIOD4, output3, X, 143, 1, Z)," &
"143 (BC_1, *, control, 1)," &
"142 (BC_1, *, internal, 1)," &
"141 (BC_1, MPIOD5, input, X)," &
"140 (BC_1, MPIOD5, output3, X, 139, 1, Z)," &
"139 (BC_1, *, control, 1)," &
"138 (BC_1, *, internal, 1)," &
-- num cell port func safe [ccell dis rslt]
"137 (BC_1, TXD1, input, X)," &
"136 (BC_1, TXD1, output3, X, 135, 1, Z)," &
"135 (BC_1, *, control, 1)," &
"134 (BC_1, *, internal, 1)," &
"133 (BC_1, RXD1, input, X)," &
"132 (BC_1, RXD1, output3, X, 131, 1, Z)," &
"131 (BC_1, *, control, 1)," &
"130 (BC_1, *, internal, 1)," &
"129 (BC_1, PWMB0, output3, X, 128, 1, Z)," &
"128 (BC_1, *, control, 1)," &
"127 (BC_1, PWMB1, output3, X, 126, 1, Z)," &
"126 (BC_1, *, control, 1)," &
"125 (BC_1, PWMB2, output3, X, 124, 1, Z)," &
"124 (BC_1, *, control, 1)," &
"123 (BC_1, PWMB3, output3, X, 122, 1, Z)," &
"122 (BC_1, *, control, 1)," &
"121 (BC_1, PWMB4, output3, X, 120, 1, Z)," &
"120 (BC_1, *, control, 1)," &
"119 (BC_1, PWMB5, output3, X, 118, 1, Z)," &
"118 (BC_1, *, control, 1)," &
-- num cell port func safe [ccell dis rslt]
"117 (BC_1, ISB0, input, X)," &
"116 (BC_1, ISB1, input, X)," &
"115 (BC_1, ISB2, input, X)," &
"114 (BC_1, IREQA_B, input, X)," &
"113 (BC_1, IREQB_B, input, X)," &
"112 (BC_1, FAULTB0, input, X)," &
"111 (BC_1, FAULTB1, input, X)," &
"110 (BC_1, FAULTB2, input, X)," &
"109 (BC_1, FAULTB3, input, X)," &
"108 (BC_1, PWMA0, output3, X, 107, 1, Z)," &
"107 (BC_1, *, control, 1)," &
"106 (BC_1, PWMA1, output3, X, 105, 1, Z)," &
"105 (BC_1, *, control, 1)," &
"104 (BC_1, PWMA2, output3, X, 103, 1, Z)," &
"103 (BC_1, *, control, 1)," &
"102 (BC_1, PWMA3, output3, X, 101, 1, Z)," &
"101 (BC_1, *, control, 1)," &
"100 (BC_1, PWMA4, output3, X, 99, 1, Z)," &
" 99 (BC_1, *, control, 1)," &
" 98 (BC_1, PWMA5, output3, X, 97, 1, Z)," &
-- num cell port func safe [ccell dis rslt]
" 97 (BC_1, *, control, 1)," &
" 96 (BC_1, FAULTA0, input, X)," &
" 95 (BC_1, FAULTA1, input, X)," &
" 94 (BC_1, FAULTA2, input, X)," &
" 93 (BC_1, FAULTA3, input, X)," &
" 92 (BC_1, XBOOT, input, X)," &
" 91 (BC_1, RSTO_B, output3, X, 90, 1, Z)," &
" 90 (BC_1, *, control, 1)," &
" 89 (BC_1, RESET_B, input, X)," &
" 88 (BC_1, DE_B, output3, X, 87, 1, Z)," &
" 87 (BC_1, *, control, 1)," &
" 86 (BC_1, ISA0, input, X)," &
" 85 (BC_1, ISA1, input, X)," &
" 84 (BC_1, ISA2, input, X)," &
" 83 (BC_1, TD0, input, X)," &
" 82 (BC_1, TD0, output3, X, 81, 1, Z)," &
" 81 (BC_1, *, control, 1)," &
" 80 (BC_1, *, internal, 1)," &
" 79 (BC_1, TD1, input, X)," &
" 78 (BC_1, TD1, output3, X, 77, 1, Z)," &
-- num cell port func safe [ccell dis rslt]
" 77 (BC_1, *, control, 1)," &
" 76 (BC_1, *, internal, 1)," &
" 75 (BC_1, TD2, input, X)," &
" 74 (BC_1, TD2, output3, X, 73, 1, Z)," &
" 73 (BC_1, *, control, 1)," &
" 72 (BC_1, *, internal, 1)," &
" 71 (BC_1, TD3, input, X)," &
" 70 (BC_1, TD3, output3, X, 69, 1, Z)," &
" 69 (BC_1, *, control, 1)," &
" 68 (BC_1, *, internal, 1)," &
" 67 (BC_1, TC0, input, X)," &
" 66 (BC_1, TC0, output3, X, 65, 1, Z)," &
" 65 (BC_1, *, control, 1)," &
" 64 (BC_1, *, internal, 1)," &
" 63 (BC_1, TC1, input, X)," &
" 62 (BC_1, TC1, output3, X, 61, 1, Z)," &
" 61 (BC_1, *, control, 1)," &
" 60 (BC_1, *, internal, 1)," &
" 59 (BC_1, MSCAN_TX, output2, 1, 59, 1, Weak1)," &
" 58 (BC_1, MSCAN_RX, input, X)," &
-- num cell port func safe [ccell dis rslt]
" 57 (BC_1, SS_B, input, X)," &
" 56 (BC_1, SS_B, output3, X, 55, 1, Z)," &
" 55 (BC_1, *, control, 1)," &
" 54 (BC_1, *, internal, 1)," &
" 53 (BC_1, SCLK, input, X)," &
" 52 (BC_1, SCLK, output3, X, 51, 1, Z)," &
" 51 (BC_1, *, control, 1)," &
" 50 (BC_1, *, internal, 1)," &
" 49 (BC_1, MISO, input, X)," &
" 48 (BC_1, MISO, output3, X, 47, 1, Z)," &
" 47 (BC_1, *, control, 1)," &
" 46 (BC_1, *, internal, 1)," &
" 45 (BC_1, MOSI, input, X)," &
" 44 (BC_1, MOSI, output3, X, 43, 1, Z)," &
" 43 (BC_1, *, control, 1)," &
" 42 (BC_1, *, internal, 1)," &
" 41 (BC_1, PHA0, input, X)," &
" 40 (BC_1, PHA0, output3, X, 39, 1, Z)," &
" 39 (BC_1, *, control, 1)," &
" 38 (BC_1, *, internal, 1)," &
-- num cell port func safe [ccell dis rslt]
" 37 (BC_1, PHB0, input, X)," &
" 36 (BC_1, PHB0, output3, X, 35, 1, Z)," &
" 35 (BC_1, *, control, 1)," &
" 34 (BC_1, *, internal, 1)," &
" 33 (BC_1, INDX0, input, X)," &
" 32 (BC_1, INDX0, output3, X, 31, 1, Z)," &
" 31 (BC_1, *, control, 1)," &
" 30 (BC_1, *, internal, 1)," &
" 29 (BC_1, HOME0, input, X)," &
" 28 (BC_1, HOME0, output3, X, 27, 1, Z)," &
" 27 (BC_1, *, control, 1)," &
" 26 (BC_1, *, internal, 1)," &
" 25 (BC_1, PHA1, input, X)," &
" 24 (BC_1, PHA1, output3, X, 23, 1, Z)," &
" 23 (BC_1, *, control, 1)," &
" 22 (BC_1, *, internal, 1)," &
" 21 (BC_1, PHB1, input, X)," &
" 20 (BC_1, PHB1, output3, X, 19, 1, Z)," &
" 19 (BC_1, *, control, 1)," &
" 18 (BC_1, *, internal, 1)," &
-- num cell port func safe [ccell dis rslt]
" 17 (BC_1, INDX1, input, X)," &
" 16 (BC_1, INDX1, output3, X, 15, 1, Z)," &
" 15 (BC_1, *, control, 1)," &
" 14 (BC_1, *, internal, 1)," &
" 13 (BC_1, HOME1, input, X)," &
" 12 (BC_1, HOME1, output3, X, 11, 1, Z)," &
" 11 (BC_1, *, control, 1)," &
" 10 (BC_1, *, internal, 1)," &
" 9 (BC_1, CLKO, output3, X, 8, 1, Z)," &
" 8 (BC_1, *, control, 1)," &
" 7 (BC_1, TXD0, input, X)," &
" 6 (BC_1, TXD0, output3, X, 5, 1, Z)," &
" 5 (BC_1, *, control, 1)," &
" 4 (BC_1, *, internal, 1)," &
" 3 (BC_1, RXD0, input, X)," &
" 2 (BC_1, RXD0, output3, X, 1, 1, Z)," &
" 1 (BC_1, *, control, 1)," &
" 0 (BC_1, *, internal, 1)" ;
end DSP56F807VF80;