BSDL Files Library for JTAG

The only free public library that contains thousands of BSDL (Boundary Scan Description Language) models to use with BScan/JTAG tools

BSDL model: PM73121

--  PMC_Sierra_Cells   VHDL Package and Package Body
--  for PMC - Sierra
--
--  revision     :  1.0
--
--  created by : James Lamond (Hewlett Packard Canada Ltd)
--
--  date         :  20 December 1995

package PMC_Sierra_Cells is

   use STD_1149_1_1990.all;

   constant cele0 : CELL_INFO;

end PMC_Sierra_Cells;


package body PMC_Sierra_Cells is

constant cele0 : CELL_INFO :=
 ((BIDIR_IN, EXTEST,  PI),  (BIDIR_OUT, EXTEST,  PO),
  (BIDIR_IN, SAMPLE,  PI),  (BIDIR_OUT, SAMPLE,  PI),
  (BIDIR_IN, RUNBIST, PI),  (BIDIR_OUT, RUNBIST, PO) );

end PMC_Sierra_Cells;  -- End of PMC_Sierra_Cells Package Body


------------------------------------------------------------------------------
--
--
-- PMC Sierra PM73121 AAL1gator II BSDL description
--
-- AAL1 SAR Processor DEVICE
--
-- Written by: PMC Sierra
-- Revised by: Jean-Francois Pomerleau (Hewlett Packard (Canada) Ltd)
-- Verified electrically against PM73121
-- Part # IC-WAC-121-A
-- Lot # RE23267
-- Date code: NNM 9812
-- Using HP3070 Boundary Scan S/W revision B.02.78
--
--
-- PM73121 BSDL Revision: 1.00 -- Original File created by PMC-Sierra
-- PM73121 BSDL Revision: 1.01 -- Change pu58 package type to LSI_PACKAGE
--                             -- Made by J-FP (HPCL) September 14th 1998
--                             -- Note: The cell description/type has not
--                             --       been verified by HP.
--
-- Notes:
-- 1. Input rise time and fall time is 10ns (max) which translates to a
--    minimum slew rate of 120V/us. During verification it is found that
--    the device is sensitive to noise and ringing on the SCAN_TCK. By
--    increasing the slew rate the device passes the verification test
--    consistently. (e.g. 250V/us) The exact value will depend on the
--    grounding and decoupling condition.
--
------------------------------------------------------------------------------
-
--
-- Testability Warnings:
--
-- Warning: Signal PRMON_OUT, pin 170 not connected to Boundary Register.
-- Warning: Signal PULLUP_DISABLE, pin 238 not connected to Boundary Register.
-- Unconnected signals (listed above) are not testable.
--
------------------------------------------------------------------------------
-

entity pm73121 is

generic (PHYSICAL_PIN_MAP : string := "LSI_PACKAGE");

port (
        scan_tms        : in           bit         ;
        scan_trstn      : in           bit         ;
        scan_tdo        : out          bit         ;
        scan_tck        : in           bit         ;
        prmon_out       : out          bit         ;
        holdoff         : out          bit         ;
        intr            : out          bit         ;
        ack_n           : out          bit         ;
        cs_n            : in           bit         ;
        wr_n            : in           bit         ;
        rd_n            : in           bit         ;
        sp_data_clk     : out          bit         ;
        reset_n         : in           bit         ;
        oe_n            : in           bit         ;
        sp_data_dir     : out          bit         ;
        sp_add_en_n     : out          bit         ;
        sp_data_en_n    : out          bit         ;
        mem_we0_n       : out          bit         ;
        mem_we1_n       : out          bit         ;
        mem_oe_n        : out          bit         ;
        mem_cs_n        : out          bit         ;
        memaddr_0_port  : inout        bit         ;
        memaddr_1_port  : inout        bit         ;
        memaddr_2_port  : inout        bit         ;
        memaddr_3_port  : inout        bit         ;
        memaddr_4_port  : inout        bit         ;
        memaddr_5_port  : inout        bit         ;
        memaddr_6_port  : inout        bit         ;
        memaddr_7_port  : inout        bit         ;
        memaddr_8_port  : inout        bit         ;
        memaddr_9_port  : inout        bit         ;
        memaddr_10_port : inout        bit         ;
        memaddr_11_port : inout        bit         ;
        memaddr_12_port : inout        bit         ;
        memaddr_13_port : inout        bit         ;
        memaddr_14_port : inout        bit         ;
        memaddr_15_port : inout        bit         ;
        memaddr_16_port : inout        bit         ;
        memaddr17       : in           bit         ;
        memdata_0_port  : inout        bit         ;
        memdata_1_port  : inout        bit         ;
        memdata_2_port  : inout        bit         ;
        memdata_3_port  : inout        bit         ;
        memdata_4_port  : inout        bit         ;
        memdata_5_port  : inout        bit         ;
        memdata_6_port  : inout        bit         ;
        memdata_7_port  : inout        bit         ;
        memdata_8_port  : inout        bit         ;
        memdata_9_port  : inout        bit         ;
        memdata_10_port : inout        bit         ;
        memdata_11_port : inout        bit         ;
        memdata_12_port : inout        bit         ;
        memdata_13_port : inout        bit         ;
        memdata_14_port : inout        bit         ;
        memdata_15_port : inout        bit         ;
        pullup_disable  : in           bit         ;
        rxdata_7_port   : in           bit         ;
        rxdata_6_port   : in           bit         ;
        rxdata_5_port   : in           bit         ;
        rxdata_4_port   : in           bit         ;
        rxdata_3_port   : in           bit         ;
        rxdata_2_port   : in           bit         ;
        rxdata_1_port   : in           bit         ;
        rxdata_0_port   : in           bit         ;
        rxsoc           : in           bit         ;
        rxempty_n       : in           bit         ;
        rxenb_n         : out          bit         ;
        rphy_addr       : in           bit         ;
        rxclk           : in           bit         ;
        tphy_addr       : in           bit         ;
        txclk           : in           bit         ;
        txenb_n         : out          bit         ;
        txfull_n        : in           bit         ;
        txsoc           : out          bit         ;
        txdata_7_port   : out          bit         ;
        txdata_6_port   : out          bit         ;
        txdata_5_port   : out          bit         ;
        txdata_4_port   : out          bit         ;
        txdata_3_port   : out          bit         ;
        txdata_2_port   : out          bit         ;
        txdata_1_port   : out          bit         ;
        txdata_0_port   : out          bit         ;
        srts_dout_3_port : out          bit         ;
        srts_dout_2_port : out          bit         ;
        srts_dout_1_port : out          bit         ;
        srts_dout_0_port : out          bit         ;
        srts_line_2_port : out          bit         ;
        srts_line_1_port : out          bit         ;
        srts_line_0_port : out          bit         ;
        srts_strobe     : out          bit         ;
        adap_strobe     : out          bit         ;
        nclk            : in           bit         ;
        srts_line_3_port : out          bit         ;
        tsig_0_port     : out          bit         ;
        tser_0_port     : out          bit         ;
        tmsync_0_port   : in           bit         ;
        tfsync_0_port   : in           bit         ;
        tclk_0_port     : inout        bit         ;
        phy_en          : in           bit         ;
        rclk_0_port     : in           bit         ;
        rfsync_0_port   : in           bit         ;
        rmsync_0_port   : in           bit         ;
        rser_0_port     : in           bit         ;
        rsig_0_port     : in           bit         ;
        tsig_1_port     : out          bit         ;
        tser_1_port     : out          bit         ;
        tmsync_1_port   : in           bit         ;
        tfsync_1_port   : in           bit         ;
        tclk_1_port     : inout        bit         ;
        rclk_1_port     : in           bit         ;
        rfsync_1_port   : in           bit         ;
        rmsync_1_port   : in           bit         ;
        rser_1_port     : in           bit         ;
        rsig_1_port     : in           bit         ;
        tlclk_src       : in           bit         ;
        tsig_2_port     : out          bit         ;
        tser_2_port     : out          bit         ;
        tmsync_2_port   : in           bit         ;
        tfsync_2_port   : in           bit         ;
        tclk_2_port     : inout        bit         ;
        rclk_2_port     : in           bit         ;
        sysclk          : in           bit         ;
        rfsync_2_port   : in           bit         ;
        rmsync_2_port   : in           bit         ;
        rser_2_port     : in           bit         ;
        rsig_2_port     : in           bit         ;
        tsig_3_port     : out          bit         ;
        tser_3_port     : out          bit         ;
        tmsync_3_port   : in           bit         ;
        tfsync_3_port   : in           bit         ;
        tclk_3_port     : inout        bit         ;
        rclk_3_port     : in           bit         ;
        rfsync_3_port   : in           bit         ;
        rmsync_3_port   : in           bit         ;
        rser_3_port     : in           bit         ;
        rsig_3_port     : in           bit         ;
        tsig_4_port     : out          bit         ;
        tser_4_port     : out          bit         ;
        tmsync_4_port   : in           bit         ;
        tfsync_4_port   : in           bit         ;
        tclk_4_port     : inout        bit         ;
        rclk_4_port     : in           bit         ;
        rfsync_4_port   : in           bit         ;
        rmsync_4_port   : in           bit         ;
        rser_4_port     : in           bit         ;
        rsig_4_port     : in           bit         ;
        tsig_5_port     : out          bit         ;
        tser_5_port     : out          bit         ;
        tmsync_5_port   : in           bit         ;
        tfsync_5_port   : in           bit         ;
        tclk_5_port     : inout        bit         ;
        rclk_5_port     : in           bit         ;
        rfsync_5_port   : in           bit         ;
        rmsync_5_port   : in           bit         ;
        rser_5_port     : in           bit         ;
        rsig_5_port     : in           bit         ;
        tsig_6_port     : out          bit         ;
        tser_6_port     : out          bit         ;
        tmsync_6_port   : in           bit         ;
        tfsync_6_port   : in           bit         ;
        tclk_6_port     : inout        bit         ;
        rclk_6_port     : in           bit         ;
        rfsync_6_port   : in           bit         ;
        rmsync_6_port   : in           bit         ;
        rser_6_port     : in           bit         ;
        rsig_6_port     : in           bit         ;
        vdd             : linkage      bit_vector  (0 to 16);
        tsig_7_port     : out          bit         ;
        tser_7_port     : out          bit         ;
        tmsync_7_port   : in           bit         ;
        tfsync_7_port   : in           bit         ;
        tclk_7_port     : inout        bit         ;
        rclk_7_port     : in           bit         ;
        rfsync_7_port   : in           bit         ;
        rmsync_7_port   : in           bit         ;
        rser_7_port     : in           bit         ;
        rsig_7_port     : in           bit         ;
        vss             : linkage      bit_vector  (0 to 34);
        scan_tdi        : in           bit
        ) ;

use STD_1149_1_1990.all;

attribute PIN_MAP of pm73121 : entity is PHYSICAL_PIN_MAP ;

   constant LSI_PACKAGE : PIN_MAP_STRING :=

        "scan_tdi : 165, vss : ( 15, 17, 21, 29, 44, 46, 53, 55, 59, "  &
        "60, 73, 85, 87, 88, 90, 104, 116, 119, 120, "  &
        "132, 144, 157, 164, 171, 179, 180, 189, 193, 202, "  &
        "209, 210, 222, 229, 239, 240 ),rsig_7_port : 162, "  &
        "rser_7_port : 161, rmsync_7_port : 160, rfsync_7_port : 159, "  &
        "rclk_7_port : 158, tclk_7_port : 156, tfsync_7_port : 155, "  &
        "tmsync_7_port : 154, tser_7_port : 153, tsig_7_port : 152, "  &
        "vdd : ( 1, 2, 19, 31, 48, 57, 61, 62, 92, "  &
        "93, 121, 122, 151, 181, 182, 212, 213 ),rsig_6_port : 149, 
rser_6_port : 148, "  &
        "rmsync_6_port : 147, rfsync_6_port : 146, rclk_6_port : 145, "  &
        "tclk_6_port : 143, tfsync_6_port : 142, tmsync_6_port : 141, "  &
        "tser_6_port : 140, tsig_6_port : 139, rsig_5_port : 137, "  &
        "rser_5_port : 136, rmsync_5_port : 135, rfsync_5_port : 134, "  &
        "rclk_5_port : 133, tclk_5_port : 131, tfsync_5_port : 130, "  &
        "tmsync_5_port : 129, tser_5_port : 128, tsig_5_port : 127, "  &
        "rsig_4_port : 125, rser_4_port : 124, rmsync_4_port : 123, "  &
        "rfsync_4_port : 118, rclk_4_port : 117, tclk_4_port : 115, "  &
        "tfsync_4_port : 114, tmsync_4_port : 113, tser_4_port : 112, "  &
        "tsig_4_port : 111, rsig_3_port : 109, rser_3_port : 108, "  &
        "rmsync_3_port : 107, rfsync_3_port : 106, rclk_3_port : 105, "  &
        "tclk_3_port : 103, tfsync_3_port : 102, tmsync_3_port : 101, "  &
        "tser_3_port : 100, tsig_3_port : 99, rsig_2_port : 97, "  &
        "rser_2_port : 96, rmsync_2_port : 95, rfsync_2_port : 94, "  &
        "sysclk : 89, rclk_2_port : 86, tclk_2_port : 84, "  &
        "tfsync_2_port : 83, tmsync_2_port : 82, tser_2_port : 81, "  &
        "tsig_2_port : 80, tlclk_src : 79, rsig_1_port : 78, "  &
        "rser_1_port : 77, rmsync_1_port : 76, rfsync_1_port : 75, "  &
        "rclk_1_port : 74, tclk_1_port : 72, tfsync_1_port : 71, "  &
        "tmsync_1_port : 70, tser_1_port : 69, tsig_1_port : 68, "  &
        "rsig_0_port : 66, rser_0_port : 65, rmsync_0_port : 64, "  &
        "rfsync_0_port : 63, rclk_0_port : 58, phy_en : 56, "  &
        "tclk_0_port : 54, tfsync_0_port : 52, tmsync_0_port : 51, "  &
        "tser_0_port : 50, tsig_0_port : 49, srts_line_3_port : 47, "  &
        "nclk : 45, adap_strobe : 43, srts_strobe : 42, "  &
        "srts_line_0_port : 41, srts_line_1_port : 40, srts_line_2_port : 39, 
"  &
        "srts_dout_0_port : 38, srts_dout_1_port : 37, srts_dout_2_port : 36, 
"  &
        "srts_dout_3_port : 35, txdata_0_port : 34, txdata_1_port : 33, "  &
        "txdata_2_port : 32, txdata_3_port : 30, txdata_4_port : 28, "  &
        "txdata_5_port : 27, txdata_6_port : 26, txdata_7_port : 25, "  &
        "txsoc : 24, txfull_n : 23, txenb_n : 22, "  &
        "txclk : 20, tphy_addr : 18, rxclk : 16, "  &
        "rphy_addr : 14, rxenb_n : 13, rxempty_n : 12, "  &
        "rxsoc : 11, rxdata_0_port : 10, rxdata_1_port : 9, "  &
        "rxdata_2_port : 8, rxdata_3_port : 7, rxdata_4_port : 6, "  &
        "rxdata_5_port : 5, rxdata_6_port : 4, rxdata_7_port : 3, "  &
        "pullup_disable : 238, memdata_15_port : 235, memdata_14_port : 234, "  
&
        "memdata_13_port : 233, memdata_12_port : 232, memdata_11_port : 231, 
"  &
        "memdata_10_port : 230, memdata_9_port : 228, memdata_8_port : 227, "  
&
        "memdata_7_port : 226, memdata_6_port : 225, memdata_5_port : 224, "  
&
        "memdata_4_port : 223, memdata_3_port : 221, memdata_2_port : 220, "  
&
        "memdata_1_port : 219, memdata_0_port : 218, memaddr17 : 216, "  &
        "memaddr_16_port : 215, memaddr_15_port : 214, memaddr_14_port : 211, 
"  &
        "memaddr_13_port : 208, memaddr_12_port : 207, memaddr_11_port : 206, 
"  &
        "memaddr_10_port : 205, memaddr_9_port : 204, memaddr_8_port : 203, "  
&
        "memaddr_7_port : 201, memaddr_6_port : 200, memaddr_5_port : 199, "  
&
        "memaddr_4_port : 198, memaddr_3_port : 197, memaddr_2_port : 196, "  
&
        "memaddr_1_port : 195, memaddr_0_port : 194, mem_cs_n : 192, "  &
        "mem_oe_n : 191, mem_we1_n : 190, mem_we0_n : 188, "  &
        "sp_data_en_n : 187, sp_add_en_n : 186, sp_data_dir : 185, "  &
        "oe_n : 184, reset_n : 183, sp_data_clk : 178, "  &
        "rd_n : 177, wr_n : 176, cs_n : 175, "  &
        "ack_n : 174, intr : 173, holdoff : 172, "  &
        "prmon_out : 170, scan_tck : 169, scan_tdo : 168, "  &
        "scan_trstn : 167, scan_tms : 166 ";

attribute TAP_SCAN_IN of scan_tdi : signal is true;

attribute TAP_SCAN_OUT of scan_tdo : signal is true;

attribute TAP_SCAN_MODE of scan_tms : signal is true;

attribute TAP_SCAN_RESET of scan_trstn : signal is true;

attribute TAP_SCAN_CLOCK of scan_tck : signal is ( 1.200000e+07, BOTH );


attribute INSTRUCTION_LENGTH of pm73121 : entity is 2;

attribute INSTRUCTION_OPCODE of pm73121 : entity is

        "SAMPLE (01)," &
        "BYPASS (11)," &
        "EXTEST (00)," &
        "intest (10)" ;

attribute INSTRUCTION_CAPTURE of pm73121 : entity is "01";



attribute REGISTER_ACCESS of pm73121 : entity is

"BOUNDARY (INTEST, SAMPLE, EXTEST)," &
"BYPASS (BYPASS)" ;

attribute BOUNDARY_CELLS of pm73121 : entity is "BC_4, BC_2, BC_1";
attribute BOUNDARY_LENGTH of pm73121 : entity is 225;

attribute BOUNDARY_REGISTER of pm73121 : entity is

        -- num   cell  port  function safe [ccell disval rslt]

        "0 ( BC_1, *, controlr, 1 ) ,"  &
        "1 ( BC_1, *, controlr, 1 ) ,"  &
        "2 ( BC_1, *, controlr, 1 ) ,"  &
        "3 ( BC_1, *, controlr, 1 ) ,"  &
        "4 ( BC_1, *, controlr, 1 ) ,"  &
        "5 ( BC_1, *, controlr, 1 ) ,"  &
        "6 ( BC_1, *, controlr, 1 ) ,"  &
        "7 ( BC_1, *, controlr, 1 ) ,"  &
        "8 ( BC_1, *, controlr, 1 ) ,"  &
        "9 ( BC_1, *, controlr, 1 ) ,"  &
        "10 ( BC_1, *, controlr, 1 ) ,"  &
        "11 ( BC_1, *, controlr, 1 ) ,"  &
        "12 ( BC_1, *, controlr, 1 ) ,"  &
        "13 ( BC_1, *, controlr, 1 ) ,"  &
        "14 ( BC_1, holdoff, output3, X , 0, 1, Z),"  &
        "15 ( BC_1, intr, output3, X , 0, 1, Z),"  &
        "16 ( BC_1, ack_n, output3, X , 0, 1, Z),"  &
        "17 ( BC_2, cs_n, input, X ) ,"  &
        "18 ( BC_2, wr_n, input, X ) ,"  &
        "19 ( BC_2, rd_n, input, X ) ,"  &
        "20 ( BC_1, sp_data_clk, output3, X , 0, 1, Z),"  &
        "21 ( BC_2, reset_n, input, X ) ,"  &
        "22 ( BC_2, oe_n, input, X ) ,"  &
        "23 ( BC_1, sp_data_dir, output3, X , 0, 1, Z),"  &
        "24 ( BC_1, sp_add_en_n, output3, X , 0, 1, Z),"  &
        "25 ( BC_1, sp_data_en_n, output3, X , 0, 1, Z),"  &
        "26 ( BC_1, mem_we0_n, output3, X , 0, 1, Z),"  &
        "27 ( BC_1, mem_we1_n, output3, X , 0, 1, Z),"  &
        "28 ( BC_1, mem_oe_n, output3, X , 0, 1, Z),"  &
        "29 ( BC_1, mem_cs_n, output3, X , 0, 1, Z),"  &
        "30 ( BC_1, memaddr_0_port, output3, X , 11, 1, Z),"  &
        "31 ( BC_2, memaddr_0_port, input, X ) ,"  &
        "32 ( BC_1, memaddr_1_port, output3, X , 11, 1, Z),"  &
        "33 ( BC_2, memaddr_1_port, input, X ) ,"  &
        "34 ( BC_1, memaddr_2_port, output3, X , 11, 1, Z),"  &
        "35 ( BC_2, memaddr_2_port, input, X ) ,"  &
        "36 ( BC_1, memaddr_3_port, output3, X , 11, 1, Z),"  &
        "37 ( BC_2, memaddr_3_port, input, X ) ,"  &
        "38 ( BC_1, memaddr_4_port, output3, X , 11, 1, Z),"  &
        "39 ( BC_2, memaddr_4_port, input, X ) ,"  &
        "40 ( BC_1, memaddr_5_port, output3, X , 11, 1, Z),"  &
        "41 ( BC_2, memaddr_5_port, input, X ) ,"  &
        "42 ( BC_1, memaddr_6_port, output3, X , 11, 1, Z),"  &
        "43 ( BC_2, memaddr_6_port, input, X ) ,"  &
        "44 ( BC_1, memaddr_7_port, output3, X , 11, 1, Z),"  &
        "45 ( BC_2, memaddr_7_port, input, X ) ,"  &
        "46 ( BC_1, memaddr_8_port, output3, X , 11, 1, Z),"  &
        "47 ( BC_2, memaddr_8_port, input, X ) ,"  &
        "48 ( BC_1, memaddr_9_port, output3, X , 11, 1, Z),"  &
        "49 ( BC_2, memaddr_9_port, input, X ) ,"  &
        "50 ( BC_1, memaddr_10_port, output3, X , 11, 1, Z),"  &
        "51 ( BC_2, memaddr_10_port, input, X ) ,"  &
        "52 ( BC_1, memaddr_11_port, output3, X , 11, 1, Z),"  &
        "53 ( BC_2, memaddr_11_port, input, X ) ,"  &
        "54 ( BC_1, memaddr_12_port, output3, X , 11, 1, Z),"  &
        "55 ( BC_2, memaddr_12_port, input, X ) ,"  &
        "56 ( BC_1, memaddr_13_port, output3, X , 11, 1, Z),"  &
        "57 ( BC_2, memaddr_13_port, input, X ) ,"  &
        "58 ( BC_1, memaddr_14_port, output3, X , 11, 1, Z),"  &
        "59 ( BC_2, memaddr_14_port, input, X ) ,"  &
        "60 ( BC_1, memaddr_15_port, output3, X , 11, 1, Z),"  &
        "61 ( BC_2, memaddr_15_port, input, X ) ,"  &
        "62 ( BC_1, memaddr_16_port, output3, X , 11, 1, Z),"  &
        "63 ( BC_2, memaddr_16_port, input, X ) ,"  &
        "64 ( BC_2, memaddr17, input, X ) ,"  &
        "65 ( BC_1, memdata_0_port, output3, X , 1, 1, Z),"  &
        "66 ( BC_2, memdata_0_port, input, X ) ,"  &
        "67 ( BC_1, memdata_1_port, output3, X , 1, 1, Z),"  &
        "68 ( BC_2, memdata_1_port, input, X ) ,"  &
        "69 ( BC_1, memdata_2_port, output3, X , 1, 1, Z),"  &
        "70 ( BC_2, memdata_2_port, input, X ) ,"  &
        "71 ( BC_1, memdata_3_port, output3, X , 1, 1, Z),"  &
        "72 ( BC_2, memdata_3_port, input, X ) ,"  &
        "73 ( BC_1, memdata_4_port, output3, X , 1, 1, Z),"  &
        "74 ( BC_2, memdata_4_port, input, X ) ,"  &
        "75 ( BC_1, memdata_5_port, output3, X , 1, 1, Z),"  &
        "76 ( BC_2, memdata_5_port, input, X ) ,"  &
        "77 ( BC_1, memdata_6_port, output3, X , 1, 1, Z),"  &
        "78 ( BC_2, memdata_6_port, input, X ) ,"  &
        "79 ( BC_1, memdata_7_port, output3, X , 1, 1, Z),"  &
        "80 ( BC_2, memdata_7_port, input, X ) ,"  &
        "81 ( BC_1, memdata_8_port, output3, X , 1, 1, Z),"  &
        "82 ( BC_2, memdata_8_port, input, X ) ,"  &
        "83 ( BC_1, memdata_9_port, output3, X , 1, 1, Z),"  &
        "84 ( BC_2, memdata_9_port, input, X ) ,"  &
        "85 ( BC_1, memdata_10_port, output3, X , 1, 1, Z),"  &
        "86 ( BC_2, memdata_10_port, input, X ) ,"  &
        "87 ( BC_1, memdata_11_port, output3, X , 1, 1, Z),"  &
        "88 ( BC_2, memdata_11_port, input, X ) ,"  &
        "89 ( BC_1, memdata_12_port, output3, X , 1, 1, Z),"  &
        "90 ( BC_2, memdata_12_port, input, X ) ,"  &
        "91 ( BC_1, memdata_13_port, output3, X , 1, 1, Z),"  &
        "92 ( BC_2, memdata_13_port, input, X ) ,"  &
        "93 ( BC_1, memdata_14_port, output3, X , 1, 1, Z),"  &
        "94 ( BC_2, memdata_14_port, input, X ) ,"  &
        "95 ( BC_1, memdata_15_port, output3, X , 1, 1, Z),"  &
        "96 ( BC_2, memdata_15_port, input, X ) ,"  &
        "97 ( BC_2, rxdata_7_port, input, X ) ,"  &
        "98 ( BC_2, rxdata_6_port, input, X ) ,"  &
        "99 ( BC_2, rxdata_5_port, input, X ) ,"  &
        "100 ( BC_2, rxdata_4_port, input, X ) ,"  &
        "101 ( BC_2, rxdata_3_port, input, X ) ,"  &
        "102 ( BC_2, rxdata_2_port, input, X ) ,"  &
        "103 ( BC_2, rxdata_1_port, input, X ) ,"  &
        "104 ( BC_2, rxdata_0_port, input, X ) ,"  &
        "105 ( BC_2, rxsoc, input, X ) ,"  &
        "106 ( BC_2, rxempty_n, input, X ) ,"  &
        "107 ( BC_1, rxenb_n, output3, X , 13, 1, Z),"  &
        "108 ( BC_2, rphy_addr, input, X ) ,"  &
        "109 ( BC_4, rxclk, clock, X ) ,"  &
        "110 ( BC_2, tphy_addr, input, X ) ,"  &
        "111 ( BC_4, txclk, clock, X ) ,"  &
        "112 ( BC_1, txenb_n, output3, X , 12, 1, Z),"  &
        "113 ( BC_2, txfull_n, input, X ) ,"  &
        "114 ( BC_1, txsoc, output3, X , 10, 1, Z),"  &
        "115 ( BC_1, txdata_7_port, output3, X , 10, 1, Z),"  &
        "116 ( BC_1, txdata_6_port, output3, X , 10, 1, Z),"  &
        "117 ( BC_1, txdata_5_port, output3, X , 10, 1, Z),"  &
        "118 ( BC_1, txdata_4_port, output3, X , 10, 1, Z),"  &
        "119 ( BC_1, txdata_3_port, output3, X , 10, 1, Z),"  &
        "120 ( BC_1, txdata_2_port, output3, X , 10, 1, Z),"  &
        "121 ( BC_1, txdata_1_port, output3, X , 10, 1, Z),"  &
        "122 ( BC_1, txdata_0_port, output3, X , 10, 1, Z),"  &
        "123 ( BC_1, srts_dout_3_port, output3, X , 0, 1, Z),"  &
        "124 ( BC_1, srts_dout_2_port, output3, X , 0, 1, Z),"  &
        "125 ( BC_1, srts_dout_1_port, output3, X , 0, 1, Z),"  &
        "126 ( BC_1, srts_dout_0_port, output3, X , 0, 1, Z),"  &
        "127 ( BC_1, srts_line_2_port, output3, X , 0, 1, Z),"  &
        "128 ( BC_1, srts_line_1_port, output3, X , 0, 1, Z),"  &
        "129 ( BC_1, srts_line_0_port, output3, X , 0, 1, Z),"  &
        "130 ( BC_1, srts_strobe, output3, X , 0, 1, Z),"  &
        "131 ( BC_1, adap_strobe, output3, X , 0, 1, Z),"  &
        "132 ( BC_4, nclk, clock, X ) ,"  &
        "133 ( BC_1, srts_line_3_port, output3, X , 0, 1, Z),"  &
        "134 ( BC_1, tsig_0_port, output3, X , 0, 1, Z),"  &
        "135 ( BC_1, tser_0_port, output3, X , 0, 1, Z),"  &
        "136 ( BC_2, tmsync_0_port, input, X ) ,"  &
        "137 ( BC_2, tfsync_0_port, input, X ) ,"  &
        "138 ( BC_1, tclk_0_port, output3, X , 2, 1, Z),"  &
        "139 ( BC_2, tclk_0_port, input, X ) ,"  &
        "140 ( BC_2, phy_en, input, X ) ,"  &
        "141 ( BC_4, rclk_0_port, clock, X ) ,"  &
        "142 ( BC_2, rfsync_0_port, input, X ) ,"  &
        "143 ( BC_2, rmsync_0_port, input, X ) ,"  &
        "144 ( BC_2, rser_0_port, input, X ) ,"  &
        "145 ( BC_2, rsig_0_port, input, X ) ,"  &
        "146 ( BC_1, tsig_1_port, output3, X , 0, 1, Z),"  &
        "147 ( BC_1, tser_1_port, output3, X , 0, 1, Z),"  &
        "148 ( BC_2, tmsync_1_port, input, X ) ,"  &
        "149 ( BC_2, tfsync_1_port, input, X ) ,"  &
        "150 ( BC_1, tclk_1_port, output3, X , 3, 1, Z),"  &
        "151 ( BC_2, tclk_1_port, input, X ) ,"  &
        "152 ( BC_4, rclk_1_port, clock, X ) ,"  &
        "153 ( BC_2, rfsync_1_port, input, X ) ,"  &
        "154 ( BC_2, rmsync_1_port, input, X ) ,"  &
        "155 ( BC_2, rser_1_port, input, X ) ,"  &
        "156 ( BC_2, rsig_1_port, input, X ) ,"  &
        "157 ( BC_2, tlclk_src, input, X ) ,"  &
        "158 ( BC_1, tsig_2_port, output3, X , 0, 1, Z),"  &
        "159 ( BC_1, tser_2_port, output3, X , 0, 1, Z),"  &
        "160 ( BC_2, tmsync_2_port, input, X ) ,"  &
        "161 ( BC_2, tfsync_2_port, input, X ) ,"  &
        "162 ( BC_1, tclk_2_port, output3, X , 4, 1, Z),"  &
        "163 ( BC_2, tclk_2_port, input, X ) ,"  &
        "164 ( BC_4, rclk_2_port, clock, X ) ,"  &
        "165 ( BC_4, sysclk, clock, X ) ,"  &
        "166 ( BC_2, rfsync_2_port, input, X ) ,"  &
        "167 ( BC_2, rmsync_2_port, input, X ) ,"  &
        "168 ( BC_2, rser_2_port, input, X ) ,"  &
        "169 ( BC_2, rsig_2_port, input, X ) ,"  &
        "170 ( BC_1, tsig_3_port, output3, X , 0, 1, Z),"  &
        "171 ( BC_1, tser_3_port, output3, X , 0, 1, Z),"  &
        "172 ( BC_2, tmsync_3_port, input, X ) ,"  &
        "173 ( BC_2, tfsync_3_port, input, X ) ,"  &
        "174 ( BC_1, tclk_3_port, output3, X , 5, 1, Z),"  &
        "175 ( BC_2, tclk_3_port, input, X ) ,"  &
        "176 ( BC_4, rclk_3_port, clock, X ) ,"  &
        "177 ( BC_2, rfsync_3_port, input, X ) ,"  &
        "178 ( BC_2, rmsync_3_port, input, X ) ,"  &
        "179 ( BC_2, rser_3_port, input, X ) ,"  &
        "180 ( BC_2, rsig_3_port, input, X ) ,"  &
        "181 ( BC_1, tsig_4_port, output3, X , 0, 1, Z),"  &
        "182 ( BC_1, tser_4_port, output3, X , 0, 1, Z),"  &
        "183 ( BC_2, tmsync_4_port, input, X ) ,"  &
        "184 ( BC_2, tfsync_4_port, input, X ) ,"  &
        "185 ( BC_1, tclk_4_port, output3, X , 6, 1, Z),"  &
        "186 ( BC_2, tclk_4_port, input, X ) ,"  &
        "187 ( BC_4, rclk_4_port, clock, X ) ,"  &
        "188 ( BC_2, rfsync_4_port, input, X ) ,"  &
        "189 ( BC_2, rmsync_4_port, input, X ) ,"  &
        "190 ( BC_2, rser_4_port, input, X ) ,"  &
        "191 ( BC_2, rsig_4_port, input, X ) ,"  &
        "192 ( BC_1, tsig_5_port, output3, X , 0, 1, Z),"  &
        "193 ( BC_1, tser_5_port, output3, X , 0, 1, Z),"  &
        "194 ( BC_2, tmsync_5_port, input, X ) ,"  &
        "195 ( BC_2, tfsync_5_port, input, X ) ,"  &
        "196 ( BC_1, tclk_5_port, output3, X , 7, 1, Z),"  &
        "197 ( BC_2, tclk_5_port, input, X ) ,"  &
        "198 ( BC_4, rclk_5_port, clock, X ) ,"  &
        "199 ( BC_2, rfsync_5_port, input, X ) ,"  &
        "200 ( BC_2, rmsync_5_port, input, X ) ,"  &
        "201 ( BC_2, rser_5_port, input, X ) ,"  &
        "202 ( BC_2, rsig_5_port, input, X ) ,"  &
        "203 ( BC_1, tsig_6_port, output3, X , 0, 1, Z),"  &
        "204 ( BC_1, tser_6_port, output3, X , 0, 1, Z),"  &
        "205 ( BC_2, tmsync_6_port, input, X ) ,"  &
        "206 ( BC_2, tfsync_6_port, input, X ) ,"  &
        "207 ( BC_1, tclk_6_port, output3, X , 8, 1, Z),"  &
        "208 ( BC_2, tclk_6_port, input, X ) ,"  &
        "209 ( BC_4, rclk_6_port, clock, X ) ,"  &
        "210 ( BC_2, rfsync_6_port, input, X ) ,"  &
        "211 ( BC_2, rmsync_6_port, input, X ) ,"  &
        "212 ( BC_2, rser_6_port, input, X ) ,"  &
        "213 ( BC_2, rsig_6_port, input, X ) ,"  &
        "214 ( BC_1, tsig_7_port, output3, X , 0, 1, Z),"  &
        "215 ( BC_1, tser_7_port, output3, X , 0, 1, Z),"  &
        "216 ( BC_2, tmsync_7_port, input, X ) ,"  &
        "217 ( BC_2, tfsync_7_port, input, X ) ,"  &
        "218 ( BC_1, tclk_7_port, output3, X , 9, 1, Z),"  &
        "219 ( BC_2, tclk_7_port, input, X ) ,"  &
        "220 ( BC_4, rclk_7_port, clock, X ) ,"  &
        "221 ( BC_2, rfsync_7_port, input, X ) ,"  &
        "222 ( BC_2, rmsync_7_port, input, X ) ,"  &
        "223 ( BC_2, rser_7_port, input, X ) ,"  &
        "224 ( BC_2, rsig_7_port, input, X ) ";


end pm73121;