-- *****************************************************************************
-- BSDL file for design AD6624A
-- Created by Synopsys Version 1999.05 (Dec 18, 1998)
-- Designer: Bert Marston
-- Company: QSI
-- Date: Fri Jan 14 09:42:16 2000
-- *****************************************************************************
entity AD6624A is
-- This section identifies the default device package selected.
generic (PHYSICAL_PIN_MAP: string:= "AD6624A");
-- This section declares all the ports in the design.
port (
A0 : in bit;
A1 : in bit;
A2 : in bit;
CHIP_ID0 : in bit;
CHIP_ID1 : in bit;
CHIP_ID2 : in bit;
CHIP_ID3 : in bit;
CLK : in bit;
EXPA0 : in bit;
EXPA1 : in bit;
EXPA2 : in bit;
EXPB0 : in bit;
EXPB1 : in bit;
EXPB2 : in bit;
IENA : in bit;
IENB : in bit;
INA0 : in bit;
INA1 : in bit;
INA10 : in bit;
INA11 : in bit;
INA12 : in bit;
INA13 : in bit;
INA2 : in bit;
INA3 : in bit;
INA4 : in bit;
INA5 : in bit;
INA6 : in bit;
INA7 : in bit;
INA8 : in bit;
INA9 : in bit;
INB0 : in bit;
INB1 : in bit;
INB10 : in bit;
INB11 : in bit;
INB12 : in bit;
INB13 : in bit;
INB2 : in bit;
INB3 : in bit;
INB4 : in bit;
INB5 : in bit;
INB6 : in bit;
INB7 : in bit;
INB8 : in bit;
INB9 : in bit;
MODE : in bit;
R_W : in bit;
SBM0 : in bit;
SDIN0 : in bit;
SDIN1 : in bit;
SDIN2 : in bit;
SDIN3 : in bit;
SDIV0 : in bit;
SDIV1 : in bit;
SDIV2 : in bit;
SDIV3 : in bit;
SYNCA : in bit;
SYNCB : in bit;
SYNCC : in bit;
SYNCD : in bit;
TCLK : in bit;
TDI : in bit;
TMS : in bit;
CS : in bit;
DS : in bit;
RESET : in bit;
TRST : in bit;
D0 : inout bit;
D1 : inout bit;
D2 : inout bit;
D3 : inout bit;
D4 : inout bit;
D5 : inout bit;
D6 : inout bit;
D7 : inout bit;
SCLK0 : inout bit;
SCLK1 : inout bit;
SCLK2 : inout bit;
SCLK3 : inout bit;
SDFS0 : inout bit;
SDFS1 : inout bit;
SDFS2 : inout bit;
SDFS3 : inout bit;
SDO0 : out bit;
SDO1 : out bit;
SDO2 : out bit;
SDO3 : out bit;
TDO : out bit;
DTACK : out bit;
LIA_A : buffer bit;
LIA_B : buffer bit;
LIB_A : buffer bit;
LIB_B : buffer bit;
SDFE0 : buffer bit;
SDFE1 : buffer bit;
SDFE2 : buffer bit;
SDFE3 : buffer bit;
DR0 : buffer bit;
DR1 : buffer bit;
DR2 : buffer bit;
DR3 : buffer bit;
VDDCORE : linkage bit_vector (1 to 10); -- VDD
VDDRING : linkage bit_vector (1 to 10); -- VDDIO
vssCORE : linkage bit_vector (1 to 8); -- GND corresponding to VDD
VSSRING : linkage bit_vector (1 to 8) -- GND corresponding to VDDIO
);
use STD_1149_1_1994.all;
attribute COMPONENT_CONFORMANCE of AD6624A: entity is "STD_1149_1_1993";
attribute PIN_MAP of AD6624A: entity is PHYSICAL_PIN_MAP;
-- This section specifies the pin map for each port. This information
-- is extracted from the port-to-pin map file that was read in using
-- the "read_pin_map" command.
constant AD6624A: PIN_MAP_STRING :=
"A0 : M10," &
"A1 : P11," &
"A2 : N10," &
"CHIP_ID0 : K14," &
"CHIP_ID1 : K12," &
"CHIP_ID2 : L14," &
"CHIP_ID3 : K13," &
"CLK : E1," &
"EXPA0 : F2," &
"EXPA1 : F1," &
"EXPA2 : F3," &
"EXPB0 : A8," &
"EXPB1 : A7," &
"EXPB2 : C8," &
"IENA : M1," &
"IENB : E2," &
"INA0 : K3," &
"INA1 : L1," &
"INA10 : G3," &
"INA11 : H1," &
"INA12 : G1," &
"INA13 : G2," &
"INA2 : K2," &
"INA3 : L3," &
"INA4 : J3," &
"INA5 : K1," &
"INA6 : J2," &
"INA7 : H3," &
"INA8 : J1," &
"INA9 : H2," &
"INB0 : D3," &
"INB1 : C1," &
"INB10 : B6," &
"INB11 : C7," &
"INB12 : A6," &
"INB13 : B7," &
"INB2 : D2," &
"INB3 : B1," &
"INB4 : B4," &
"INB5 : A3," &
"INB6 : A4," &
"INB7 : B5," &
"INB8 : C4," &
"INB9 : C6," &
"MODE : M11," &
"R_W : P10," &
"SBM0 : J13," &
"SDIN0 : F14," &
"SDIN1 : D14," &
"SDIN2 : C11," &
"SDIN3 : A9," &
"SDIV0 : H14," &
"SDIV1 : H13," &
"SDIV2 : J12," &
"SDIV3 : J14," &
"SYNCA : M5," &
"SYNCB : P4," &
"SYNCC : N5," &
"SYNCD : M4," &
"TCLK : N14," &
"TDI : L12," &
"TMS : L13," &
"CS : N11," &
"DS : M8," &
"RESET : P5," &
"TRST : M12," &
"D0 : P9," &
"D1 : N8," &
"D2 : M7," &
"D3 : P8," &
"D4 : N7," &
"D5 : M6," &
"D6 : P6," &
"D7 : N6," &
"SCLK0 : G14," &
"SCLK1 : F12," &
"SCLK2 : C12," &
"SCLK3 : C10," &
"SDFS0 : H12," &
"SDFS1 : D12," &
"SDFS2 : A13," &
"SDFS3 : A10," &
"SDO0 : G13," &
"SDO1 : E13," &
"SDO2 : B11," &
"SDO3 : B9," &
"TDO : M14," &
"DTACK : N9," &
"LIA_A : N4," &
"LIA_B : P2," &
"LIB_A : E3," &
"LIB_B : D1," &
"SDFE0 : G12," &
"SDFE1 : C14," &
"SDFE2 : B10," &
"SDFE3 : C9," &
"DR0 : F13," &
"DR1 : D13," &
"DR2 : A11," &
"DR3 : B8," &
"VDDCORE : (E6, E8, E10, F5, G10, H5, J10, K5, K7, K9)," & -- VDD
"VDDRING : (E5, E7, E9, F10, G5, H10, J5, K6, K8, K10)," & -- VDDIO
"VSSCORE : (F6, F7, F8, F9, G6, G7, G8, G9),"& -- GND corresponding to VDD
"VSSRING : (H6, H7, H8, H9, J6, J7, J8, J9)"; -- GND corresponding to VDDIO
-- This section specifies the TAP ports.
-- For the TAP TCK port, the parameters in the brackets are:
-- First Field : Maximum TCK frequency.
-- Second Field: Allowable states TCK may be stopped in.
attribute TAP_SCAN_CLOCK of TCLK : signal is (1.000000e+07, BOTH);
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_RESET of TRST : signal is true;
-- Specifies the number of bits in the instruction register.
attribute INSTRUCTION_LENGTH of AD6624A: entity is 3;
-- Specifies the boundary-scan instructions implemented in the
-- design and their opcodes.
attribute INSTRUCTION_OPCODE of AD6624A: entity is
"BYPASS (111)," &
"EXTEST (000)," &
"SAMPLE (010)," &
"HIGHZ (011)," &
"CLAMP (100)," &
"IDCODE (001)";
-- Specifies the bit pattern that is loaded into the instruction
-- register when the TAP controller passes through the Capture-IR
-- state. The standard mandates that the two LSBs must be "01".
-- The remaining bits are design specific.
attribute INSTRUCTION_CAPTURE of AD6624A: entity is "001";
-- Specifies the bit pattern that is loaded into the DEVICE_ID
-- register during the IDCODE instruction when the TAP controller
-- passes through the Capture-DR state.
attribute IDCODE_REGISTER of AD6624A: entity is
"0001" & -- 4-bit version number
"0010011110001100" & -- 16-bit part number 0x278C
"00011100101" & -- 11-bit identity of the manufacturer
"1"; -- Required by IEEE Std 1149.1
-- This section specifies the test data register placed between TDI
-- and TDO for each implemented instruction.
attribute REGISTER_ACCESS of AD6624A: entity is
"BYPASS (BYPASS, HIGHZ, CLAMP)," &
"BOUNDARY (EXTEST, SAMPLE)," &
"DEVICE_ID (IDCODE)";
-- Specifies the length of the boundary scan register.
attribute BOUNDARY_LENGTH of AD6624A: entity is 124;
-- The following list specifies the characteristics of each cell
-- in the boundary scan register from TDI to TDO.
-- The following is a description of the label fields:
-- num : Is the cell number.
-- cell : Is the cell type as defined by the standard.
-- port : Is the design port name. Control cells do not
-- have a port name.
-- function: Is the function of the cell as defined by the
-- standard. Is one of input, output2, output3,
-- bidir, control or controlr.
-- safe : Specifies the value that the BSR cell should be
-- loaded with for safe operation when the software
-- might otherwise choose a random value.
-- ccell : The control cell number. Specifies the control
-- cell that drives the output enable for this port.
-- disval : Specifies the value that is loaded into the
-- control cell to disable the output enable for
-- the corresponding port.
-- rslt : Resulting state. Shows the state of the driver
-- when it is disabled.
attribute BOUNDARY_REGISTER of AD6624A: entity is
--
-- num cell port function safe [ccell disval rslt]
--
"123 (BC_4, CHIP_ID3, observe_only, X), " &
"122 (BC_4, CHIP_ID2, observe_only, X), " &
"121 (BC_4, CHIP_ID1, observe_only, X), " &
"120 (BC_4, CHIP_ID0, observe_only, X), " &
"119 (BC_4, SBM0, observe_only, X), " &
"118 (BC_4, SDIV3, observe_only, X), " &
"117 (BC_4, SDIV2, observe_only, X), " &
"116 (BC_4, SDIV1, observe_only, X), " &
"115 (BC_4, SDIV0, observe_only, X), " &
"114 (BC_4, SCLK0, observe_only, X), " &
"113 (BC_1, SCLK0, output3, X, 112, 1, PULL0)," &
"112 (BC_1, *, control, 1), " &
"111 (BC_4, SDFS0, observe_only, X), " &
"110 (BC_1, SDFS0, output3, X, 109, 1, PULL0)," &
"109 (BC_1, *, control, 1), " &
"108 (BC_1, SDO0, output3, X, 107, 1, PULL0)," &
"107 (BC_1, *, control, 1), " &
"106 (BC_4, SDIN0, observe_only, X), " &
"105 (BC_1, SDFE0, output2, X), " &
"104 (BC_1, DR0, output2, X), " &
"103 (BC_4, SCLK1, observe_only, X), " &
"102 (BC_1, SCLK1, output3, X, 101, 1, PULL0)," &
"101 (BC_1, *, control, 1), " &
"100 (BC_4, SDFS1, observe_only, X), " &
"99 (BC_1, SDFS1, output3, X, 98, 1, PULL0)," &
"98 (BC_1, *, control, 1), " &
"97 (BC_1, SDO1, output3, X, 96, 1, PULL0)," &
"96 (BC_1, *, control, 1), " &
"95 (BC_4, SDIN1, observe_only, X), " &
"94 (BC_1, SDFE1, output2, X), " &
"93 (BC_1, DR1, output2, X), " &
"92 (BC_4, SCLK2, observe_only, X), " &
"91 (BC_1, SCLK2, output3, X, 90, 1, PULL0)," &
"90 (BC_1, *, control, 1), " &
"89 (BC_4, SDFS2, observe_only, X), " &
"88 (BC_1, SDFS2, output3, X, 87, 1, PULL0)," &
"87 (BC_1, *, control, 1), " &
"86 (BC_1, SDO2, output3, X, 85, 1, PULL0)," &
"85 (BC_1, *, control, 1), " &
"84 (BC_4, SDIN2, observe_only, X), " &
"83 (BC_1, SDFE2, output2, X), " &
"82 (BC_1, DR2, output2, X), " &
"81 (BC_4, SCLK3, observe_only, X), " &
"80 (BC_1, SCLK3, output3, X, 79, 1, PULL0)," &
"79 (BC_1, *, control, 1), " &
"78 (BC_4, SDFS3, observe_only, X), " &
"77 (BC_1, SDFS3, output3, X, 76, 1, PULL0)," &
"76 (BC_1, *, control, 1), " &
"75 (BC_1, SDO3, output3, X, 74, 1, PULL0)," &
"74 (BC_1, *, control, 1), " &
"73 (BC_4, SDIN3, observe_only, X), " &
"72 (BC_1, SDFE3, output2, X), " &
"71 (BC_1, DR3, output2, X), " &
"70 (BC_4, EXPB0, observe_only, X), " &
"69 (BC_4, EXPB1, observe_only, X), " &
"68 (BC_4, EXPB2, observe_only, X), " &
"67 (BC_4, INB13, observe_only, X), " &
"66 (BC_4, INB12, observe_only, X), " &
"65 (BC_4, INB11, observe_only, X), " &
"64 (BC_4, INB10, observe_only, X), " &
"63 (BC_4, INB9, observe_only, X), " &
"62 (BC_4, INB8, observe_only, X), " &
"61 (BC_4, INB7, observe_only, X), " &
"60 (BC_4, INB6, observe_only, X), " &
"59 (BC_4, INB5, observe_only, X), " &
"58 (BC_4, INB4, observe_only, X), " &
"57 (BC_4, INB3, observe_only, X), " &
"56 (BC_4, INB2, observe_only, X), " &
"55 (BC_4, INB1, observe_only, X), " &
"54 (BC_4, INB0, observe_only, X), " &
"53 (BC_4, IENB, observe_only, X), " &
"52 (BC_1, LIB_B, output2, X), " &
"51 (BC_1, LIB_A, output2, X), " &
"50 (BC_4, CLK, clock, X), " &
"49 (BC_4, EXPA0, observe_only, X), " &
"48 (BC_4, EXPA1, observe_only, X), " &
"47 (BC_4, EXPA2, observe_only, X), " &
"46 (BC_4, INA13, observe_only, X), " &
"45 (BC_4, INA12, observe_only, X), " &
"44 (BC_4, INA11, observe_only, X), " &
"43 (BC_4, INA10, observe_only, X), " &
"42 (BC_4, INA9, observe_only, X), " &
"41 (BC_4, INA8, observe_only, X), " &
"40 (BC_4, INA7, observe_only, X), " &
"39 (BC_4, INA6, observe_only, X), " &
"38 (BC_4, INA5, observe_only, X), " &
"37 (BC_4, INA4, observe_only, X), " &
"36 (BC_4, INA3, observe_only, X), " &
"35 (BC_4, INA2, observe_only, X), " &
"34 (BC_4, INA1, observe_only, X), " &
"33 (BC_4, INA0, observe_only, X), " &
"32 (BC_4, IENA, observe_only, X), " &
"31 (BC_1, LIA_B, output2, X), " &
"30 (BC_1, LIA_A, output2, X), " &
"29 (BC_4, SYNCD, observe_only, X), " &
"28 (BC_4, SYNCC, observe_only, X), " &
"27 (BC_4, SYNCB, observe_only, X), " &
"26 (BC_4, SYNCA, observe_only, X), " &
"25 (BC_4, RESET, observe_only, X), " &
"24 (BC_4, D7, observe_only, X), " &
"23 (BC_1, D7, output3, X, 8, 1, Z), " &
"22 (BC_4, D6, observe_only, X), " &
"21 (BC_1, D6, output3, X, 8, 1, Z), " &
"20 (BC_4, D5, observe_only, X), " &
"19 (BC_1, D5, output3, X, 8, 1, Z), " &
"18 (BC_4, D4, observe_only, X), " &
"17 (BC_1, D4, output3, X, 8, 1, Z), " &
"16 (BC_4, D3, observe_only, X), " &
"15 (BC_1, D3, output3, X, 8, 1, Z), " &
"14 (BC_4, D2, observe_only, X), " &
"13 (BC_1, D2, output3, X, 8, 1, Z), " &
"12 (BC_4, D1, observe_only, X), " &
"11 (BC_1, D1, output3, X, 8, 1, Z), " &
"10 (BC_4, D0, observe_only, X), " &
"9 (BC_1, D0, output3, X, 8, 1, Z), " &
"8 (BC_1, *, control, 1), " &
"7 (BC_4, DS, observe_only, X), " &
"6 (BC_1, DTACK, output2, 1), " &
"5 (BC_4, R_W, observe_only, X), " &
"4 (BC_4, MODE, observe_only, X), " &
"3 (BC_4, A2, observe_only, X), " &
"2 (BC_4, A1, observe_only, X), " &
"1 (BC_4, A0, observe_only, X), " &
"0 (BC_4, CS, observe_only, X) ";
end AD6624A;
