--*******************************************************************************************************
--** Copyright (c) 2000 Cypress Semiconductor
--** All rights reserved.
--**
--** File Name: 1354BV25_x36_165.bsdl
--** Release: 1.1
--** Last Updated: February, 25 2004
--** Function: 256K x36 NoBL Pipelined SRAM, BSDL file for JTAG
--** Part #: CY7C1354BV25
--** Notes: IMPORTANT NOTE: Please be aware that the CY7C1354BV25 device is NOT IEEE
--** 1149.1 compliant.
--** Ref CY7C1354BV25 Datasheet at www.cypress.com/sram/datasheets.html
--** Queries ? :contact Cypress MPD Applications
--** Written by : Cypress MPD Applications
--*******************************************************************************************************
entity CY7C1354BV25_165 is
generic (PHYSICAL_PIN_MAP : string := "FBGA");
port (
A: in bit_vector(0 to 17);
ADV_b: in bit;
BWA_b: in bit;
BWB_b: in bit;
BWC_b: in bit;
BWD_b: in bit;
CE1_b: in bit;
CE2: in bit;
CE3_b: in bit;
CEN_b: in bit;
CLK: in bit;
DQ_A: in bit_vector(0 to 7);
DQ_Pa: in bit;
DQ_B: in bit_vector(0 to 7);
DQ_Pb: in bit;
DQ_C: in bit_vector(0 to 7);
DQ_Pc: in bit;
DQ_D: in bit_vector(0 to 7);
DQ_Pd: in bit;
OE_b: in bit;
MODE: in bit;
WE_b: in bit;
TMS: in bit;
TDI: in bit;
TCK: in bit;
TDO: out bit;
ZZ: in bit;
VDD: linkage bit_vector(0 to 17);
VSS: linkage bit_vector(0 to 33);
VDDQ: linkage bit_vector(0 to 19);
NC: linkage bit_vector(0 to 20)
);
use STD_1149_1_1994.all;
attribute COMPONENT_CONFORMANCE of CY7C1354BV25_165 : entity is
"STD_1149_1_1993";
attribute PIN_MAP of CY7C1354BV25_165 : entity is PHYSICAL_PIN_MAP;
constant FBGA:PIN_MAP_STRING:=
"A:(R6,P6,A9,B10,A10,R11,R10,P10,R9,P9,R8,P8, " &
"R4,P4,R3,P3,B2,A2), " &--Address
"ADV_b: A8, " &
"BWA_b: B5, " &
"BWB_b: A5, " &
"BWC_b: A4, " &
"BWD_b: B4, " & -- Byte Write
"CEN_b: A7, " &
"CE1_b: A3, " &
"CE2: B3, " &
"CE3_b: A6, " &
"CLK: B6, " & -- Clock
"DQ_A: (J10,K10,L10,M10,J11,K11,L11,M11), " &
"DQ_Pa: N11," &
"DQ_B: (E10,F10,G10,D10,D11,E11,F11,G11), " &
"DQ_Pb: C11," &
"DQ_C: (G2,F2,E2,D2,G1,F1,E1,D1), " &
"DQ_Pc: C1," &
"DQ_D: (L2,K2,J2,M2,M1,L1,K1,J1), " &
"DQ_Pd: N1," &
"WE_b: B7," &
"OE_b: B8," &
"MODE: R1," &
"TMS: R5," &
"TDI: P5," &
"TCK: R7," &
"TDO: P7," &
"VDD: (D4,D8,E4,E8,F4,F8,G4,G8,H4,H8, " &
"J4,J8,K4,K8,L4,L8,M4,M8), " &
"VDDQ: (C3,C9,D3,D9,E3,E9,F3,F9,G3,G9," &
"J3,J9,K3,K9,L3,L9,M3,M9,N3,N9)," &
"VSS: (C4,C5,C6,C7,C8,D5,D6,D7,E5,E6,E7," &
"F5,F6,F7,G5,G6,G7,H5,H6,H7,J5,J6,"&
"J7,K5,K6,K7,L5,L6,L7,M5,M6,M7,N4,N8), " &
"ZZ: H11, " &
"NC: (A1,A11,B1,B9,B11,C2,C10,H1,H2," &
"H3,H9,H10,N2,N5,N6,N7,N10,P1,P2,P11,R2) ";
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_CLOCK of TCK : signal is (50.0e6, BOTH);
attribute INSTRUCTION_LENGTH of CY7C1354BV25_165 : entity is 3;
attribute INSTRUCTION_OPCODE of CY7C1354BV25_165 : entity is
"EXTEST (000)," &
"IDCODE (001)," &
"SAMPLE (010)," & -- Sample-Z
"SAMPLD (100)," & -- Sample/Preload
"BYPASS (111) ";
attribute INSTRUCTION_CAPTURE of CY7C1354BV25_165 : entity is "001";
attribute IDCODE_REGISTER of CY7C1354BV25_165 : entity is
"001" & -- Reserved for version number
"01011001000100110" & -- Defines the type of SRAM
"00000110100" & -- Manufacturer identity
"1"; -- ID register Presence indicator
attribute REGISTER_ACCESS of CY7C1354BV25_165 : entity is
"BOUNDARY (EXTEST,SAMPLE,SAMPLD)," &
"BYPASS (BYPASS)";
attribute BOUNDARY_LENGTH of CY7C1354BV25_165 : entity is 69;
attribute BOUNDARY_REGISTER of CY7C1354BV25_165 : entity is
"0 (BC_4, CLK, input, X)," &
"1 (BC_4, WE_b, input, X)," &
"2 (BC_4, CEN_b, input, X)," &
"3 (BC_4, OE_b, input, X)," &
"4 (BC_4, ADV_b, input, X)," &
"5 (BC_4, A(2), input, X)," &
"6 (BC_4, A(3), input, X)," &
"7 (BC_4, A(4), input, X)," &
"8 (BC_4, DQ_Pb, input, X)," &
"9 (BC_4, DQ_b(0), input, X)," &
"10 (BC_4, DQ_b(1), input, X)," &
"11 (BC_4, DQ_b(2), input, X)," &
"12 (BC_4, DQ_b(3), input, X)," &
"13 (BC_4, DQ_b(4), input, X)," &
"14 (BC_4, DQ_b(5), input, X)," &
"15 (BC_4, DQ_b(6), input, X)," &
"16 (BC_4, DQ_b(7), input, X)," &
"17 (BC_4, ZZ, input, X)," &
"18 (BC_4, DQ_a(0), input, X)," &
"19 (BC_4, DQ_a(1), input, X)," &
"20 (BC_4, DQ_a(2), input, X)," &
"21 (BC_4, DQ_a(3), input, X)," &
"22 (BC_4, DQ_a(4), input, X)," &
"23 (BC_4, DQ_a(5), input, X)," &
"24 (BC_4, DQ_a(6), input, X)," &
"25 (BC_4, DQ_a(7), input, X)," &
"26 (BC_4, DQ_Pa, input, X)," &
"27 (BC_4, A(5), input, X)," &
"28 (BC_4, A(6), input, X)," &
"29 (BC_4, A(7), input, X)," &
"30 (BC_4, A(8), input, X)," &
"31 (BC_4, A(9), input, X)," &
"32 (BC_4, A(10), input, X)," &
"33 (BC_4, A(11), input, X)," &
"34 (BC_4, A(0), input, X)," &
"35 (BC_4, A(1), input, X)," &
"36 (BC_4, A(12), input, X)," &
"37 (BC_4, A(13), input, X)," &
"38 (BC_4, A(14), input, X)," &
"39 (BC_4, A(15), input, X)," &
"40 (BC_4, MODE, input, X)," &
"41 (BC_4, DQ_Pd, input, X)," &
"42 (BC_4, DQ_d(0), input, X)," &
"43 (BC_4, DQ_d(1), input, X)," &
"44 (BC_4, DQ_d(2), input, X)," &
"45 (BC_4, DQ_d(3), input, X)," &
"46 (BC_4, DQ_d(4), input, X)," &
"47 (BC_4, DQ_d(5), input, X)," &
"48 (BC_4, DQ_d(6), input, X)," &
"49 (BC_4, DQ_d(7), input, X)," &
"50 (BC_4, *, internal, X)," &
"51 (BC_4, DQ_c(0), input, X)," &
"52 (BC_4, DQ_c(1), input, X)," &
"53 (BC_4, DQ_c(2), input, X)," &
"54 (BC_4, DQ_c(3), input, X)," &
"55 (BC_4, DQ_c(4), input, X)," &
"56 (BC_4, DQ_c(5), input, X)," &
"57 (BC_4, DQ_c(6), input, X)," &
"58 (BC_4, DQ_c(7), input, X)," &
"59 (BC_4, DQ_Pc, input, X)," &
"60 (BC_4, A(16), input, X)," &
"61 (BC_4, A(17), input, X)," &
"62 (BC_4, CE1_b, input, X)," &
"63 (BC_4, CE2, input, X)," &
"64 (BC_4, BWD_b, input, X)," &
"65 (BC_4, BWC_b, input, X)," &
"66 (BC_4, BWB_b, input, X)," &
"67 (BC_4, BWA_b, input, X)," &
"68 (BC_4, CE3_b, input, X)";
end CY7C1354BV25_165 ;