BSDL Files Library for JTAG

The only free public library that contains thousands of BSDL (Boundary Scan Description Language) models to use with BScan/JTAG tools

BSDL model: ZL30314


-- **********************************************************************
--
--  FILE :  zl30314gkg.bsd
--  generated by Cz.P. as zl30314 on Sat Sep 22 17:26:41 EDT 2007
--  using p.jtag.bsd rev 3.5 - 9 May, 2007
--
--  BSDL description for top level entity zl30314
--  Device : ZL30314  Sync Ethernet and Network Synchronizer
--  Package : 256-TEPBGA 17x17mm
-- 
--  Number of BSC cells: 160
-- 
-- **********************************************************************
--  Modification History:
--       Initial release:   Sat Sep 22 17:26:41 EDT 2007
-- **********************************************************************
--
--                        IMPORTANT NOTICE
--
--  This information is for modeling purposes only, and is not guaranteed.
--
--  This information is provided "as is" without warranty of any kind.
--  It may contain technical inaccuracies or typographical errors.
--
--  ZARLINK and ZL30314 are trademarks of ZARLINK Semiconductor. ZARLINK
--  products, marketed under trademarks, are protected under numerous US
--  and foreign patents and pending applications,  maskwork rights,  and
--  copyrights.
--
--  ZARLINK reserves the right to make changes to any products and 
--  services at any time without notice.  ZARLINK assumes no
--  responsibility or liability arising out of the application or use of
--  any information, product, or service described herein except as
--  expressly agreed to in writing by ZARLINK Corporation. ZARLINK 
--  customers are advised to obtain the latest version of device 
--  specifications before relying on any published information and before
--  placing orders for products or services.
--
--  ======================================================================
--  This BSDL model has been validated for syntax and semantics compliance
--  to IEEE 1149.1 using ASSET/Agilent BSDL Validation Service.
--  ======================================================================
--

--  ********************************************************************
--
--                             SPECIAL NOTES
--
--    1. All instruction opcodes other than those defined in this file
--       should be considered PRIVATE.
--
--  ********************************************************************



entity zl30314 is

  generic(PHYSICAL_PIN_MAP : string := "BGA314_PACKAGE");

port (
      	CS_B: in bit;
      	DPLL2_IN_REF: out bit;
     	ETH_CLK0: out bit;
      	ETH_CLK1: out bit;
      	ETH_FILTER: linkage bit;
     	FILTER_REF0: linkage bit;
      	FILTER_REF1: linkage bit;
     	IC_GND1: linkage bit;
      	IC_GND2: linkage bit;
      	IC_OPEN: linkage bit_vector (1 to 12);
      	INT0_B: out bit;
      	INT1_B: out bit;
      	M1_COL: in bit;
      	M1_CRS: inout bit;
      	M1_GTX_CLK: out bit;
      	M1_MDC: inout bit;
      	M1_MDIO: inout bit;
      	M1_REFCLK: in bit;
      	M1_RXCLK: in bit;
      	M1_RXD: in bit_vector (0 to 7);
      	M1_RXDV: in bit;
      	M1_RXER: in bit;
      	M1_TXCLK: inout bit;
      	M1_TXD: buffer bit_vector (0 to 7);
      	M1_TXEN: buffer bit;
      	M1_TXER: buffer bit;
      	M2_COL: in bit;
      	M2_CRS: inout bit;
      	M2_GTX_CLK: out bit;
      	M2_MDC: inout bit;
      	M2_MDIO: inout bit;
      	M2_REFCLK: in bit;
      	M2_RXCLK: in bit;
      	M2_RXD: in bit_vector (0 to 7);
      	M2_RXDV: in bit;
      	M2_RXER: in bit;
      	M2_TXCLK: inout bit;
      	M2_TXD: buffer bit_vector (0 to 7);
      	M2_TXEN: buffer bit;
      	M2_TXER: buffer bit;
      	NC: linkage bit_vector (1 to 58);
      	ONE_PPS_OUT: out bit;
      	OSC_I: linkage bit;
      	OSC_O: linkage bit;
     	P0_CLK0: out bit;
      	P0_CLK1: out bit;
     	P0_FP0: out bit;
      	P0_FP1: out bit;
     	P1_CLK0: out bit;
      	P1_CLK1: out bit;
      	PHY_RST_B: buffer bit;
      	REF: in bit_vector (0 to 7);
      	RST_B: in bit;
      	SCK: inout bit;
      	SI: inout bit;
      	SO: out bit;
      	SYNC: in bit_vector (0 to 2);
      	TCK: in bit;
      	TDI: in bit;
      	TDO: out bit;
      	TMS: in bit;
      	TRST_B: in bit;
      	AVDD18A: linkage bit_vector (1 to 4);
      	AVDD33A: linkage bit_vector (1 to 2);
      	AVSS: linkage bit_vector (1 to 6);
      	VDD18CORE: linkage bit_vector (1 to 9);
      	VDD33IO: linkage bit_vector (1 to 15);
      	VSS: linkage bit_vector (1 to 53)
);

 

  use STD_1149_1_2001.all;

  attribute COMPONENT_CONFORMANCE of zl30314 : entity is
        "STD_1149_1_2001";

  attribute PIN_MAP of zl30314 : entity is PHYSICAL_PIN_MAP;
  constant BGA314_PACKAGE : PIN_MAP_STRING :=
  "CS_B             : R11      , " &  
  "DPLL2_IN_REF     : T1       , " &  
  "ETH_CLK0         : A5       , " &  
  "ETH_CLK1         : A8       , " &  
  "ETH_FILTER       : D1       , " &  
  "FILTER_REF0      : D2       , " &  
  "FILTER_REF1      : D3       , " &  
  "IC_GND1          : P14      , " &  
  "IC_GND2          : E14      , " &  
  "IC_OPEN          :(C16      , " & -- IC_OPEN[1]      
                     "A6       , " & -- IC_OPEN[2]      
                     "A7       , " & -- IC_OPEN[3]      
                     "A10      , " & -- IC_OPEN[4]      
                     "J1       , " & -- IC_OPEN[5]      
                     "J2       , " & -- IC_OPEN[6]      
                     "P11      , " & -- IC_OPEN[7]      
                     "N12      , " & -- IC_OPEN[8]      
                     "M6       , " & -- IC_OPEN[9]      
                     "M7       , " & -- IC_OPEN[10]     
                     "M10      , " & -- IC_OPEN[11]     
                     "D16     ), " & -- IC_OPEN[12]     
  "INT0_B           : N11      , " &  
  "INT1_B           : P12      , " &  
  "M1_COL           : H15      , " &  
  "M1_CRS           : J15      , " &  
  "M1_GTX_CLK       : F16      , " &  
  "M1_MDC           : G1       , " &  
  "M1_MDIO          : G2       , " &  
  "M1_REFCLK        : J16      , " &  
  "M1_RXCLK         : H16      , " &  
  "M1_RXD           :(L12      , " & -- M1_RXD[0]       
                     "L13      , " & -- M1_RXD[1]       
                     "L14      , " & -- M1_RXD[2]       
                     "L15      , " & -- M1_RXD[3]       
                     "K12      , " & -- M1_RXD[4]       
                     "K13      , " & -- M1_RXD[5]       
                     "K14      , " & -- M1_RXD[6]       
                     "K15     ), " & -- M1_RXD[7]       
  "M1_RXDV          : K16      , " &  
  "M1_RXER          : J13      , " &  
  "M1_TXCLK         : G16      , " &  
  "M1_TXD           :(H12      , " & -- M1_TXD[0]       
                     "H13      , " & -- M1_TXD[1]       
                     "H14      , " & -- M1_TXD[2]       
                     "G15      , " & -- M1_TXD[3]       
                     "G13      , " & -- M1_TXD[4]       
                     "G12      , " & -- M1_TXD[5]       
                     "F14      , " & -- M1_TXD[6]       
                     "F15     ), " & -- M1_TXD[7]       
  "M1_TXEN          : F13      , " &  
  "M1_TXER          : E16      , " &  
  "M2_COL           : P7       , " &  
  "M2_CRS           : R6       , " &  
  "M2_GTX_CLK       : T9       , " &  
  "M2_MDC           : F1       , " &  
  "M2_MDIO          : F2       , " &  
  "M2_REFCLK        : T6       , " &  
  "M2_RXCLK         : T7       , " &  
  "M2_RXD           :(T3       , " & -- M2_RXD[0]       
                     "P4       , " & -- M2_RXD[1]       
                     "R4       , " & -- M2_RXD[2]       
                     "T4       , " & -- M2_RXD[3]       
                     "N6       , " & -- M2_RXD[4]       
                     "P5       , " & -- M2_RXD[5]       
                     "R5       , " & -- M2_RXD[6]       
                     "T5      ), " & -- M2_RXD[7]       
  "M2_RXDV          : N7       , " &  
  "M2_RXER          : P6       , " &  
  "M2_TXCLK         : T8       , " &  
  "M2_TXD           :(R8       , " & -- M2_TXD[0]       
                     "P8       , " & -- M2_TXD[1]       
                     "N8       , " & -- M2_TXD[2]       
                     "M8       , " & -- M2_TXD[3]       
                     "R9       , " & -- M2_TXD[4]       
                     "P9       , " & -- M2_TXD[5]       
                     "N9       , " & -- M2_TXD[6]       
                     "M9      ), " & -- M2_TXD[7]       
  "M2_TXEN          : T10      , " &  
  "M2_TXER          : R10      , " &  
  "NC               :(A13      , " & -- NC[1]           
                     "B10      , " & -- NC[2]           
                     "B11      , " & -- NC[3]           
                     "B12      , " & -- NC[4]           
                     "B13      , " & -- NC[5]           
                     "B5       , " & -- NC[6]           
                     "B6       , " & -- NC[7]           
                     "C1       , " & -- NC[8]           
                     "C10      , " & -- NC[9]           
                     "C11      , " & -- NC[10]          
                     "C12      , " & -- NC[11]          
                     "C13      , " & -- NC[12]          
                     "C4       , " & -- NC[13]          
                     "D13      , " & -- NC[14]          
                     "E10      , " & -- NC[15]          
                     "E11      , " & -- NC[16]          
                     "E12      , " & -- NC[17]          
                     "E3       , " & -- NC[18]          
                     "E5       , " & -- NC[19]          
                     "E6       , " & -- NC[20]          
                     "E9       , " & -- NC[21]          
                     "F5       , " & -- NC[22]          
                     "G5       , " & -- NC[23]          
                     "H3       , " & -- NC[24]          
                     "M15      , " & -- NC[25]          
                     "N15      , " & -- NC[26]          
                     "N5       , " & -- NC[27]          
                     "M5       , " & -- NC[28]          
                     "N4       , " & -- NC[29]          
                     "P2       , " & -- NC[30]          
                     "R1       , " & -- NC[31]          
                     "J3       , " & -- NC[32]          
                     "P3       , " & -- NC[33]          
                     "R2       , " & -- NC[34]          
                     "P13      , " & -- NC[35]          
                     "T15      , " & -- NC[36]          
                     "R15      , " & -- NC[37]          
                     "M12      , " & -- NC[38]          
                     "N13      , " & -- NC[39]          
                     "R16      , " & -- NC[40]          
                     "T16      , " & -- NC[41]          
                     "A4       , " & -- NC[42]          
                     "F12      , " & -- NC[43]          
                     "A3       , " & -- NC[44]          
                     "A2       , " & -- NC[45]          
                     "A1       , " & -- NC[46]          
                     "H4       , " & -- NC[47]          
                     "E8       , " & -- NC[48]          
                     "C8       , " & -- NC[49]          
                     "B8       , " & -- NC[50]          
                     "K4       , " & -- NC[51]          
                     "J5       , " & -- NC[52]          
                     "K5       , " & -- NC[53]          
                     "L5       , " & -- NC[54]          
                     "N2       , " & -- NC[55]          
                     "E7       , " & -- NC[56]          
                     "C7       , " & -- NC[57]          
                     "B7      ), " & -- NC[58]          
  "ONE_PPS_OUT      : M11      , " &  
  "OSC_I            : N16      , " &  
  "OSC_O            : M16      , " &  
  "P0_CLK0          : A14      , " &  
  "P0_CLK1          : B16      , " &  
  "P0_FP0           : A15      , " &  
  "P0_FP1           : A16      , " &  
  "P1_CLK0          : A11      , " &  
  "P1_CLK1          : A12      , " &  
  "PHY_RST_B        : G3       , " &  
  "REF              :(P1       , " & -- REF[0]          
                     "M1       , " & -- REF[1]          
                     "L1       , " & -- REF[2]          
                     "M3       , " & -- REF[3]          
                     "L3       , " & -- REF[4]          
                     "K1       , " & -- REF[5]          
                     "K2       , " & -- REF[6]          
                     "K3      ), " & -- REF[7]          
  "RST_B            : E15      , " &  
  "SCK              : T11      , " &  
  "SI               : T12      , " &  
  "SO               : R12      , " &  
  "SYNC             :(N1       , " & -- SYNC[0]         
                     "M2       , " & -- SYNC[1]         
                     "L2      ), " & -- SYNC[2]         
  "TCK              : P15      , " &  
  "TDI              : M13      , " &  
  "TDO              : M14      , " &  
  "TMS              : N14      , " &  
  "TRST_B           : P16      , " &  
  "AVDD18A          :(C3,   B1,   C2,   T14)," &
  "AVDD33A          :(B3,   B2)," &
  "AVSS             :(D5,   D4,   E4,   F4,   G4,   R14)," &
  "VDD18CORE        :(M4,   E13,  C5,   T2,   D15,  J4,   R13,  H2,   H5)," &
  "VDD33IO          :(C15,  B14,  C14,  B9,   A9,   C9,   C6,   B4,   E1,   E2,   N3,   R7," &
                     "N10,  J14,  G14)," &
  "VSS              :(F11,  B15,  D12,  D11,  D10,  D9,   D8,   D7,   D6,   F6,   G6,   G8," &
                     "G7,   F7,   F8,   F9,   F10,  D14,  F3,   G10,  G11,  G9,   H1,   H10," &
                     "H11,  H6,   H7,   H8,   H9,   J10,  J11,  J12,  J6,   J7,   J8,   J9," &
                     "K10,  K11,  K6,   K7,   K8,   K9,   L10,  L11,  L16,  L4,   L6,   L7," &
                     "L8,   L9,   P10,  R3,   T13)";
  
  attribute TAP_SCAN_IN    of TDI     : signal is true;
  attribute TAP_SCAN_MODE  of TMS     : signal is true;
  attribute TAP_SCAN_OUT   of TDO     : signal is true;
  attribute TAP_SCAN_CLOCK of TCK     : signal is (10.0e6,BOTH);
  attribute TAP_SCAN_RESET of TRST_B   : signal is true;


--
-- NOTE:  All instruction opcodes other than those defined in this file
--        should be considered PRIVATE.
--

  attribute INSTRUCTION_LENGTH of zl30314 : entity is 4;
  attribute INSTRUCTION_OPCODE of zl30314 : entity is
    "bypass                       (1111)," &
    "extest                       (0000)," &
    "idcode                       (0010)," &
    "preload                      (0001)," &
    "sample                       (0001)";

  attribute INSTRUCTION_CAPTURE of zl30314 : entity is "xx01";

  attribute IDCODE_REGISTER of zl30314 : entity is
        "0001" & 		-- version
        "0111011001101010" &    -- part number
        "00010100101" &		-- manufacturer id
        "1";


  attribute REGISTER_ACCESS of zl30314 : entity is
    "boundary (extest, sample, preload)," &
    "bypass (bypass)," &
    "device_id (idcode)" ;
 
  attribute BOUNDARY_LENGTH of zl30314 : entity is 160;
 
  attribute BOUNDARY_REGISTER of zl30314 : entity is

--       num      cell  port                    function       safe ccel  disval  rslt

	" 0     ( BC_4, M1_RXD(0),              input,         X)                        ," &
	" 1     ( BC_4, M1_RXD(1),              input,         X)                        ," &
	" 2     ( BC_4, M1_RXD(2),              input,         X)                        ," &
	" 3     ( BC_4, M1_RXD(3),              input,         X)                        ," &
	" 4     ( BC_4, M1_RXD(4),              input,         X)                        ," &
	" 5     ( BC_4, M1_RXD(5),              input,         X)                        ," &
	" 6     ( BC_4, M1_RXD(6),              input,         X)                        ," &
	" 7     ( BC_4, M1_RXD(7),              input,         X)                        ," &
	" 8     ( BC_4, M1_RXDV,                input,         X)                        ," &
	" 9     ( BC_4, M1_RXER,                input,         X)                        ," &
	" 10    ( BC_2, *,                      control,       1)                        ," &
	" 11    ( BC_7, M1_CRS,                 bidir,         X,   10,    1,      Z)    ," &
	" 12    ( BC_4, M1_REFCLK,              input,         X)                        ," &
	" 13    ( BC_4, M1_RXCLK,               input,         X)                        ," &
	" 14    ( BC_4, M1_COL,                 input,         X)                        ," &
	" 15    ( BC_2, *,                      control,       1)                        ," &
	" 16    ( BC_7, M1_TXCLK,               bidir,         X,   15,    1,      Z)    ," &
	" 17    ( BC_2, *,                      control,       1)                        ," &
	" 18    ( BC_1, M1_GTX_CLK,             output3,       X,   17,    1,      Z)    ," &
	" 19    ( BC_1, M1_TXD(0),              output2,       X)                        ," &
	" 20    ( BC_1, M1_TXD(1),              output2,       X)                        ," &
	" 21    ( BC_1, M1_TXD(2),              output2,       X)                        ," &
	" 22    ( BC_1, M1_TXD(3),              output2,       X)                        ," &
	" 23    ( BC_1, M1_TXD(4),              output2,       X)                        ," &
	" 24    ( BC_1, M1_TXD(5),              output2,       X)                        ," &
	" 25    ( BC_1, M1_TXD(6),              output2,       X)                        ," &
	" 26    ( BC_1, M1_TXD(7),              output2,       X)                        ," &
	" 27    ( BC_1, M1_TXEN,                output2,       X)                        ," &
	" 28    ( BC_1, M1_TXER,                output2,       X)                        ," &
	" 29    ( BC_0, *,                      internal,      X)                        ," &
	" 30    ( BC_4, RST_B,                  input,         X)                        ," &
	" 31    ( BC_0, *,                      internal,      X)                        ," &
	" 32    ( BC_0, *,                      internal,      X)                        ," &
	" 33    ( BC_2, *,                      control,       1)                        ," &
	" 34    ( BC_1, P0_CLK1,                output3,       X,   33,    1,      Z)    ," &
	" 35    ( BC_2, *,                      control,       1)                        ," &
	" 36    ( BC_1, P0_FP1,                 output3,       X,   35,    1,      Z)    ," &
	" 37    ( BC_2, *,                      control,       1)                        ," &
	" 38    ( BC_1, P0_FP0,                 output3,       X,   37,    1,      Z)    ," &
	" 39    ( BC_2, *,                      control,       1)                        ," &
	" 40    ( BC_1, P0_CLK0,                output3,       X,   39,    1,      Z)    ," &
	" 41    ( BC_2, *,                      control,       1)                        ," &
	" 42    ( BC_1, P1_CLK1,                output3,       X,   41,    1,      Z)    ," &
	" 43    ( BC_2, *,                      control,       1)                        ," &
	" 44    ( BC_1, P1_CLK0,                output3,       X,   43,    1,      Z)    ," &
	" 45    ( BC_0, *,                      internal,      1)                        ," &
	" 46    ( BC_0, *,                      internal,      X)                        ," &
	" 47    ( BC_0, *,                      internal,      X)                        ," &
	" 48    ( BC_0, *,                      internal,      X)                        ," &
	" 49    ( BC_0, *,                      internal,      X)                        ," &
	" 50    ( BC_0, *,                      internal,      X)                        ," &
	" 51    ( BC_0, *,                      internal,      X)                        ," &
	" 52    ( BC_0, *,                      internal,      X)                        ," &
	" 53    ( BC_2, *,                      control,       1)                        ," &
	" 54    ( BC_1, ETH_CLK1,               output3,       X,   53,    1,      Z)    ," &
	" 55    ( BC_0, *,                      internal,      1)                        ," &
	" 56    ( BC_0, *,                      internal,      X)                        ," &
	" 57    ( BC_0, *,                      internal,      1)                        ," &
	" 58    ( BC_0, *,                      internal,      X)                        ," &
	" 59    ( BC_2, *,                      control,       1)                        ," &
	" 60    ( BC_1, ETH_CLK0,               output3,       X,   59,    1,      Z)    ," &
	" 61    ( BC_2, *,                      control,       1)                        ," &
	" 62    ( BC_7, M2_MDC,                 bidir,         X,   61,    1,      Z)    ," &
	" 63    ( BC_2, *,                      control,       1)                        ," &
	" 64    ( BC_7, M2_MDIO,                bidir,         X,   63,    1,      Z)    ," &
	" 65    ( BC_1, PHY_RST_B,              output2,       X)                        ," &
	" 66    ( BC_2, *,                      control,       1)                        ," &
	" 67    ( BC_7, M1_MDC,                 bidir,         X,   66,    1,      Z)    ," &
	" 68    ( BC_2, *,                      control,       1)                        ," &
	" 69    ( BC_7, M1_MDIO,                bidir,         X,   68,    1,      Z)    ," &
	" 70    ( BC_0, *,                      internal,      X)                        ," &
	" 71    ( BC_0, *,                      internal,      X)                        ," &
	" 72    ( BC_0, *,                      internal,      X)                        ," &
	" 73    ( BC_0, *,                      internal,      X)                        ," &
	" 74    ( BC_0, *,                      internal,      X)                        ," &
	" 75    ( BC_0, *,                      internal,      X)                        ," &
	" 76    ( BC_0, *,                      internal,      X)                        ," &
	" 77    ( BC_0, *,                      internal,      X)                        ," &
	" 78    ( BC_4, REF(7),                 input,         X)                        ," &
	" 79    ( BC_4, REF(6),                 input,         X)                        ," &
	" 80    ( BC_4, REF(5),                 input,         X)                        ," &
	" 81    ( BC_4, REF(4),                 input,         X)                        ," &
	" 82    ( BC_4, REF(3),                 input,         X)                        ," &
	" 83    ( BC_4, REF(2),                 input,         X)                        ," &
	" 84    ( BC_4, SYNC(2),                input,         X)                        ," &
	" 85    ( BC_4, REF(1),                 input,         X)                        ," &
	" 86    ( BC_4, SYNC(1),                input,         X)                        ," &
	" 87    ( BC_4, SYNC(0),                input,         X)                        ," &
	" 88    ( BC_4, REF(0),                 input,         X)                        ," &
	" 89    ( BC_0, *,                      internal,      1)                        ," &
	" 90    ( BC_0, *,                      internal,      X)                        ," &
	" 91    ( BC_0, *,                      internal,      1)                        ," &
	" 92    ( BC_0, *,                      internal,      X)                        ," &
	" 93    ( BC_0, *,                      internal,      1)                        ," &
	" 94    ( BC_0, *,                      internal,      X)                        ," &
	" 95    ( BC_0, *,                      internal,      1)                        ," &
	" 96    ( BC_0, *,                      internal,      X)                        ," &
	" 97    ( BC_0, *,                      internal,      1)                        ," &
	" 98    ( BC_0, *,                      internal,      X)                        ," &
	" 99    ( BC_0, *,                      internal,      X)                        ," &
	" 100   ( BC_0, *,                      internal,      X)                        ," &
	" 101   ( BC_0, *,                      internal,      X)                        ," &
	" 102   ( BC_0, *,                      internal,      X)                        ," &
	" 103   ( BC_0, *,                      internal,      X)                        ," &
	" 104   ( BC_2, *,                      control,       1)                        ," &
	" 105   ( BC_1, DPLL2_IN_REF,           output3,       X,   104,   1,      Z)    ," &
	" 106   ( BC_4, M2_RXD(0),              input,         X)                        ," &
	" 107   ( BC_4, M2_RXD(1),              input,         X)                        ," &
	" 108   ( BC_4, M2_RXD(2),              input,         X)                        ," &
	" 109   ( BC_4, M2_RXD(3),              input,         X)                        ," &
	" 110   ( BC_4, M2_RXD(4),              input,         X)                        ," &
	" 111   ( BC_4, M2_RXD(5),              input,         X)                        ," &
	" 112   ( BC_4, M2_RXD(6),              input,         X)                        ," &
	" 113   ( BC_4, M2_RXD(7),              input,         X)                        ," &
	" 114   ( BC_4, M2_RXDV,                input,         X)                        ," &
	" 115   ( BC_4, M2_RXER,                input,         X)                        ," &
	" 116   ( BC_2, *,                      control,       1)                        ," &
	" 117   ( BC_7, M2_CRS,                 bidir,         X,   116,   1,      Z)    ," &
	" 118   ( BC_4, M2_REFCLK,              input,         X)                        ," &
	" 119   ( BC_4, M2_RXCLK,               input,         X)                        ," &
	" 120   ( BC_4, M2_COL,                 input,         X)                        ," &
	" 121   ( BC_2, *,                      control,       1)                        ," &
	" 122   ( BC_7, M2_TXCLK,               bidir,         X,   121,   1,      Z)    ," &
	" 123   ( BC_2, *,                      control,       1)                        ," &
	" 124   ( BC_1, M2_GTX_CLK,             output3,       X,   123,   1,      Z)    ," &
	" 125   ( BC_1, M2_TXD(0),              output2,       X)                        ," &
	" 126   ( BC_1, M2_TXD(1),              output2,       X)                        ," &
	" 127   ( BC_1, M2_TXD(2),              output2,       X)                        ," &
	" 128   ( BC_1, M2_TXD(3),              output2,       X)                        ," &
	" 129   ( BC_1, M2_TXD(4),              output2,       X)                        ," &
	" 130   ( BC_1, M2_TXD(5),              output2,       X)                        ," &
	" 131   ( BC_1, M2_TXD(6),              output2,       X)                        ," &
	" 132   ( BC_1, M2_TXD(7),              output2,       X)                        ," &
	" 133   ( BC_1, M2_TXEN,                output2,       X)                        ," &
	" 134   ( BC_1, M2_TXER,                output2,       X)                        ," &
	" 135   ( BC_2, *,                      control,       1)                        ," &
	" 136   ( BC_7, SCK,                    bidir,         X,   135,   1,      Z)    ," &
	" 137   ( BC_4, CS_B,                   input,         X)                        ," &
	" 138   ( BC_0, *,                      internal,      X)                        ," &
	" 139   ( BC_0, *,                      internal,      X)                        ," &
	" 140   ( BC_2, *,                      control,       1)                        ," &
	" 141   ( BC_7, SI,                     bidir,         X,   140,   1,      Z)    ," &
	" 142   ( BC_2, *,                      control,       1)                        ," &
	" 143   ( BC_1, SO,                     output3,       X,   142,   1,      Z)    ," &
	" 144   ( BC_2, *,                      control,       1)                        ," &
	" 145   ( BC_1, INT1_B,                 output3,       X,   144,   1,      Z)    ," &
	" 146   ( BC_2, *,                      control,       1)                        ," &
	" 147   ( BC_1, INT0_B,                 output3,       X,   146,   1,      Z)    ," &
	" 148   ( BC_0, *,                      internal,      X)                        ," &
	" 149   ( BC_0, *,                      internal,      1)                        ," &
	" 150   ( BC_0, *,                      internal,      X)                        ," &
	" 151   ( BC_2, *,                      control,       1)                        ," &
	" 152   ( BC_1, ONE_PPS_OUT,            output3,       X,   151,   1,      Z)    ," &
	" 153   ( BC_0, *,                      internal,      X)                        ," &
	" 154   ( BC_0, *,                      internal,      X)                        ," &
	" 155   ( BC_0, *,                      internal,      X)                        ," &
	" 156   ( BC_0, *,                      internal,      X)                        ," &
	" 157   ( BC_0, *,                      internal,      X)                        ," &
	" 158   ( BC_0, *,                      internal,      X)                        ," &
	" 159   ( BC_0, *,                      internal,      X)                        ";

end zl30314;

------------- end of BSDL description for the zl30314 ----------