BSDL Files Library for JTAG

The only free public library that contains thousands of BSDL (Boundary Scan Description Language) models to use with BScan/JTAG tools

BSDL model: tms320tci6614

----------------------------------------------------------------------
-- BSDL Description for TMS320TCI6614 PG1.0                                  
-- Revised 26 July 2012                                             --
----------------------------------------------------------------------
--  Supported Devices: tms320tci6614 Revision 1.0                   --
--  Supported Devices: tms320tci6612 Revision 1.0                   --
----------------------------------------------------------------------
--  Created by    : Texas Instruments Incorporated                  --
--  BSDL Revision : 0.4 Swapped BC_1 to BC_4 for Serdes input pins           --
--  BSDL Revision : 0.3 Updated pull up/down for some pins                   --
--  BSDL Revision : 0.2 masked off coreclksel & spics2              --
--  BSDL Revision : 0.1 originally created                                   --
--                                                                  --
--  BSDL Status   : Released                                        --
--  Date Created  : 05 July 2012                                    --
--  Revision      : 1.4                                             --
----------------------------------------------------------------------
--                                                                  --
--                          IMPORTANT NOTICE
--  Texas Instruments Incorporated (TI) reserves the right to make
--  changes to its products or to discontinue any semiconductor
--  product or service without notice, and advises its customers to
--  obtain the latest version of the relevant information to
--  verify, before placing orders, that the information being
--  relied on is current.
--  TI warrants performance of its semiconductor products and
--  related software to the specifications applicable at the time
--  of sale in accordance with TI's standard warranty. Testing and
--  other quality control techniques are utilized to the extent TI
--  deems necessary to support this warranty. Specific testing of
--  all parameters of each device is not necessarily performed,
--  except those mandated by government requirements.
--
--  Certain applications using semiconductor devices may involve
--  potential risks of death, personal injury, or severe property
--  or environmental damage ("Critical Applications").
--    TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED,
--    AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN
--    LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER
--    CRITICAL APPLICATIONS.
--  Inclusion of TI products in such applications is understood
--  to be fully at the risk of the customer.  Use of TI products
--  in such applications requires the written approval of an
--  appropriate TI officer. Questions concerning potential risk
--  applications should be directed to TI through a local SC sales
--  office.
--  In order to minimize risks associated with the customer's
--  applications, adequate design and operating safeguards should
--  be provided by the
--  customer to minimize inherent or procedural hazards.

--  TI assumes no liability for applications assistance, customer
--  product design, software performance, or infringement of
--  patents or services described herein.  Nor does TI warrant or
--  represent that any license, either express or implied, is
--  granted under any patent right, copyright, mask work right, or
--  other intellectual property right of TI covering or relating
--  to any combination, machine, or process in which such
--  semiconductor products or services might be or are used.
--  Also see: Standard Terms and Conditions of Sale for Semiconductor        --
--  Products. www.ti.com/sc/docs/stdterms.htm                                --
--                                                                           --
--  Mailing Address:                                                         --
--                                                                           --
--             Texas Instruments                                             --
--             Post Office Box 655303                                        --
--             Dallas, Texas 75265                                           --
--            Copyright (c) 2007, Texas Instruments Incorporated
-------------------------------------------------------------------


entity tms320tci6614 is

  generic(PHYSICAL_PIN_MAP : string := "CMS");

  port(
   rsv26                           :  linkage bit;
   rsv27                           :  linkage bit;
   aifrxn0                         :  in      bit;
   aifrxn1                         :  in      bit;
   aifrxn2                         :  in      bit;
   aifrxn3                         :  in      bit;
   aifrxn4                         :  in      bit;
   aifrxn5                         :  in      bit;
   aifrxp0                         :  in      bit;
   aifrxp1                         :  in      bit;
   aifrxp2                         :  in      bit;
   aifrxp3                         :  in      bit;
   aifrxp4                         :  in      bit;
   aifrxp5                         :  in      bit;
   aiftxn0                         :  buffer  bit;
   aiftxn1                         :  buffer  bit;
   aiftxn2                         :  buffer  bit;
   aiftxn3                         :  buffer  bit;
   aiftxn4                         :  buffer  bit;
   aiftxn5                         :  buffer  bit;
   aiftxp0                         :  buffer  bit;
   aiftxp1                         :  buffer  bit;
   aiftxp2                         :  buffer  bit;
   aiftxp3                         :  buffer  bit;
   aiftxp4                         :  buffer  bit;
   aiftxp5                         :  buffer  bit;
   altcoreclkn                     :  in      bit;
   altcoreclkp                     :  in      bit;
   bootcomplete                    :  inout   bit;
-- coreclksel                      :  inout   bit;
   rsv20                           :  inout   bit;
   rsv05                           :  buffer  bit;
   rsv04                           :  buffer  bit;
   coresel0                        :  inout   bit;
   coresel1                        :  inout   bit;
   coresel2                        :  inout   bit;
   rsv21                           :  inout   bit;
   rsv07                           :  buffer  bit;
   rsv06                           :  buffer  bit;
   ddra00                          :  inout   bit;
   ddra01                          :  inout   bit;
   ddra02                          :  inout   bit;
   ddra03                          :  inout   bit;
   ddra04                          :  inout   bit;
   ddra05                          :  inout   bit;
   ddra06                          :  inout   bit;
   ddra07                          :  inout   bit;
   ddra08                          :  inout   bit;
   ddra09                          :  inout   bit;
   ddra10                          :  inout   bit;
   ddra11                          :  inout   bit;
   ddra12                          :  inout   bit;
   ddra13                          :  inout   bit;
   ddra14                          :  inout   bit;
   ddra15                          :  inout   bit;
   ddrba0                          :  inout   bit;
   ddrba1                          :  inout   bit;
   ddrba2                          :  inout   bit;
   ddrcasz                         :  inout   bit;
   ddrcb00                         :  inout   bit;
   ddrcb01                         :  inout   bit;
   ddrcb02                         :  inout   bit;
   ddrcb03                         :  inout   bit;
   ddrcb04                         :  inout   bit;
   ddrcb05                         :  inout   bit;
   ddrcb06                         :  inout   bit;
   ddrcb07                         :  inout   bit;
   ddrce0z                         :  inout   bit;
   ddrce1z                         :  inout   bit;
   ddrcke0                         :  inout   bit;
   ddrcke1                         :  inout   bit;
   ddrclkn                         :  in      bit;
   ddrclkp                         :  in      bit;
   ddrclkoutn0                     :  inout   bit;
   ddrclkoutn1                     :  inout   bit;
   ddrclkoutp0                     :  inout   bit;
   ddrclkoutp1                     :  inout   bit;
   ddrd00                          :  inout   bit;
   ddrd01                          :  inout   bit;
   ddrd02                          :  inout   bit;
   ddrd03                          :  inout   bit;
   ddrd04                          :  inout   bit;
   ddrd05                          :  inout   bit;
   ddrd06                          :  inout   bit;
   ddrd07                          :  inout   bit;
   ddrd08                          :  inout   bit;
   ddrd09                          :  inout   bit;
   ddrd10                          :  inout   bit;
   ddrd11                          :  inout   bit;
   ddrd12                          :  inout   bit;
   ddrd13                          :  inout   bit;
   ddrd14                          :  inout   bit;
   ddrd15                          :  inout   bit;
   ddrd16                          :  inout   bit;
   ddrd17                          :  inout   bit;
   ddrd18                          :  inout   bit;
   ddrd19                          :  inout   bit;
   ddrd20                          :  inout   bit;
   ddrd21                          :  inout   bit;
   ddrd22                          :  inout   bit;
   ddrd23                          :  inout   bit;
   ddrd24                          :  inout   bit;
   ddrd25                          :  inout   bit;
   ddrd26                          :  inout   bit;
   ddrd27                          :  inout   bit;
   ddrd28                          :  inout   bit;
   ddrd29                          :  inout   bit;
   ddrd30                          :  inout   bit;
   ddrd31                          :  inout   bit;
   ddrd32                          :  inout   bit;
   ddrd33                          :  inout   bit;
   ddrd34                          :  inout   bit;
   ddrd35                          :  inout   bit;
   ddrd36                          :  inout   bit;
   ddrd37                          :  inout   bit;
   ddrd38                          :  inout   bit;
   ddrd39                          :  inout   bit;
   ddrd40                          :  inout   bit;
   ddrd41                          :  inout   bit;
   ddrd42                          :  inout   bit;
   ddrd43                          :  inout   bit;
   ddrd44                          :  inout   bit;
   ddrd45                          :  inout   bit;
   ddrd46                          :  inout   bit;
   ddrd47                          :  inout   bit;
   ddrd48                          :  inout   bit;
   ddrd49                          :  inout   bit;
   ddrd50                          :  inout   bit;
   ddrd51                          :  inout   bit;
   ddrd52                          :  inout   bit;
   ddrd53                          :  inout   bit;
   ddrd54                          :  inout   bit;
   ddrd55                          :  inout   bit;
   ddrd56                          :  inout   bit;
   ddrd57                          :  inout   bit;
   ddrd58                          :  inout   bit;
   ddrd59                          :  inout   bit;
   ddrd60                          :  inout   bit;
   ddrd61                          :  inout   bit;
   ddrd62                          :  inout   bit;
   ddrd63                          :  inout   bit;
   ddrdqm0                         :  inout   bit;
   ddrdqm1                         :  inout   bit;
   ddrdqm2                         :  inout   bit;
   ddrdqm3                         :  inout   bit;
   ddrdqm4                         :  inout   bit;
   ddrdqm5                         :  inout   bit;
   ddrdqm6                         :  inout   bit;
   ddrdqm7                         :  inout   bit;
   ddrdqm8                         :  inout   bit;
   ddrdqs0n                        :  inout   bit;
   ddrdqs0p                        :  inout   bit;
   ddrdqs1n                        :  inout   bit;
   ddrdqs1p                        :  inout   bit;
   ddrdqs2n                        :  inout   bit;
   ddrdqs2p                        :  inout   bit;
   ddrdqs3n                        :  inout   bit;
   ddrdqs3p                        :  inout   bit;
   ddrdqs4n                        :  inout   bit;
   ddrdqs4p                        :  inout   bit;
   ddrdqs5n                        :  inout   bit;
   ddrdqs5p                        :  inout   bit;
   ddrdqs6n                        :  inout   bit;
   ddrdqs6p                        :  inout   bit;
   ddrdqs7n                        :  inout   bit;
   ddrdqs7p                        :  inout   bit;
   ddrdqs8n                        :  inout   bit;
   ddrdqs8p                        :  inout   bit;
   ddrodt0                         :  inout   bit;
   ddrodt1                         :  inout   bit;
   ddrrasz                         :  inout   bit;
   ddrresetz                       :  inout   bit;
   ddrslrate0                      :  inout   bit;
   ddrslrate1                      :  inout   bit;
   ddrwez                          :  inout   bit;
   paclksel                        :  inout   bit;
   emifa00                         :  inout   bit;
   emifa01                         :  inout   bit;
   emifa02                         :  inout   bit;
   emifa03                         :  inout   bit;
   emifa04                         :  inout   bit;
   emifa05                         :  inout   bit;
   emifa06                         :  inout   bit;
   emifa07                         :  inout   bit;
   emifa08                         :  inout   bit;
   emifa09                         :  inout   bit;
   emifa10                         :  inout   bit;
   emifa11                         :  inout   bit;
   emifa12                         :  inout   bit;
   emifa13                         :  inout   bit;
   emifa14                         :  inout   bit;
   emifa15                         :  inout   bit;
   emifa16                         :  inout   bit;
   emifa17                         :  inout   bit;
   emifa18                         :  inout   bit;
   emifa19                         :  inout   bit;
   emifa20                         :  inout   bit;
   emifa21                         :  inout   bit;
   emifa22                         :  inout   bit;
   emifa23                         :  inout   bit;
   emifbe0z                        :  inout   bit;
   emifbe1z                        :  inout   bit;
   emifce0z                        :  inout   bit;
   emifce1z                        :  inout   bit;
   emifce2z                        :  inout   bit;
   emifce3z                        :  inout   bit;
   emifd00                         :  inout   bit;
   emifd01                         :  inout   bit;
   emifd02                         :  inout   bit;
   emifd03                         :  inout   bit;
   emifd04                         :  inout   bit;
   emifd05                         :  inout   bit;
   emifd06                         :  inout   bit;
   emifd07                         :  inout   bit;
   emifd08                         :  inout   bit;
   emifd09                         :  inout   bit;
   emifd10                         :  inout   bit;
   emifd11                         :  inout   bit;
   emifd12                         :  inout   bit;
   emifd13                         :  inout   bit;
   emifd14                         :  inout   bit;
   emifd15                         :  inout   bit;
   emifoez                         :  inout   bit;
   emifrnw                         :  inout   bit;
   emifwez                         :  inout   bit;
   emifwait0                       :  inout   bit;
   emifwait1                       :  inout   bit;
   emu00                           :  inout   bit;
   emu01                           :  inout   bit;
   emu02                           :  inout   bit;
   emu03                           :  inout   bit;
   emu04                           :  inout   bit;
   emu05                           :  inout   bit;
   emu06                           :  inout   bit;
   emu07                           :  inout   bit;
   emu08                           :  inout   bit;
   emu09                           :  inout   bit;
   emu10                           :  inout   bit;
   emu11                           :  inout   bit;
   emu12                           :  inout   bit;
   emu13                           :  inout   bit;
   emu14                           :  inout   bit;
   emu15                           :  inout   bit;
   emu16                           :  inout   bit;
   emu17                           :  inout   bit;
   emu18                           :  inout   bit;
   rsv01                           :  inout   bit;
   gpio00                          :  inout   bit;
   gpio01                          :  inout   bit;
   gpio02                          :  inout   bit;
   gpio03                          :  inout   bit;
   gpio04                          :  inout   bit;
   gpio05                          :  inout   bit;
   gpio06                          :  inout   bit;
   gpio07                          :  inout   bit;
   gpio08                          :  inout   bit;
   gpio09                          :  inout   bit;
   gpio10                          :  inout   bit;
   gpio11                          :  inout   bit;
   gpio12                          :  inout   bit;
   gpio13                          :  inout   bit;
   gpio14                          :  inout   bit;
   gpio15                          :  inout   bit;
   gpio16                          :  inout   bit;
   gpio17                          :  inout   bit;
   gpio18                          :  inout   bit;
   gpio19                          :  inout   bit;
   gpio20                          :  inout   bit;
   gpio21                          :  inout   bit;
   gpio22                          :  inout   bit;
   gpio23                          :  inout   bit;
   gpio24                          :  inout   bit;
   gpio25                          :  inout   bit;
   gpio26                          :  inout   bit;
   gpio27                          :  inout   bit;
   gpio28                          :  inout   bit;
   gpio29                          :  inout   bit;
   gpio30                          :  inout   bit;
   gpio31                          :  inout   bit;
   hout                            :  inout   bit;
   rsv14                           :  linkage bit;
   mcmclkn                         :  in      bit;
   mcmclkp                         :  in      bit;
   mcmrefclkoutn                   :  linkage bit;
   mcmrefclkoutp                   :  linkage bit;
   mcmrxflclk                      :  inout   bit;
   mcmrxfldat                      :  inout   bit;
   mcmrxn0                         :  in      bit;
   mcmrxn1                         :  in      bit;
   mcmrxn2                         :  in      bit;
   mcmrxn3                         :  in      bit;
   mcmrxp0                         :  in      bit;
   mcmrxp1                         :  in      bit;
   mcmrxp2                         :  in      bit;
   mcmrxp3                         :  in      bit;
   mcmrxpmclk                      :  inout   bit;
   mcmrxpmdat                      :  inout   bit;
   mcmtxflclk                      :  inout   bit;
   mcmtxfldat                      :  inout   bit;
   mcmtxn0                         :  buffer  bit;
   mcmtxn1                         :  buffer  bit;
   mcmtxn2                         :  buffer  bit;
   mcmtxn3                         :  buffer  bit;
   mcmtxp0                         :  buffer  bit;
   mcmtxp1                         :  buffer  bit;
   mcmtxp2                         :  buffer  bit;
   mcmtxp3                         :  buffer  bit;
   mcmtxpmclk                      :  inout   bit;
   mcmtxpmdat                      :  inout   bit;
   mdclk                           :  inout   bit;
   mdio                            :  inout   bit;
   paclkn                          :  in      bit;
   paclkp                          :  in      bit;
   rsv25                           :  buffer  bit;
   rsv24                           :  buffer  bit;
   rsv22                           :  inout   bit;
   rsv03                           :  inout   bit;
   rsv16                           :  linkage bit;
   pcieclkn                        :  in      bit;
   pcieclkp                        :  in      bit;
   pcierxn0                        :  in      bit;
   pcierxn1                        :  in      bit;
   pcierxp0                        :  in      bit;
   pcierxp1                        :  in      bit;
   pcietxn0                        :  buffer  bit;
   pcietxn1                        :  buffer  bit;
   pcietxp0                        :  buffer  bit;
   pcietxp1                        :  buffer  bit;
   rsv08                           :  linkage bit;
   rsv09                           :  linkage bit;
   ptv15                           :  linkage bit;
   physync                         :  inout   bit;
   radsync                         :  inout   bit;
   nmiz                            :  inout   bit;
   porz                            :  in      bit;
   resetz                          :  in      bit;
   resetfullz                      :  in      bit;
   resetstatz                      :  inout   bit;
   lresetnmienz                    :  inout   bit;
   lresetz                         :  inout   bit;
   riorxn0                         :  in      bit;
   riorxn1                         :  in      bit;
   riorxn2                         :  in      bit;
   riorxn3                         :  in      bit;
   riorxp0                         :  in      bit;
   riorxp1                         :  in      bit;
   riorxp2                         :  in      bit;
   riorxp3                         :  in      bit;
   riotxn0                         :  buffer  bit;
   riotxn1                         :  buffer  bit;
   riotxn2                         :  buffer  bit;
   riotxn3                         :  buffer  bit;
   riotxp0                         :  buffer  bit;
   riotxp1                         :  buffer  bit;
   riotxp2                         :  buffer  bit;
   riotxp3                         :  buffer  bit;
   rp1clkn                         :  in      bit;
   rp1clkp                         :  in      bit;
   rp1fbn                          :  in      bit;
   rp1fbp                          :  in      bit;
   scl                             :  inout   bit;
   sda                             :  inout   bit;
   rsv17                           :  linkage bit;
   sgmiirxn0                       :  in      bit;
   sgmiirxn1                       :  in      bit;
   sgmiirxp0                       :  in      bit;
   sgmiirxp1                       :  in      bit;
   sgmiitxn0                       :  buffer  bit;
   sgmiitxn1                       :  buffer  bit;
   sgmiitxp0                       :  buffer  bit;
   sgmiitxp1                       :  buffer  bit;
   extframeevent                   :  inout   bit;
   spiclk                          :  inout   bit;
   spiscs0                         :  inout   bit;
   spiscs1                         :  inout   bit;
-- spiscs2                         :  inout   bit;
   spiscs3                         :  inout   bit;
   spiscs4                         :  inout   bit;
   spisimo                         :  inout   bit;
   spisomi                         :  inout   bit;
   sriosgmiiclkn                   :  in      bit;
   sriosgmiiclkp                   :  in      bit;
   sysclkn                         :  in      bit;
   sysclkp                         :  in      bit;
   sysclkout                       :  inout   bit;
   tck                             :  in      bit;
   tdi                             :  in      bit;
   tms                             :  in      bit;
   trstz                           :  in      bit;
   tdo                             :  out     bit;
   timi0                           :  inout   bit;
   timi1                           :  inout   bit;
   timo0                           :  inout   bit;
   timo1                           :  inout   bit;
   uart1cts                        :  inout   bit;
   uart1rts                        :  inout   bit;
   uart1rxd                        :  inout   bit;
   uart1txd                        :  inout   bit;
   uartcts                         :  inout   bit;
   uartrts                         :  inout   bit;
   uartrxd                         :  inout   bit;
   uarttxd                         :  inout   bit;
   usimclk                         :  inout   bit;
   usimio                          :  inout   bit;
   usimrst                         :  inout   bit;
   rsv29                           :  inout   bit;
   vcntl0                          :  out     bit;
   vcntl1                          :  out     bit;
   vcntl2                          :  out     bit;
   vcntl3                          :  out     bit;
   rsv30                           :  inout   bit;

   vdd                             : linkage bit_vector(1 to 190);
   vss                             : linkage bit_vector(1 to 294));

 use STD_1149_1_2001.all;

 attribute COMPONENT_CONFORMANCE of tms320tci6614 : entity is "STD_1149_1_2001";

 attribute      PIN_MAP          of tms320tci6614 : entity is PHYSICAL_PIN_MAP;
 constant CMS : PIN_MAP_STRING :=

   "rsv26                 :  V25," &  
   "rsv27                 :  R25," &  
   "aifrxn0               :  T29," &  
   "aifrxn1               :  R30," &  
   "aifrxn2               :  Y29," &  
   "aifrxn3               :  W30," &  
   "aifrxn4               :  AA30," &  
   "aifrxn5               :  AB29," &  
   "aifrxp0               :  U29," &  
   "aifrxp1               :  T30," &  
   "aifrxp2               :  W29," &  
   "aifrxp3               :  V30," &  
   "aifrxp4               :  AB30," &  
   "aifrxp5               :  AC29," &  
   "aiftxn0               :  T27," &  
   "aiftxn1               :  T28," &  
   "aiftxn2               :  Y27," &  
   "aiftxn3               :  W28," &  
   "aiftxn4               :  AB28," &  
   "aiftxn5               :  AB27," &  
   "aiftxp0               :  U27," &  
   "aiftxp1               :  R28," &  
   "aiftxp2               :  W27," &  
   "aiftxp3               :  V28," &  
   "aiftxp4               :  AA28," &  
   "aiftxp5               :  AC27," &  
   "altcoreclkn           :  AD25," &  
   "altcoreclkp           :  AC25," &  
   "bootcomplete          :  F2," &  
-- "coreclksel            :  AC26," &  
   "rsv20                 :  AE23," &  
   "rsv05                 :  AD24," &  
   "rsv04                 :  AE24," &  
   "coresel0              :  G3," &  
   "coresel1              :  J4," &  
   "coresel2              :  H3," &  
   "rsv21                 :  H5," &  
   "rsv07                 :  E2," &  
   "rsv06                 :  D2," &  
   "ddra00                :  D17," &  
   "ddra01                :  B16," &  
   "ddra02                :  C17," &  
   "ddra03                :  B17," &  
   "ddra04                :  E17," &  
   "ddra05                :  B15," &  
   "ddra06                :  A15," &  
   "ddra07                :  A16," &  
   "ddra08                :  D16," &  
   "ddra09                :  E16," &  
   "ddra10                :  C15," &  
   "ddra11                :  D15," &  
   "ddra12                :  F16," &  
   "ddra13                :  F17," &  
   "ddra14                :  E14," &  
   "ddra15                :  F14," &  
   "ddrba0                :  A18," &  
   "ddrba1                :  A19," &  
   "ddrba2                :  B18," &  
   "ddrcasz               :  E19," &  
   "ddrcb00               :  E13," &  
   "ddrcb01               :  F13," &  
   "ddrcb02               :  F12," &  
   "ddrcb03               :  D13," &  
   "ddrcb04               :  C12," &  
   "ddrcb05               :  B12," &  
   "ddrcb06               :  B11," &  
   "ddrcb07               :  A11," &  
   "ddrce0z               :  F19," &  
   "ddrce1z               :  F18," &  
   "ddrcke0               :  D20," &  
   "ddrcke1               :  D14," &  
   "ddrclkn               :  C1," &  
   "ddrclkoutn0           :  B20," &  
   "ddrclkoutn1           :  B14," &  
   "ddrclkoutp0           :  A20," &  
   "ddrclkoutp1           :  C14," &  
   "ddrclkp               :  B1," &  
   "ddrd00                :  C3," &  
   "ddrd01                :  B2," &  
   "ddrd02                :  F5," &  
   "ddrd03                :  E4," &  
   "ddrd04                :  D3," &  
   "ddrd05                :  B4," &  
   "ddrd06                :  A4," &  
   "ddrd07                :  D4," &  
   "ddrd08                :  E5," &  
   "ddrd09                :  F6," &  
   "ddrd10                :  G6," &  
   "ddrd11                :  F7," &  
   "ddrd12                :  A6," &  
   "ddrd13                :  B6," &  
   "ddrd14                :  C6," &  
   "ddrd15                :  D6," &  
   "ddrd16                :  D7," &  
   "ddrd17                :  F8," &  
   "ddrd18                :  D8," &  
   "ddrd19                :  E8," &  
   "ddrd20                :  B7," &  
   "ddrd21                :  A9," &  
   "ddrd22                :  A7," &  
   "ddrd23                :  B9," &  
   "ddrd24                :  F9," &  
   "ddrd25                :  D10," &  
   "ddrd26                :  E10," &  
   "ddrd27                :  D9," &  
   "ddrd28                :  C9," &  
   "ddrd29                :  E11," &  
   "ddrd30                :  C11," &  
   "ddrd31                :  D11," &  
   "ddrd32                :  F20," &  
   "ddrd33                :  D21," &  
   "ddrd34                :  B22," &  
   "ddrd35                :  C22," &  
   "ddrd36                :  D22," &  
   "ddrd37                :  F22," &  
   "ddrd38                :  E22," &  
   "ddrd39                :  F21," &  
   "ddrd40                :  B23," &  
   "ddrd41                :  D23," &  
   "ddrd42                :  D24," &  
   "ddrd43                :  C23," &  
   "ddrd44                :  E24," &  
   "ddrd45                :  F23," &  
   "ddrd46                :  F24," &  
   "ddrd47                :  E25," &  
   "ddrd48                :  B26," &  
   "ddrd49                :  A26," &  
   "ddrd50                :  B27," &  
   "ddrd51                :  C27," &  
   "ddrd52                :  C26," &  
   "ddrd53                :  D25," &  
   "ddrd54                :  D26," &  
   "ddrd55                :  E26," &  
   "ddrd56                :  A29," &  
   "ddrd57                :  B29," &  
   "ddrd58                :  C28," &  
   "ddrd59                :  B28," &  
   "ddrd60                :  D27," &  
   "ddrd61                :  D29," &  
   "ddrd62                :  D30," &  
   "ddrd63                :  D28," &  
   "ddrdqm0               :  A2," &  
   "ddrdqm1               :  D5," &  
   "ddrdqm2               :  E7," &  
   "ddrdqm3               :  F10," &  
   "ddrdqm4               :  E21," &  
   "ddrdqm5               :  A23," &  
   "ddrdqm6               :  A27," &  
   "ddrdqm7               :  A28," &  
   "ddrdqm8               :  D12," &  
   "ddrdqs0n              :  A3," &  
   "ddrdqs0p              :  B3," &  
   "ddrdqs1n              :  C5," &  
   "ddrdqs1p              :  B5," &  
   "ddrdqs2n              :  C8," &  
   "ddrdqs2p              :  B8," &  
   "ddrdqs3n              :  B10," &  
   "ddrdqs3p              :  A10," &  
   "ddrdqs4n              :  B21," &  
   "ddrdqs4p              :  A21," &  
   "ddrdqs5n              :  B24," &  
   "ddrdqs5p              :  A24," &  
   "ddrdqs6n              :  C25," &  
   "ddrdqs6p              :  B25," &  
   "ddrdqs7n              :  B30," &  
   "ddrdqs7p              :  C30," &  
   "ddrdqs8n              :  A13," &  
   "ddrdqs8p              :  B13," &  
   "ddrodt0               :  C18," &  
   "ddrodt1               :  D18," &  
   "ddrrasz               :  D19," &  
   "ddrresetz             :  C20," &  
   "ddrslrate0            :  E1," &  
   "ddrslrate1            :  D1," &  
   "ddrwez                :  B19," &  
   "paclksel              :  K3," &  
   "emifa00               :  L1," &  
   "emifa01               :  W5," &  
   "emifa02               :  M2," &  
   "emifa03               :  N3," &  
   "emifa04               :  P3," &  
   "emifa05               :  T4," &  
   "emifa06               :  U4," &  
   "emifa07               :  R4," &  
   "emifa08               :  R3," &  
   "emifa09               :  W4," &  
   "emifa10               :  Y5," &  
   "emifa11               :  P2," &  
   "emifa12               :  N1," &  
   "emifa13               :  P1," &  
   "emifa14               :  R2," &  
   "emifa15               :  T2," &  
   "emifa16               :  U3," &  
   "emifa17               :  V3," &  
   "emifa18               :  Y4," &  
   "emifa19               :  T1," &  
   "emifa20               :  W3," &  
   "emifa21               :  V2," &  
   "emifa22               :  AA5," &  
   "emifa23               :  U1," &  
   "emifbe0z              :  K1," &  
   "emifbe1z              :  L2," &  
   "emifce0z              :  R5," &  
   "emifce1z              :  P5," &  
   "emifce2z              :  N5," &  
   "emifce3z              :  V5," &  
   "emifd00               :  V1," &  
   "emifd01               :  AA4," &  
   "emifd02               :  Y2," &  
   "emifd03               :  W2," &  
   "emifd04               :  AA3," &  
   "emifd05               :  Y1," &  
   "emifd06               :  AB1," &  
   "emifd07               :  AA1," &  
   "emifd08               :  AB2," &  
   "emifd09               :  AB3," &  
   "emifd10               :  AC2," &  
   "emifd11               :  AD1," &  
   "emifd12               :  AB4," &  
   "emifd13               :  AD2," &  
   "emifd14               :  AC3," &  
   "emifd15               :  AC4," &  
   "emifoez               :  L3," &  
   "emifrnw               :  U5," &  
   "emifwait0             :  N4," &  
   "emifwait1             :  M3," &  
   "emifwez               :  T5," &  
   "emu00                 :  AF28," &  
   "emu01                 :  AG28," &  
   "emu02                 :  AH29," &  
   "emu03                 :  AF27," &  
   "emu04                 :  AG27," &  
   "emu05                 :  AH28," &  
   "emu06                 :  AJ29," &  
   "emu07                 :  AK29," &  
   "emu08                 :  AJ28," &  
   "emu09                 :  AH26," &  
   "emu10                 :  AK28," &  
   "emu11                 :  AG26," &  
   "emu12                 :  AJ27," &  
   "emu13                 :  AK27," &  
   "emu14                 :  AJ26," &  
   "emu15                 :  AK26," &  
   "emu16                 :  AK25," &  
   "emu17                 :  AK24," &  
   "emu18                 :  AJ24," &  
   "rsv01                 :  AE21," &  
   "gpio00                :  AJ20," &  
   "gpio01                :  AF19," &  
   "gpio02                :  AG19," &  
   "gpio03                :  AH19," &  
   "gpio04                :  AK19," &  
   "gpio05                :  AJ19," &  
   "gpio06                :  AK18," &  
   "gpio07                :  AJ18," &  
   "gpio08                :  AH18," &  
   "gpio09                :  AG18," &  
   "gpio10                :  AF18," &  
   "gpio11                :  AK22," &  
   "gpio12                :  AJ21," &  
   "gpio13                :  AG20," &  
   "gpio14                :  AK21," &  
   "gpio15                :  AH20," &  
   "gpio16                :  AG23," &  
   "gpio17                :  AH24," &  
   "gpio18                :  AF21," &  
   "gpio19                :  AG21," &  
   "gpio20                :  AH23," &  
   "gpio21                :  AE19," &  
   "gpio22                :  AH22," &  
   "gpio23                :  AJ23," &  
   "gpio24                :  AJ22," &  
   "gpio25                :  AF20," &  
   "gpio26                :  AH21," &  
   "gpio27                :  AE20," &  
   "gpio28                :  AF23," &  
   "gpio29                :  AF22," &  
   "gpio30                :  AG24," &  
   "gpio31                :  AF24," &  
   "hout                  :  G4," &  
   "rsv14                 :  L25," &  
   "mcmclkn               :  E30," &  
   "mcmclkp               :  E29," &  
   "mcmrefclkoutn         :  G30," &  
   "mcmrefclkoutp         :  F30," &  
   "mcmrxflclk            :  G28," &  
   "mcmrxfldat            :  F29," &  
   "mcmrxn0               :  J30," &  
   "mcmrxn1               :  K29," &  
   "mcmrxn2               :  N29," &  
   "mcmrxn3               :  N30," &  
   "mcmrxp0               :  K30," &  
   "mcmrxp1               :  L29," &  
   "mcmrxp2               :  P29," &  
   "mcmrxp3               :  M30," &  
   "mcmrxpmclk            :  E28," &  
   "mcmrxpmdat            :  F28," &  
   "mcmtxflclk            :  G25," &  
   "mcmtxfldat            :  G27," &  
   "mcmtxn0               :  K26," &  
   "mcmtxn1               :  K27," &  
   "mcmtxn2               :  P27," &  
   "mcmtxn3               :  M26," &  
   "mcmtxp0               :  J26," &  
   "mcmtxp1               :  L27," &  
   "mcmtxp2               :  N27," &  
   "mcmtxp3               :  N26," &  
   "mcmtxpmclk            :  F26," &  
   "mcmtxpmdat            :  F27," &  
   "mdclk                 :  AF12," & 
   "mdio                  :  AD12," &  
   "paclkn                :  AK14," &  
   "paclkp                :  AJ14," &  
   "rsv22                 :  AD6," &  
   "rsv25                 :  AH11," &  
   "rsv24                 :  AH12," &  
   "rsv03                 :  J1," &  
   "rsv16                 :  AD5," &  
   "pcieclkn              :  AJ13," &  
   "pcieclkp              :  AK13," &  
   "pcierxn0              :  AK9," &  
   "pcierxn1              :  AJ10," &  
   "pcierxp0              :  AK8," &  
   "pcierxp1              :  AJ11," &  
   "pcietxn0              :  AG11," &  
   "pcietxn1              :  AH9," &  
   "pcietxp0              :  AG10," &  
   "pcietxp1              :  AH8," &  
   "rsv08                 :  H2," &  
   "rsv09                 :  F1," &  
   "ptv15                 :  K4," &  
   "radsync               :  AF29," &  
   "physync               :  AJ30," &  
   "nmiz                  :  J2," &  
   "porz                  :  AE22," &  
   "resetz                :  G2," &  
   "resetfullz            :  G1," &  
   "resetstatz            :  H4," &  
   "lresetnmienz          :  H1," &  
   "lresetz               :  F3," &  
   "riorxn0               :  AK6," &  
   "riorxn1               :  AJ5," &  
   "riorxn2               :  AK2," &  
   "riorxn3               :  AJ1," &  
   "riorxp0               :  AK5," &  
   "riorxp1               :  AJ4," &  
   "riorxp2               :  AK3," &  
   "riorxp3               :  AJ2," &  
   "riotxn0               :  AJ8," &  
   "riotxn1               :  AG7," &  
   "riotxn2               :  AH5," &  
   "riotxn3               :  AG4," &  
   "riotxp0               :  AJ7," &  
   "riotxp1               :  AG8," &  
   "riotxp2               :  AH6," &  
   "riotxp3               :  AG5," &  
   "rp1clkn               :  AE29," &  
   "rp1clkp               :  AF30," &  
   "rp1fbn                :  AH30," &  
   "rp1fbp                :  AG30," &  
   "scl                   :  AF17," &  
   "sda                   :  AE17," &  
   "rsv17                 :  AD4," &  
   "sgmiirxn0             :  AG1," &  
   "sgmiirxn1             :  AH2," &  
   "sgmiirxp0             :  AG2," &  
   "sgmiirxp1             :  AH3," &  
   "sgmiitxn0             :  AE3," &  
   "sgmiitxn1             :  AF2," &  
   "sgmiitxp0             :  AE4," &  
   "sgmiitxp1             :  AF3," &  
   "extframeevent         :  AE13," &  
   "spiclk                :  AH14," &  
   "spiscs0               :  AG15," &  
   "spiscs1               :  AF15," &  
-- "spiscs2               :  AK15," &  
   "spiscs3               :  AJ15," &  
   "spiscs4               :  AH15," &  
   "spisimo               :  AF14," &  
   "spisomi               :  AG14," &  
   "sriosgmiiclkn         :  AK11," &  
   "sriosgmiiclkp         :  AK12," &  
   "sysclkn               :  AD30," &  
   "sysclkp               :  AE30," &  
   "sysclkout             :  AD28," &  
   "tck                   :  AE28," &  
   "tdi                   :  AF26," &  
   "tms                   :  AE26," &  
   "trstz                 :  AE27," &  
   "tdo                   :  AD26," &  
   "timi0                 :  AJ25," &  
   "timi1                 :  AE25," &  
   "timo0                 :  AH25," &  
   "timo1                 :  AF25," &  
   "uart1cts              :  AK16," &  
   "uart1rts              :  AJ16," &  
   "uart1rxd              :  AF16," &  
   "uart1txd              :  AG16," &  
   "uartcts               :  AJ17," &  
   "uartrts               :  AK17," &  
   "uartrxd               :  AG17," &  
   "uarttxd               :  AH16," &  
   "usimclk               :  AH13," &  
   "usimio                :  AF13," &  
   "usimrst               :  AG13," &  
   "rsv29                 :  J28," &  
   "vcntl0                :  H28," &  
   "vcntl1                :  G26," &  
   "vcntl2                :  G29," &  
   "vcntl3                :  H29," &  
   "rsv30                 :  H27," &  

   "vdd                   :(AA11, AA13, AA15, AA17, AA19, AA21, AB12, AB14, AB16, AB18, AB20, AB8, AC9, K10, K12, K14, K16, K18, K20, K22," &
                          "K8, L11, L13, L15, L17, L19, M12, M14, M16, M18, M22, M8, N11, N13, N15, N17, N19, P10, P12, P14, P16, P18, P20," &
                          "P22, P8, R11, R13, R15, R17, R19, R21, R9, T10, T12, T14, T16, T18, T20, T22, T8, U11, U13, U15, U17, U19, U21," &
                          "U9, V10, V12, V14, V16, V18, V22, V8, W11, W13, W15, W17, W19, W9, Y12, Y14, Y16, Y18, Y22, Y8, AA9, AB10, L21," &
                          "L9, M10, M20, N21, N9, V20, W21, Y10, Y20, AA24, U24, N24, AF9, AC5, AE5, G11, G13, G15, G17, G19, G21, G7, G9," &
                          "H10, H12, H14, H16, H18, H20, H8, J11, J13, J15, J17, J19, J21, AB25, J5, AD14, G23, H22, H24, J23, AB22, AC13, AC15," &
                          "AC17, AC19, AC21, AC23, AD16, AD18, AD20, AD22, AE15, AA7, AB6, J7, J9, K6, L5, L7, M6, N7, P6, R7, T6, U7, V6," &
                          "W7, Y6, AA26, AB23, K23, K25, L24, M23, N25, P23, R24, R26, T23, T25, U26, V23, W24, W26, Y23, Y25, AC11, AD10," &
                          "AD8, AE11, AE7, AE9, AF10, AF6, AF8, H6, J6, F15)," &

   "vss                   :(A1, A12, A14, A17, A22, A25, A30, A5, A8, AA10, AA12, AA14, AA16, AA18, AA2, AA20, AA22, AA23, AA25, AA27, AA29," &
                          "AA6, AA8, AB11, AB13, AB15, AB17, AB19, AB21, AB24, AB26, AB5, AB7, AB9, AC1, AC10, AC12, AC14, AC16, AC18, AC20," &
                          "AC22, AC24, AC28, AC30, AC6, AC8, AD11, AD13, AD15, AD17, AD19, AD21, AD23, AD27, AD29, AD3, AD9, AE10, AE12, AE14," &
                          "AE16, AE18, AE2, AE6, AE8, AF1, AF11, AF4, AF5, AF7, AG12, AG22, AG25, AG29, AG3, AG6, AG9, AH1, AH10, AH17, AH27," &
                          "AH4, AH7, AJ12, AJ3, AJ6, AJ9, AK1, AK10, AK20, AK23, AK30, AK4, AK7, C10, C13, C16, C19, C2, C21, C24, C29, C4, C7," &
                          "E12, E15, E18, E20, E23, E27, E3, E6, E9, F11, F25, F4, G10, G12, G14, G16, G18, G20, G22, G24, G5, G8, H11, H13, H15, H17," &
                          "H19, H21, H23, H26, H30, H7, H9, J10, J12, J14, J16, J18, J20, J22, J25, J27, J29, J3, J8, K11, K13, K15, K17, K19," & 
                          "K2, K21, K24, K28, K5, K7, K9, L10, L12, L14, L16, L18, L20, L22, L23, L26, L28, L30, L4, L6, L8, M1, M11, M13, M15," &
                          "M17, M19, M21, M24, M25, M27, M28, M29, M4, M5, M7, M9, N10, N12, N14, N16, N18, N2, N20, N22, N23, N28, N6, N8, P11, P13," &
                          "P15, P17, P19, P21, P24, P25, P26, P28, P30, P4, P7, P9, R1, R10, R12, R14, R16, R18, R20, R22, R23, R27, R29, R6, R8," &
                          "T11, T13, T15, T17, T19, T21, T24, T26, T3, T7, T9, U10, U12, U14, U16, U18, U2, U20, U22, U23, U25, U28, U30, U6, U8," &
                          "V11, V13, V15, V17, V19, V21, V24, V26, V27, V29, V4, V7, V9, W1, W10, W12, W14, W16, W18, W20, W22, W23, W25, W6, W8," &
                          "Y11, Y13, Y15, Y17, Y19, Y21, Y24, Y26, Y28, Y3, Y30, Y7, Y9)";

 attribute PORT_GROUPING of tms320tci6614 : entity is
    "Differential_Voltage  (            "&
    "(mcmtxp0, mcmtxn0),                "&
    "(mcmtxp1, mcmtxn1),                "&
    "(mcmtxp2, mcmtxn2),                "&
    "(mcmtxp3, mcmtxn3),                "&
    "(riotxp0, riotxn0),                "&
    "(riotxp1, riotxn1),                "&
    "(riotxp2, riotxn2),                "&
    "(riotxp3, riotxn3),                "&
    "(pcietxp0, pcietxn0),              "&
    "(pcietxp1, pcietxn1),              "&
    "(sgmiitxp0, sgmiitxn0),            "&
    "(sgmiitxp1, sgmiitxn1),            "&
    "(aiftxp0, aiftxn0),                "&
    "(aiftxp1, aiftxn1),                "&
    "(aiftxp2, aiftxn2),                "&
    "(aiftxp3, aiftxn3),                "&
    "(aiftxp4, aiftxn4),                "&
    "(aiftxp5, aiftxn5),                "&
    "(rp1clkp, rp1clkn),                "&
    "(rp1fbp, rp1fbn),                  "&
    "(sysclkp, sysclkn),                "&
    "(paclkp, paclkn),                  "&
    "(altcoreclkp, altcoreclkn),        "&
    "(sriosgmiiclkp, sriosgmiiclkn),    "&
    "(ddrclkp, ddrclkn),                "&
    "(pcieclkp, pcieclkn),              "&
    "(mcmclkp, mcmclkn),                "&
    "(ddrdqs8p, ddrdqs8n),              "&
    "(ddrdqs7p, ddrdqs7n),              "&
    "(ddrdqs6p, ddrdqs6n),              "&
    "(ddrdqs5p, ddrdqs5n),              "&
    "(ddrdqs4p, ddrdqs4n),              "&
    "(ddrdqs3p, ddrdqs3n),              "&
    "(ddrdqs2p, ddrdqs2n),              "&
    "(ddrdqs1p, ddrdqs1n),              "&
    "(ddrdqs0p, ddrdqs0n),              "&
    "(rsv04, rsv05),                    "&
    "(rsv06, rsv07),                    "&
    "(rsv24, rsv25))                    ";

attribute TAP_SCAN_IN    of tdi    : signal is true;
attribute TAP_SCAN_MODE  of tms    : signal is true;
attribute TAP_SCAN_OUT   of tdo    : signal is true;
attribute TAP_SCAN_CLOCK of tck    : signal is (20.0e6,BOTH);
attribute TAP_SCAN_RESET of trstz  : signal is true;

attribute COMPLIANCE_PATTERNS of tms320tci6614 : entity is "(porz, resetfullz)(11)";
attribute INSTRUCTION_LENGTH  of tms320tci6614 : entity is 6;
attribute INSTRUCTION_OPCODE  of tms320tci6614 : entity is
      "private_0       (000010),      "&
      "IDCODE          (000100),      "&
      "private_1       (000101),      "&
      "private_2       (000111),      "&
      "private_3       (001000),      "&
      "private_4       (010111),      "&
      "EXTEST          (011000),      "&
      "private_5       (011001),      "&
      "private_6       (011010),      "&
      "SAMPLE          (011011),      "&
      "PRELOAD         (011100),      "&
      "private_7       (011101),      "&
      "private_8       (011110),      "&
      "private_9       (011111),      "&
      "EXTEST_PULSE    (100100),      "&
      "EXTEST_TRAIN    (100101),      "&
      "private_a       (110001),      "&
      "BYPASS          (000000,111111)";

 attribute INSTRUCTION_CAPTURE of tms320tci6614 : entity is "000001";

 attribute INSTRUCTION_PRIVATE of tms320tci6614 : entity is
      "private_0,    " &
      "private_1,    " &
      "private_2,    " &
      "private_3,    " &
      "private_4,    " &
      "private_5,    " &
      "private_6,    " &
      "private_7,    " &
      "private_8,    " &
      "private_9,    " &
      "EXTEST_PULSE, " &
      "EXTEST_TRAIN, " &
      "private_a";

 attribute IDCODE_REGISTER     of tms320tci6614 : entity is
      "0000" &
      "1011100101100010" &
      "00000010111" &
      "1";
 attribute REGISTER_ACCESS of tms320tci6614 : entity is
      "BOUNDARY      (EXTEST),          "&
      "BOUNDARY      (SAMPLE),          "&
      "BOUNDARY      (PRELOAD),         "&
      "DEVICE_ID     (IDCODE),          "&
      "GEN_REG1[1]   (private_0),      "&
      "GEN_REG32[32] (private_1),      "&
      "GEN_REG8[8]   (private_2),      "&
      "GEN_REG32[32] (private_3),      "&
      "GEN_REG1[1]   (private_4),      "&
      "GEN_REG1[1]   (private_5),      "&
      "GEN_REG1[1]   (private_6),      "&
      "GEN_REG1[1]   (private_7),      "&
      "GEN_REG1[1]   (private_8),      "&
      "GEN_REG1[1]   (private_9),      "&
      "BOUNDARY      (EXTEST_PULSE),    "&
      "BOUNDARY      (EXTEST_TRAIN),    "&
      "GEN_REG1[1]   (private_a),      "&
      "BYPASS        (BYPASS)           ";

  attribute BOUNDARY_LENGTH of tms320tci6614 : entity is 622;

attribute BOUNDARY_REGISTER of tms320tci6614 : entity is
     " 621 (BC_7, emu00         ,  bidir          , X,  620, 1, PULL1  ),"&
     " 620 (BC_2, *             ,  control        , 1                  ),"&
     " 619 (BC_7, emu01         ,  bidir          , X,  618, 1, PULL1  ),"&
     " 618 (BC_2, *             ,  control        , 1                  ),"&
     " 617 (BC_7, emu02         ,  bidir          , X,  616, 1, PULL1  ),"&
     " 616 (BC_2, *             ,  control        , 1                  ),"&
     " 615 (BC_7, emu03         ,  bidir          , X,  614, 1, PULL1  ),"&
     " 614 (BC_2, *             ,  control        , 1                  ),"&
     " 613 (BC_7, emu04         ,  bidir          , X,  612, 1, PULL1  ),"&
     " 612 (BC_2, *             ,  control        , 1                  ),"&
     " 611 (BC_7, emu05         ,  bidir          , X,  610, 1, PULL1  ),"&
     " 610 (BC_2, *             ,  control        , 1                  ),"&
     " 609 (BC_7, emu06         ,  bidir          , X,  608, 1, PULL1  ),"&
     " 608 (BC_2, *             ,  control        , 1                  ),"&
     " 607 (BC_7, emu07         ,  bidir          , X,  606, 1, PULL1  ),"&
     " 606 (BC_2, *             ,  control        , 1                  ),"&
     " 605 (BC_7, emu08         ,  bidir          , X,  604, 1, PULL1  ),"&
     " 604 (BC_2, *             ,  control        , 1                  ),"&
     " 603 (BC_7, emu09         ,  bidir          , X,  602, 1, PULL1  ),"&
     " 602 (BC_2, *             ,  control        , 1                  ),"&
     " 601 (BC_7, emu10         ,  bidir          , X,  600, 1, PULL1  ),"&
     " 600 (BC_2, *             ,  control        , 1                  ),"&
     " 599 (BC_7, emu11         ,  bidir          , X,  598, 1, PULL1  ),"&
     " 598 (BC_2, *             ,  control        , 1                  ),"&
     " 597 (BC_7, emu12         ,  bidir          , X,  596, 1, PULL1  ),"&
     " 596 (BC_2, *             ,  control        , 1                  ),"&
     " 595 (BC_7, emu13         ,  bidir          , X,  594, 1, PULL1  ),"&
     " 594 (BC_2, *             ,  control        , 1                  ),"&
     " 593 (BC_7, emu14         ,  bidir          , X,  592, 1, PULL1  ),"&
     " 592 (BC_2, *             ,  control        , 1                  ),"&
     " 591 (BC_7, emu15         ,  bidir          , X,  590, 1, PULL1  ),"&
     " 590 (BC_2, *             ,  control        , 1                  ),"&
     " 589 (BC_7, emu16         ,  bidir          , X,  588, 1, PULL1  ),"&
     " 588 (BC_2, *             ,  control        , 1                  ),"&
     " 587 (BC_7, emu17         ,  bidir          , X,  586, 1, PULL1  ),"&
     " 586 (BC_2, *             ,  control        , 1                  ),"&
     " 585 (BC_7, emu18         ,  bidir          , X,  584, 1, PULL1  ),"&
     " 584 (BC_2, *             ,  control        , 1                  ),"&
     " 583 (BC_7, rsv01         ,  bidir          , X,  582, 1, PULL1  ),"&
     " 582 (BC_2, *             ,  control        , 1                  ),"&
     " 581 (BC_7, timi0         ,  bidir          , X,  580, 1, PULL0  ),"&
     " 580 (BC_2, *             ,  control        , 1                  ),"&
     " 579 (BC_7, timi1         ,  bidir          , X,  578, 1, PULL0  ),"&
     " 578 (BC_2, *             ,  control        , 1                  ),"&
     " 577 (BC_7, timo0         ,  bidir          , X,  576, 1, PULL0  ),"&
     " 576 (BC_2, *             ,  control        , 1                  ),"&
     " 575 (BC_7, timo1         ,  bidir          , X,  574, 1, PULL0  ),"&
     " 574 (BC_2, *             ,  control        , 1                  ),"&
     " 573 (BC_7, gpio00        ,  bidir          , X,  572, 1, PULL1  ),"&
     " 572 (BC_2, *             ,  control        , 1                  ),"&
     " 571 (BC_7, gpio01        ,  bidir          , X,  570, 1, PULL0  ),"&
     " 570 (BC_2, *             ,  control        , 1                  ),"&
     " 569 (BC_7, gpio02        ,  bidir          , X,  568, 1, PULL0  ),"&
     " 568 (BC_2, *             ,  control        , 1                  ),"&
     " 567 (BC_7, gpio03        ,  bidir          , X,  566, 1, PULL0  ),"&
     " 566 (BC_2, *             ,  control        , 1                  ),"&
     " 565 (BC_7, gpio04        ,  bidir          , X,  564, 1, PULL0  ),"&
     " 564 (BC_2, *             ,  control        , 1                  ),"&
     " 563 (BC_7, gpio05        ,  bidir          , X,  562, 1, PULL0  ),"&
     " 562 (BC_2, *             ,  control        , 1                  ),"&
     " 561 (BC_7, gpio06        ,  bidir          , X,  560, 1, PULL0  ),"&
     " 560 (BC_2, *             ,  control        , 1                  ),"&
     " 559 (BC_7, gpio07        ,  bidir          , X,  558, 1, PULL0  ),"&
     " 558 (BC_2, *             ,  control        , 1                  ),"&
     " 557 (BC_7, gpio08        ,  bidir          , X,  556, 1, PULL0  ),"&
     " 556 (BC_2, *             ,  control        , 1                  ),"&
     " 555 (BC_7, gpio09        ,  bidir          , X,  554, 1, PULL0  ),"&
     " 554 (BC_2, *             ,  control        , 1                  ),"&
     " 553 (BC_7, gpio10        ,  bidir          , X,  552, 1, PULL0  ),"&
     " 552 (BC_2, *             ,  control        , 1                  ),"&
     " 551 (BC_7, gpio11        ,  bidir          , X,  550, 1, PULL0  ),"&
     " 550 (BC_2, *             ,  control        , 1                  ),"&
     " 549 (BC_7, gpio12        ,  bidir          , X,  548, 1, PULL0  ),"&
     " 548 (BC_2, *             ,  control        , 1                  ),"&
     " 547 (BC_7, gpio13        ,  bidir          , X,  546, 1, PULL0  ),"&
     " 546 (BC_2, *             ,  control        , 1                  ),"&
     " 545 (BC_7, gpio14        ,  bidir          , X,  544, 1, PULL0  ),"&
     " 544 (BC_2, *             ,  control        , 1                  ),"&
     " 543 (BC_7, gpio15        ,  bidir          , X,  542, 1, PULL0  ),"&
     " 542 (BC_2, *             ,  control        , 1                  ),"&
     " 541 (BC_7, gpio16        ,  bidir          , X,  540, 1, PULL0  ),"&
     " 540 (BC_2, *             ,  control        , 1                  ),"&
     " 539 (BC_7, gpio17        ,  bidir          , X,  538, 1, PULL1  ),"&
     " 538 (BC_2, *             ,  control        , 1                  ),"&
     " 537 (BC_7, gpio18        ,  bidir          , X,  536, 1, PULL1  ),"&
     " 536 (BC_2, *             ,  control        , 1                  ),"&
     " 535 (BC_7, gpio19        ,  bidir          , X,  534, 1, PULL1  ),"&
     " 534 (BC_2, *             ,  control        , 1                  ),"&
     " 533 (BC_7, gpio20        ,  bidir          , X,  532, 1, PULL1  ),"&
     " 532 (BC_2, *             ,  control        , 1                  ),"&
     " 531 (BC_7, gpio21        ,  bidir          , X,  530, 1, PULL1  ),"&
     " 530 (BC_2, *             ,  control        , 1                  ),"&
     " 529 (BC_7, gpio22        ,  bidir          , X,  528, 1, PULL1  ),"&
     " 528 (BC_2, *             ,  control        , 1                  ),"&
     " 527 (BC_7, gpio23        ,  bidir          , X,  526, 1, PULL1  ),"&
     " 526 (BC_2, *             ,  control        , 1                  ),"&
     " 525 (BC_7, gpio24        ,  bidir          , X,  524, 1, PULL1  ),"&
     " 524 (BC_2, *             ,  control        , 1                  ),"&
     " 523 (BC_7, gpio25        ,  bidir          , X,  522, 1, PULL1  ),"&
     " 522 (BC_2, *             ,  control        , 1                  ),"&
     " 521 (BC_7, gpio26        ,  bidir          , X,  520, 1, PULL1  ),"&
     " 520 (BC_2, *             ,  control        , 1                  ),"&
     " 519 (BC_7, gpio27        ,  bidir          , X,  518, 1, PULL1  ),"&
     " 518 (BC_2, *             ,  control        , 1                  ),"&
     " 517 (BC_7, gpio28        ,  bidir          , X,  516, 1, PULL1  ),"&
     " 516 (BC_2, *             ,  control        , 1                  ),"&
     " 515 (BC_7, gpio29        ,  bidir          , X,  514, 1, PULL1  ),"&
     " 514 (BC_2, *             ,  control        , 1                  ),"&
     " 513 (BC_7, gpio30        ,  bidir          , X,  512, 1, PULL1  ),"&
     " 512 (BC_2, *             ,  control        , 1                  ),"&
     " 511 (BC_7, gpio31        ,  bidir          , X,  510, 1, PULL1  ),"&
     " 510 (BC_2, *             ,  control        , 1                  ),"&
     " 509 (BC_1, scl           ,  output2        , 1,  509, 1, WEAK1  ),"&
     " 508 (BC_1, *             ,  internal       , 0                  ),"&
     " 507 (BC_3, scl           ,  input          , X                  ),"&
     " 506 (BC_1, sda           ,  output2        , 1,  506, 1, WEAK1  ),"&
     " 505 (BC_1, *             ,  internal       , 0                  ),"&
     " 504 (BC_3, sda           ,  input          , X                  ),"&
     " 503 (BC_7, mdio          ,  bidir          , X,  502 , 1, PULL1 ),"&
     " 502 (BC_2, *             ,  control        , 1                  ),"&
     " 501 (BC_7, mdclk         ,  bidir          , X,  500 , 1, PULL0 ),"&
     " 500 (BC_2, *             ,  control        , 1                  ),"&
     " 499 (BC_7, usimrst       ,  bidir          , X,  498 , 1, PULL0 ),"&
     " 498 (BC_2, *             ,  control        , 1                  ),"&
     " 497 (BC_7, usimclk       ,  bidir          , X,  496 , 1, PULL0 ),"&
     " 496 (BC_2, *             ,  control        , 1                  ),"&
     " 495 (BC_7, usimio        ,  bidir          , X,  494 , 1, PULL0 ),"&
     " 494 (BC_2, *             ,  control        , 1                  ),"&
     " 493 (BC_7, uartrxd       ,  bidir          , X,  492 , 1, PULL0 ),"&
     " 492 (BC_2, *             ,  control        , 1                  ),"&
     " 491 (BC_7, uarttxd       ,  bidir          , X,  490 , 1, PULL0 ),"&
     " 490 (BC_2, *             ,  control        , 1                  ),"&
     " 489 (BC_7, uartcts       ,  bidir          , X,  488 , 1, PULL0 ),"&
     " 488 (BC_2, *             ,  control        , 1                  ),"&
     " 487 (BC_7, uartrts       ,  bidir          , X,  486 , 1, PULL0 ),"&
     " 486 (BC_2, *             ,  control        , 1                  ),"&
     " 485 (BC_7, uart1rxd      ,  bidir          , X,  484 , 1, PULL0 ),"&
     " 484 (BC_2, *             ,  control        , 1                  ),"&
     " 483 (BC_7, uart1txd      ,  bidir          , X,  482 , 1, PULL0 ),"&
     " 482 (BC_2, *             ,  control        , 1                  ),"&
     " 481 (BC_7, uart1cts      ,  bidir          , X,  480 , 1, PULL0 ),"&
     " 480 (BC_2, *             ,  control        , 1                  ),"&
     " 479 (BC_7, uart1rts      ,  bidir          , X,  478 , 1, PULL0 ),"&
     " 478 (BC_2, *             ,  control        , 1                  ),"&
     " 477 (BC_7, extframeevent ,  bidir          , X,  476 , 1, PULL0 ),"&
     " 476 (BC_2, *             ,  control        , 1                  ),"&
     " 475 (BC_7, spiscs0       ,  bidir          , X,  474, 1, PULL1  ),"&
     " 474 (BC_2, *             ,  control        , 1                  ),"&
     " 473 (BC_7, spiscs1       ,  bidir          , X,  472, 1, PULL1  ),"&
     " 472 (BC_2, *             ,  control        , 1                  ),"&
     " 471 (BC_2, *             ,  internal       , X                  ),"&
     " 470 (BC_2, *             ,  internal       , X                  ),"&
     " 469 (BC_7, spiscs3       ,  bidir          , X,  468, 1, PULL1  ),"&
     " 468 (BC_2, *             ,  control        , 1                  ),"&
     " 467 (BC_7, spiscs4       ,  bidir          , X,  466, 1, PULL1  ),"&
     " 466 (BC_2, *             ,  control        , 1                  ),"&
     " 465 (BC_7, spiclk        ,  bidir          , X,  464, 1, PULL0  ),"&
     " 464 (BC_2, *             ,  control        , 1                  ),"&
     " 463 (BC_7, spisomi       ,  bidir          , X,  462, 1, PULL0  ),"&
     " 462 (BC_2, *             ,  control        , 1                  ),"&
     " 461 (BC_7, spisimo       ,  bidir          , X,  460, 1, PULL0  ),"&
     " 460 (BC_2, *             ,  control        , 1                  ),"&
     " 459 (BC_1, rsv24         ,  output2        , X                  ),"&
     " 458 (BC_7, rsv22         ,  bidir          , X,  457, 1, PULL0  ),"&
     " 457 (BC_2, *             ,  control        , 1                  ),"&
     " 456 (BC_1, paclkp        ,  input          , X                  ),"&
     " 455 (BC_1, pcieclkp      ,  input          , X                  ),"&
     " 454 (BC_1, sriosgmiiclkp ,  input          , X                  ),"&
     " 453 (BC_4, *             ,  internal       , X                  ),"&
     " 452 (BC_4, pcierxn0      ,  observe_only   , X                  ),"&
     " 451 (BC_4, pcierxp0      ,  observe_only   , X                  ),"&
     " 450 (BC_4, pcierxn1      ,  observe_only   , X                  ),"&
     " 449 (BC_4, pcierxp1      ,  observe_only   , X                  ),"&
     " 448 (BC_1, pcietxp0      ,  output2        , X                  ),"&
     " 447 (BC_1, pcietxp1      ,  output2        , X                  ),"&
     " 446 (BC_4, sgmiirxn0     ,  observe_only   , X                  ),"&
     " 445 (BC_4, sgmiirxp0     ,  observe_only   , X                  ),"&
     " 444 (BC_4, sgmiirxn1     ,  observe_only   , X                  ),"&
     " 443 (BC_4, sgmiirxp1     ,  observe_only   , X                  ),"&
     " 442 (BC_1, sgmiitxp0     ,  output2        , X                  ),"&
     " 441 (BC_1, sgmiitxp1     ,  output2        , X                  ),"&
     " 440 (BC_4, riorxn0       ,  observe_only   , X                  ),"&
     " 439 (BC_4, riorxp0       ,  observe_only   , X                  ),"&
     " 438 (BC_4, riorxn1       ,  observe_only   , X                  ),"&
     " 437 (BC_4, riorxp1       ,  observe_only   , X                  ),"&
     " 436 (BC_4, riorxn2       ,  observe_only   , X                  ),"&
     " 435 (BC_4, riorxp2       ,  observe_only   , X                  ),"&
     " 434 (BC_4, riorxn3       ,  observe_only   , X                  ),"&
     " 433 (BC_4, riorxp3       ,  observe_only   , X                  ),"&
     " 432 (BC_1, riotxp0       ,  output2        , X                  ),"&
     " 431 (BC_1, riotxp1       ,  output2        , X                  ),"&
     " 430 (BC_1, riotxp2       ,  output2        , X                  ),"&
     " 429 (BC_1, riotxp3       ,  output2        , X                  ),"&
     " 428 (BC_7, emifd00       ,  bidir          , X,  427 , 1, PULL0 ),"&
     " 427 (BC_2, *             ,  control        , 1                  ),"&
     " 426 (BC_7, emifd01       ,  bidir          , X,  425 , 1, PULL0 ),"&
     " 425 (BC_2, *             ,  control        , 1                  ),"&
     " 424 (BC_7, emifd02       ,  bidir          , X,  423 , 1, PULL0 ),"&
     " 423 (BC_2, *             ,  control        , 1                  ),"&
     " 422 (BC_7, emifd03       ,  bidir          , X,  421 , 1, PULL0 ),"&
     " 421 (BC_2, *             ,  control        , 1                  ),"&
     " 420 (BC_7, emifd04       ,  bidir          , X,  419 , 1, PULL0 ),"&
     " 419 (BC_2, *             ,  control        , 1                  ),"&
     " 418 (BC_7, emifd05       ,  bidir          , X,  417 , 1, PULL0 ),"&
     " 417 (BC_2, *             ,  control        , 1                  ),"&
     " 416 (BC_7, emifd06       ,  bidir          , X,  415 , 1, PULL0 ),"&
     " 415 (BC_2, *             ,  control        , 1                  ),"&
     " 414 (BC_7, emifd07       ,  bidir          , X,  413 , 1, PULL0 ),"&
     " 413 (BC_2, *             ,  control        , 1                  ),"&
     " 412 (BC_7, emifd08       ,  bidir          , X,  411 , 1, PULL0 ),"&
     " 411 (BC_2, *             ,  control        , 1                  ),"&
     " 410 (BC_7, emifd09       ,  bidir          , X,  409 , 1, PULL0 ),"&
     " 409 (BC_2, *             ,  control        , 1                  ),"&
     " 408 (BC_7, emifd10       ,  bidir          , X,  407 , 1, PULL0 ),"&
     " 407 (BC_2, *             ,  control        , 1                  ),"&
     " 406 (BC_7, emifd11       ,  bidir          , X,  405 , 1, PULL0 ),"&
     " 405 (BC_2, *             ,  control        , 1                  ),"&
     " 404 (BC_7, emifd12       ,  bidir          , X,  403 , 1, PULL0 ),"&
     " 403 (BC_2, *             ,  control        , 1                  ),"&
     " 402 (BC_7, emifd13       ,  bidir          , X,  401 , 1, PULL0 ),"&
     " 401 (BC_2, *             ,  control        , 1                  ),"&
     " 400 (BC_7, emifd14       ,  bidir          , X,  399 , 1, PULL0 ),"&
     " 399 (BC_2, *             ,  control        , 1                  ),"&
     " 398 (BC_7, emifd15       ,  bidir          , X,  397 , 1, PULL0 ),"&
     " 397 (BC_2, *             ,  control        , 1                  ),"&
     " 396 (BC_7, emifa00       ,  bidir          , X,  395 , 1, PULL0 ),"&
     " 395 (BC_2, *             ,  control        , 1                  ),"&
     " 394 (BC_7, emifa01       ,  bidir          , X,  393 , 1, PULL0 ),"&
     " 393 (BC_2, *             ,  control        , 1                  ),"&
     " 392 (BC_7, emifa02       ,  bidir          , X,  391 , 1, PULL0 ),"&
     " 391 (BC_2, *             ,  control        , 1                  ),"&
     " 390 (BC_7, emifa03       ,  bidir          , X,  389 , 1, PULL0 ),"&
     " 389 (BC_2, *             ,  control        , 1                  ),"&
     " 388 (BC_7, emifa04       ,  bidir          , X,  387 , 1, PULL0 ),"&
     " 387 (BC_2, *             ,  control        , 1                  ),"&
     " 386 (BC_7, emifa05       ,  bidir          , X,  385 , 1, PULL0 ),"&
     " 385 (BC_2, *             ,  control        , 1                  ),"&
     " 384 (BC_7, emifa06       ,  bidir          , X,  383 , 1, PULL0 ),"&
     " 383 (BC_2, *             ,  control        , 1                  ),"&
     " 382 (BC_7, emifa07       ,  bidir          , X,  381 , 1, PULL0 ),"&
     " 381 (BC_2, *             ,  control        , 1                  ),"&
     " 380 (BC_7, emifa08       ,  bidir          , X,  379 , 1, PULL0 ),"&
     " 379 (BC_2, *             ,  control        , 1                  ),"&
     " 378 (BC_7, emifa09       ,  bidir          , X,  377 , 1, PULL0 ),"&
     " 377 (BC_2, *             ,  control        , 1                  ),"&
     " 376 (BC_7, emifa10       ,  bidir          , X,  375 , 1, PULL0 ),"&
     " 375 (BC_2, *             ,  control        , 1                  ),"&
     " 374 (BC_7, emifa11       ,  bidir          , X,  373 , 1, PULL0 ),"&
     " 373 (BC_2, *             ,  control        , 1                  ),"&
     " 372 (BC_7, emifa12       ,  bidir          , X,  371 , 1, PULL0 ),"&
     " 371 (BC_2, *             ,  control        , 1                  ),"&
     " 370 (BC_7, emifa13       ,  bidir          , X,  369 , 1, PULL0 ),"&
     " 369 (BC_2, *             ,  control        , 1                  ),"&
     " 368 (BC_7, emifa14       ,  bidir          , X,  367 , 1, PULL0 ),"&
     " 367 (BC_2, *             ,  control        , 1                  ),"&
     " 366 (BC_7, emifa15       ,  bidir          , X,  365 , 1, PULL0 ),"&
     " 365 (BC_2, *             ,  control        , 1                  ),"&
     " 364 (BC_7, emifa16       ,  bidir          , X,  363 , 1, PULL0 ),"&
     " 363 (BC_2, *             ,  control        , 1                  ),"&
     " 362 (BC_7, emifa17       ,  bidir          , X,  361 , 1, PULL0 ),"&
     " 361 (BC_2, *             ,  control        , 1                  ),"&
     " 360 (BC_7, emifa18       ,  bidir          , X,  359 , 1, PULL0 ),"&
     " 359 (BC_2, *             ,  control        , 1                  ),"&
     " 358 (BC_7, emifa19       ,  bidir          , X,  357 , 1, PULL0 ),"&
     " 357 (BC_2, *             ,  control        , 1                  ),"&
     " 356 (BC_7, emifa20       ,  bidir          , X,  355 , 1, PULL0 ),"&
     " 355 (BC_2, *             ,  control        , 1                  ),"&
     " 354 (BC_7, emifa21       ,  bidir          , X,  353 , 1, PULL0 ),"&
     " 353 (BC_2, *             ,  control        , 1                  ),"&
     " 352 (BC_7, emifa22       ,  bidir          , X,  351 , 1, PULL0 ),"&
     " 351 (BC_2, *             ,  control        , 1                  ),"&
     " 350 (BC_7, emifa23       ,  bidir          , X,  349 , 1, PULL0 ),"&
     " 349 (BC_2, *             ,  control        , 1                  ),"&
     " 348 (BC_7, emifrnw       ,  bidir          , X,  347 , 1, PULL1 ),"&
     " 347 (BC_2, *             ,  control        , 1                  ),"&
     " 346 (BC_7, emifce0z      ,  bidir          , X,  345 , 1, PULL1 ),"&
     " 345 (BC_2, *             ,  control        , 1                  ),"&
     " 344 (BC_7, emifce1z      ,  bidir          , X,  343 , 1, PULL1 ),"&
     " 343 (BC_2, *             ,  control        , 1                  ),"&
     " 342 (BC_7, emifce2z      ,  bidir          , X,  341 , 1, PULL1 ),"&
     " 341 (BC_2, *             ,  control        , 1                  ),"&
     " 340 (BC_7, emifce3z      ,  bidir          , X,  339 , 1, PULL1 ),"&
     " 339 (BC_2, *             ,  control        , 1                  ),"&
     " 338 (BC_7, emifoez       ,  bidir          , X,  337 , 1, PULL1 ),"&
     " 337 (BC_2, *             ,  control        , 1                  ),"&
     " 336 (BC_7, emifwez       ,  bidir          , X,  335 , 1, PULL1 ),"&
     " 335 (BC_2, *             ,  control        , 1                  ),"&
     " 334 (BC_7, emifbe0z      ,  bidir          , X,  333 , 1, PULL1 ),"&
     " 333 (BC_2, *             ,  control        , 1                  ),"&
     " 332 (BC_7, emifbe1z      ,  bidir          , X,  331 , 1, PULL1 ),"&
     " 331 (BC_2, *             ,  control        , 1                  ),"&
     " 330 (BC_7, emifwait0     ,  bidir          , X,  329 , 1, PULL0 ),"&
     " 329 (BC_2, *             ,  control        , 1                  ),"&
     " 328 (BC_7, emifwait1     ,  bidir          , X,  327 , 1, PULL0 ),"&
     " 327 (BC_2, *             ,  control        , 1                  ),"&
     " 326 (BC_7, coresel0      ,  bidir          , X,  325, 1, PULL0  ),"&
     " 325 (BC_2, *             ,  control        , 1                  ),"&
     " 324 (BC_7, coresel1      ,  bidir          , X,  323, 1, PULL0  ),"&
     " 323 (BC_2, *             ,  control        , 1                  ),"&
     " 322 (BC_7, coresel2      ,  bidir          , X,  321, 1, PULL0  ),"&
     " 321 (BC_2, *             ,  control        , 1                  ),"&
     " 320 (BC_7, resetstatz    ,  bidir          , X,  319, 1, PULL1  ),"&
     " 319 (BC_2, *             ,  control        , 1                  ),"&
     " 318 (BC_7, lresetz       ,  bidir          , X,  317, 1, PULL1  ),"&
     " 317 (BC_2, *             ,  control        , 1                  ),"&
     " 316 (BC_1, resetz        ,  input          , X                  ),"&
     " 315 (BC_7, lresetnmienz  ,  bidir          , X,  314, 1, PULL1  ),"&
     " 314 (BC_2, *             ,  control        , 1                  ),"&
     " 313 (BC_7, bootcomplete  ,  bidir          , X,  312, 1, PULL0  ),"&
     " 312 (BC_2, *             ,  control        , 1                  ),"&
     " 311 (BC_7, paclksel      ,  bidir          , X,  310, 1, PULL0  ),"&
     " 310 (BC_2, *             ,  control        , 1                  ),"&
     " 309 (BC_7, rsv03         ,  bidir          , X,  308, 1, PULL0  ),"&
     " 308 (BC_2, *             ,  control        , 1                  ),"&
     " 307 (BC_7, hout          ,  bidir          , X,  306, 1, PULL1  ),"&
     " 306 (BC_2, *             ,  control        , 1                  ),"&
     " 305 (BC_7, nmiz          ,  bidir          , X,  304, 1, PULL1  ),"&
     " 304 (BC_2, *             ,  control        , 1                  ),"&
     " 303 (BC_1, ddrclkp       ,  input          , X                  ),"&
     " 302 (BC_7, ddrslrate0    ,  bidir          , X,  301, 1, PULL0  ),"&
     " 301 (BC_2, *             ,  control        , 1                  ),"&
     " 300 (BC_7, ddrslrate1    ,  bidir          , X,  299, 1, PULL0  ),"&
     " 299 (BC_2, *             ,  control        , 1                  ),"&
     " 298 (BC_1, rsv06         ,  output2        , X                  ),"&
     " 297 (BC_7, rsv21         ,  bidir          , X,  296, 1, PULL0  ),"&
     " 296 (BC_2, *             ,  control        , 1                  ),"&
     " 295 (BC_7, ddrresetz     ,  bidir          , X,  294 , 1, Z     ),"&
     " 294 (BC_2, *             ,  control        , 1                  ),"&
     " 293 (BC_7, ddrcke0       ,  bidir          , X,  294 , 1, Z     ),"&
     " 292 (BC_7, ddrce0z       ,  bidir          , X,  294 , 1, Z     ),"&
     " 291 (BC_7, ddrce1z       ,  bidir          , X,  294 , 1, Z     ),"&
     " 290 (BC_7, ddrclkoutp0   ,  bidir          , X,  294 , 1, Z     ),"&
     " 289 (BC_7, ddrclkoutn0   ,  bidir          , X,  294 , 1, Z     ),"&
     " 288 (BC_7, ddrrasz       ,  bidir          , X,  294 , 1, Z     ),"&
     " 287 (BC_7, ddrcasz       ,  bidir          , X,  294 , 1, Z     ),"&
     " 286 (BC_7, ddrwez        ,  bidir          , X,  294 , 1, Z     ),"&
     " 285 (BC_7, ddrodt0       ,  bidir          , X,  294 , 1, Z     ),"&
     " 284 (BC_7, ddrodt1       ,  bidir          , X,  294 , 1, Z     ),"&
     " 283 (BC_7, ddrba0        ,  bidir          , X,  282 , 1, Z     ),"&
     " 282 (BC_2, *             ,  control        , 1                  ),"&
     " 281 (BC_7, ddrba1        ,  bidir          , X,  282 , 1, Z     ),"&
     " 280 (BC_7, ddrba2        ,  bidir          , X,  282 , 1, Z     ),"&
     " 279 (BC_7, ddra00        ,  bidir          , X,  282 , 1, Z     ),"&
     " 278 (BC_7, ddra01        ,  bidir          , X,  282 , 1, Z     ),"&
     " 277 (BC_7, ddra02        ,  bidir          , X,  282 , 1, Z     ),"&
     " 276 (BC_7, ddra03        ,  bidir          , X,  282 , 1, Z     ),"&
     " 275 (BC_7, ddra04        ,  bidir          , X,  282 , 1, Z     ),"&
     " 274 (BC_7, ddra05        ,  bidir          , X,  282 , 1, Z     ),"&
     " 273 (BC_7, ddra06        ,  bidir          , X,  282 , 1, Z     ),"&
     " 272 (BC_7, ddra07        ,  bidir          , X,  282 , 1, Z     ),"&
     " 271 (BC_7, ddra08        ,  bidir          , X,  270 , 1, Z     ),"&
     " 270 (BC_2, *             ,  control        , 1                  ),"&
     " 269 (BC_7, ddra09        ,  bidir          , X,  270 , 1, Z     ),"&
     " 268 (BC_7, ddra10        ,  bidir          , X,  270 , 1, Z     ),"&
     " 267 (BC_7, ddra11        ,  bidir          , X,  270 , 1, Z     ),"&
     " 266 (BC_7, ddrclkoutp1   ,  bidir          , X,  270 , 1, Z     ),"&
     " 265 (BC_7, ddrclkoutn1   ,  bidir          , X,  270 , 1, Z     ),"&
     " 264 (BC_7, ddra12        ,  bidir          , X,  270 , 1, Z     ),"&
     " 263 (BC_7, ddra13        ,  bidir          , X,  270 , 1, Z     ),"&
     " 262 (BC_7, ddra14        ,  bidir          , X,  270 , 1, Z     ),"&
     " 261 (BC_7, ddra15        ,  bidir          , X,  270 , 1, Z     ),"&
     " 260 (BC_7, ddrcke1       ,  bidir          , X,  270 , 1, Z     ),"&
     " 259 (BC_7, ddrd56        ,  bidir          , X,  258 , 1, Z     ),"&
     " 258 (BC_2, *             ,  control        , 1                  ),"&
     " 257 (BC_7, ddrd57        ,  bidir          , X,  256 , 1, Z     ),"&
     " 256 (BC_2, *             ,  control        , 1                  ),"&
     " 255 (BC_7, ddrd58        ,  bidir          , X,  254 , 1, Z     ),"&
     " 254 (BC_2, *             ,  control        , 1                  ),"&
     " 253 (BC_7, ddrd59        ,  bidir          , X,  252 , 1, Z     ),"&
     " 252 (BC_2, *             ,  control        , 1                  ),"&
     " 251 (BC_7, ddrd60        ,  bidir          , X,  250 , 1, Z     ),"&
     " 250 (BC_2, *             ,  control        , 1                  ),"&
     " 249 (BC_7, ddrd61        ,  bidir          , X,  248 , 1, Z     ),"&
     " 248 (BC_2, *             ,  control        , 1                  ),"&
     " 247 (BC_7, ddrd62        ,  bidir          , X,  246 , 1, Z     ),"&
     " 246 (BC_2, *             ,  control        , 1                  ),"&
     " 245 (BC_7, ddrd63        ,  bidir          , X,  244 , 1, Z     ),"&
     " 244 (BC_2, *             ,  control        , 1                  ),"&
     " 243 (BC_7, ddrdqs7p      ,  bidir          , X,  242 , 1, Z     ),"&
     " 242 (BC_2, *             ,  control        , 1                  ),"&
     " 241 (BC_7, ddrdqm7       ,  bidir          , X,  240 , 1, Z     ),"&
     " 240 (BC_2, *             ,  control        , 1                  ),"&
     " 239 (BC_7, ddrd48        ,  bidir          , X,  238 , 1, Z     ),"&
     " 238 (BC_2, *             ,  control        , 1                  ),"&
     " 237 (BC_7, ddrd49        ,  bidir          , X,  236 , 1, Z     ),"&
     " 236 (BC_2, *             ,  control        , 1                  ),"&
     " 235 (BC_7, ddrd50        ,  bidir          , X,  234 , 1, Z     ),"&
     " 234 (BC_2, *             ,  control        , 1                  ),"&
     " 233 (BC_7, ddrd51        ,  bidir          , X,  232 , 1, Z     ),"&
     " 232 (BC_2, *             ,  control        , 1                  ),"&
     " 231 (BC_7, ddrd52        ,  bidir          , X,  230 , 1, Z     ),"&
     " 230 (BC_2, *             ,  control        , 1                  ),"&
     " 229 (BC_7, ddrd53        ,  bidir          , X,  228 , 1, Z     ),"&
     " 228 (BC_2, *             ,  control        , 1                  ),"&
     " 227 (BC_7, ddrd54        ,  bidir          , X,  226 , 1, Z     ),"&
     " 226 (BC_2, *             ,  control        , 1                  ),"&
     " 225 (BC_7, ddrd55        ,  bidir          , X,  224 , 1, Z     ),"&
     " 224 (BC_2, *             ,  control        , 1                  ),"&
     " 223 (BC_7, ddrdqs6p      ,  bidir          , X,  222 , 1, Z     ),"&
     " 222 (BC_2, *             ,  control        , 1                  ),"&
     " 221 (BC_7, ddrdqm6       ,  bidir          , X,  220 , 1, Z     ),"&
     " 220 (BC_2, *             ,  control        , 1                  ),"&
     " 219 (BC_7, ddrd40        ,  bidir          , X,  218 , 1, Z     ),"&
     " 218 (BC_2, *             ,  control        , 1                  ),"&
     " 217 (BC_7, ddrd41        ,  bidir          , X,  216 , 1, Z     ),"&
     " 216 (BC_2, *             ,  control        , 1                  ),"&
     " 215 (BC_7, ddrd42        ,  bidir          , X,  214 , 1, Z     ),"&
     " 214 (BC_2, *             ,  control        , 1                  ),"&
     " 213 (BC_7, ddrd43        ,  bidir          , X,  212 , 1, Z     ),"&
     " 212 (BC_2, *             ,  control        , 1                  ),"&
     " 211 (BC_7, ddrd44        ,  bidir          , X,  210 , 1, Z     ),"&
     " 210 (BC_2, *             ,  control        , 1                  ),"&
     " 209 (BC_7, ddrd45        ,  bidir          , X,  208 , 1, Z     ),"&
     " 208 (BC_2, *             ,  control        , 1                  ),"&
     " 207 (BC_7, ddrd46        ,  bidir          , X,  206 , 1, Z     ),"&
     " 206 (BC_2, *             ,  control        , 1                  ),"&
     " 205 (BC_7, ddrd47        ,  bidir          , X,  204 , 1, Z     ),"&
     " 204 (BC_2, *             ,  control        , 1                  ),"&
     " 203 (BC_7, ddrdqs5p      ,  bidir          , X,  202 , 1, Z     ),"&
     " 202 (BC_2, *             ,  control        , 1                  ),"&
     " 201 (BC_7, ddrdqm5       ,  bidir          , X,  200 , 1, Z     ),"&
     " 200 (BC_2, *             ,  control        , 1                  ),"&
     " 199 (BC_7, ddrd32        ,  bidir          , X,  198 , 1, Z     ),"&
     " 198 (BC_2, *             ,  control        , 1                  ),"&
     " 197 (BC_7, ddrd33        ,  bidir          , X,  196 , 1, Z     ),"&
     " 196 (BC_2, *             ,  control        , 1                  ),"&
     " 195 (BC_7, ddrd34        ,  bidir          , X,  194 , 1, Z     ),"&
     " 194 (BC_2, *             ,  control        , 1                  ),"&
     " 193 (BC_7, ddrd35        ,  bidir          , X,  192 , 1, Z     ),"&
     " 192 (BC_2, *             ,  control        , 1                  ),"&
     " 191 (BC_7, ddrd36        ,  bidir          , X,  190 , 1, Z     ),"&
     " 190 (BC_2, *             ,  control        , 1                  ),"&
     " 189 (BC_7, ddrd37        ,  bidir          , X,  188 , 1, Z     ),"&
     " 188 (BC_2, *             ,  control        , 1                  ),"&
     " 187 (BC_7, ddrd38        ,  bidir          , X,  186 , 1, Z     ),"&
     " 186 (BC_2, *             ,  control        , 1                  ),"&
     " 185 (BC_7, ddrd39        ,  bidir          , X,  184 , 1, Z     ),"&
     " 184 (BC_2, *             ,  control        , 1                  ),"&
     " 183 (BC_7, ddrdqs4p      ,  bidir          , X,  182 , 1, Z     ),"&
     " 182 (BC_2, *             ,  control        , 1                  ),"&
     " 181 (BC_7, ddrdqm4       ,  bidir          , X,  180 , 1, Z     ),"&
     " 180 (BC_2, *             ,  control        , 1                  ),"&
     " 179 (BC_7, ddrd24        ,  bidir          , X,   178 , 1, Z    ),"&
     " 178 (BC_2, *             ,  control        , 1                  ),"&
     " 177 (BC_7, ddrd25        ,  bidir          , X,   176 , 1, Z    ),"&
     " 176 (BC_2, *             ,  control        , 1                  ),"&
     " 175 (BC_7, ddrd26        ,  bidir          , X,   174 , 1, Z    ),"&
     " 174 (BC_2, *             ,  control        , 1                  ),"&
     " 173 (BC_7, ddrd27        ,  bidir          , X,   172 , 1, Z    ),"&
     " 172 (BC_2, *             ,  control        , 1                  ),"&
     " 171 (BC_7, ddrd28        ,  bidir          , X,   170 , 1, Z    ),"&
     " 170 (BC_2, *             ,  control        , 1                  ),"&
     " 169 (BC_7, ddrd29        ,  bidir          , X,   168 , 1, Z    ),"&
     " 168 (BC_2, *             ,  control        , 1                  ),"&
     " 167 (BC_7, ddrd30        ,  bidir          , X,   166 , 1, Z    ),"&
     " 166 (BC_2, *             ,  control        , 1                  ),"&
     " 165 (BC_7, ddrd31        ,  bidir          , X,   164 , 1, Z    ),"&
     " 164 (BC_2, *             ,  control        , 1                  ),"&
     " 163 (BC_7, ddrdqs3p      ,  bidir          , X,   162 , 1, Z    ),"&
     " 162 (BC_2, *             ,  control        , 1                  ),"&
     " 161 (BC_7, ddrdqm3       ,  bidir          , X,   160 , 1, Z    ),"&
     " 160 (BC_2, *             ,  control        , 1                  ),"&
     " 159 (BC_7, ddrd16        ,  bidir          , X,   158 , 1, Z    ),"&
     " 158 (BC_2, *             ,  control        , 1                  ),"&
     " 157 (BC_7, ddrd17        ,  bidir          , X,   156 , 1, Z    ),"&
     " 156 (BC_2, *             ,  control        , 1                  ),"&
     " 155 (BC_7, ddrd18        ,  bidir          , X,   154 , 1, Z    ),"&
     " 154 (BC_2, *             ,  control        , 1                  ),"&
     " 153 (BC_7, ddrd19        ,  bidir          , X,   152 , 1, Z    ),"&
     " 152 (BC_2, *             ,  control        , 1                  ),"&
     " 151 (BC_7, ddrd20        ,  bidir          , X,   150 , 1, Z    ),"&
     " 150 (BC_2, *             ,  control        , 1                  ),"&
     " 149 (BC_7, ddrd21        ,  bidir          , X,   148 , 1, Z    ),"&
     " 148 (BC_2, *             ,  control        , 1                  ),"&
     " 147 (BC_7, ddrd22        ,  bidir          , X,   146 , 1, Z    ),"&
     " 146 (BC_2, *             ,  control        , 1                  ),"&
     " 145 (BC_7, ddrd23        ,  bidir          , X,   144 , 1, Z    ),"&
     " 144 (BC_2, *             ,  control        , 1                  ),"&
     " 143 (BC_7, ddrdqs2p      ,  bidir          , X,   142 , 1, Z    ),"&
     " 142 (BC_2, *             ,  control        , 1                  ),"&
     " 141 (BC_7, ddrdqm2       ,  bidir          , X,   140 , 1, Z    ),"&
     " 140 (BC_2, *             ,  control        , 1                  ),"&
     " 139 (BC_7, ddrd08        ,  bidir          , X,   138 , 1, Z    ),"&
     " 138 (BC_2, *             ,  control        , 1                  ),"&
     " 137 (BC_7, ddrd09        ,  bidir          , X,   136 , 1, Z    ),"&
     " 136 (BC_2, *             ,  control        , 1                  ),"&
     " 135 (BC_7, ddrd10        ,  bidir          , X,   134 , 1, Z    ),"&
     " 134 (BC_2, *             ,  control        , 1                  ),"&
     " 133 (BC_7, ddrd11        ,  bidir          , X,   132 , 1, Z    ),"&
     " 132 (BC_2, *             ,  control        , 1                  ),"&
     " 131 (BC_7, ddrd12        ,  bidir          , X,   130 , 1, Z    ),"&
     " 130 (BC_2, *             ,  control        , 1                  ),"&
     " 129 (BC_7, ddrd13        ,  bidir          , X,   128 , 1, Z    ),"&
     " 128 (BC_2, *             ,  control        , 1                  ),"&
     " 127 (BC_7, ddrd14        ,  bidir          , X,   126 , 1, Z    ),"&
     " 126 (BC_2, *             ,  control        , 1                  ),"&
     " 125 (BC_7, ddrd15        ,  bidir          , X,   124 , 1, Z    ),"&
     " 124 (BC_2, *             ,  control        , 1                  ),"&
     " 123 (BC_7, ddrdqs1p      ,  bidir          , X,   122 , 1, Z    ),"&
     " 122 (BC_2, *             ,  control        , 1                  ),"&
     " 121 (BC_7, ddrdqm1       ,  bidir          , X,   120 , 1, Z    ),"&
     " 120 (BC_2, *             ,  control        , 1                  ),"&
     " 119 (BC_7, ddrd00        ,  bidir          , X,   118 , 1, Z    ),"&
     " 118 (BC_2, *             ,  control        , 1                  ),"&
     " 117 (BC_7, ddrd01        ,  bidir          , X,   116 , 1, Z    ),"&
     " 116 (BC_2, *             ,  control        , 1                  ),"&
     " 115 (BC_7, ddrd02        ,  bidir          , X,   114 , 1, Z    ),"&
     " 114 (BC_2, *             ,  control        , 1                  ),"&
     " 113 (BC_7, ddrd03        ,  bidir          , X,   112 , 1, Z    ),"&
     " 112 (BC_2, *             ,  control        , 1                  ),"&
     " 111 (BC_7, ddrd04        ,  bidir          , X,   110 , 1, Z    ),"&
     " 110 (BC_2, *             ,  control        , 1                  ),"&
     " 109 (BC_7, ddrd05        ,  bidir          , X,   108 , 1, Z    ),"&
     " 108 (BC_2, *             ,  control        , 1                  ),"&
     " 107 (BC_7, ddrd06        ,  bidir          , X,   106 , 1, Z    ),"&
     " 106 (BC_2, *             ,  control        , 1                  ),"&
     " 105 (BC_7, ddrd07        ,  bidir          , X,   104 , 1, Z    ),"&
     " 104 (BC_2, *             ,  control        , 1                  ),"&
     " 103 (BC_7, ddrdqs0p      ,  bidir          , X,   102 , 1, Z    ),"&
     " 102 (BC_2, *             ,  control        , 1                  ),"&
     " 101 (BC_7, ddrdqm0       ,  bidir          , X,   100 , 1, Z    ),"&
     " 100 (BC_2, *             ,  control        , 1                  ),"&
     "  99 (BC_7, ddrcb00       ,  bidir          , X,   98 , 1, Z     ),"&
     "  98 (BC_2, *             ,  control        , 1                  ),"&
     "  97 (BC_7, ddrcb01       ,  bidir          , X,   96 , 1, Z     ),"&
     "  96 (BC_2, *             ,  control        , 1                  ),"&
     "  95 (BC_7, ddrcb02       ,  bidir          , X,   94 , 1, Z     ),"&
     "  94 (BC_2, *             ,  control        , 1                  ),"&
     "  93 (BC_7, ddrcb03       ,  bidir          , X,   92 , 1, Z     ),"&
     "  92 (BC_2, *             ,  control        , 1                  ),"&
     "  91 (BC_7, ddrcb04       ,  bidir          , X,   90 , 1, Z     ),"&
     "  90 (BC_2, *             ,  control        , 1                  ),"&
     "  89 (BC_7, ddrcb05       ,  bidir          , X,    88 , 1, Z    ),"&
     "  88 (BC_2, *             ,  control        , 1                  ),"&
     "  87 (BC_7, ddrcb06       ,  bidir          , X,    86 , 1, Z    ),"&
     "  86 (BC_2, *             ,  control        , 1                  ),"&
     "  85 (BC_7, ddrcb07       ,  bidir          , X,    84 , 1, Z    ),"&
     "  84 (BC_2, *             ,  control        , 1                  ),"&
     "  83 (BC_7, ddrdqs8p      ,  bidir          , X,    82 , 1, Z    ),"&
     "  82 (BC_2, *             ,  control        , 1                  ),"&
     "  81 (BC_7, ddrdqm8       ,  bidir          , X,    80 , 1, Z    ),"&
     "  80 (BC_2, *             ,  control        , 1                  ),"&
     "  79 (BC_1, rsv29         ,  output2        , 1,   79, 1, WEAK1  ),"&
     "  78 (BC_1, *             ,  internal       , 0                  ),"&
     "  77 (BC_3, rsv29         ,  input          , X                  ),"&
     "  76 (BC_1, rsv30         ,  output2        , 1,   76, 1, WEAK1  ),"&
     "  75 (BC_1, *             ,  internal       , 0                  ),"&
     "  74 (BC_3, rsv30         ,  input          , X                  ),"&
     "  73 (BC_1, vcntl0        ,  output2        , 1,   73, 1, WEAK1  ),"&
     "  72 (BC_1, *             ,  internal       , 0                  ),"&
     "  71 (BC_4, vcntl0        ,  observe_only   , X                  ),"&
     "  70 (BC_1, vcntl1        ,  output2        , 1,   70, 1, WEAK1  ),"&
     "  69 (BC_1, *             ,  internal       , 0                  ),"&
     "  68 (BC_4, vcntl1        ,  observe_only   , X                  ),"&
     "  67 (BC_1, vcntl2        ,  output2        , 1,   67, 1, WEAK1  ),"&
     "  66 (BC_1, *             ,  internal       , 0                  ),"&
     "  65 (BC_4, vcntl2        ,  observe_only   , X                  ),"&
     "  64 (BC_1, vcntl3        ,  output2        , 1,   64, 1, WEAK1  ),"&
     "  63 (BC_1, *             ,  internal       , 0                  ),"&
     "  62 (BC_4, vcntl3        ,  observe_only   , X                  ),"&
     "  61 (BC_7, mcmrxflclk    ,  bidir          , X,   60, 1, PULL0  ),"&
     "  60 (BC_2, *             ,  control        , 1                  ),"&
     "  59 (BC_7, mcmrxfldat    ,  bidir          , X,   58, 1, PULL0  ),"&
     "  58 (BC_2, *             ,  control        , 1                  ),"&
     "  57 (BC_7, mcmtxflclk    ,  bidir          , X,   56, 1, PULL0  ),"&
     "  56 (BC_2, *             ,  control        , 1                  ),"&
     "  55 (BC_7, mcmtxfldat    ,  bidir          , X,   54, 1, PULL0  ),"&
     "  54 (BC_2, *             ,  control        , 1                  ),"&
     "  53 (BC_7, mcmrxpmclk    ,  bidir          , X,   52, 1, PULL0  ),"&
     "  52 (BC_2, *             ,  control        , 1                  ),"&
     "  51 (BC_7, mcmrxpmdat    ,  bidir          , X,   50, 1, PULL0  ),"&
     "  50 (BC_2, *             ,  control        , 1                  ),"&
     "  49 (BC_7, mcmtxpmclk    ,  bidir          , X,   48, 1, PULL0  ),"&
     "  48 (BC_2, *             ,  control        , 1                  ),"&
     "  47 (BC_7, mcmtxpmdat    ,  bidir          , X,   46, 1, PULL0  ),"&
     "  46 (BC_2, *             ,  control        , 1                  ),"&
     "  45 (BC_1, mcmclkp       ,  input          , X                  ),"&
     "  44 (BC_4, mcmrxn0       ,  observe_only   , X                  ),"&
     "  43 (BC_4, mcmrxp0       ,  observe_only   , X                  ),"&
     "  42 (BC_4, mcmrxn1       ,  observe_only   , X                  ),"&
     "  41 (BC_4, mcmrxp1       ,  observe_only   , X                  ),"&
     "  40 (BC_4, mcmrxn2       ,  observe_only   , X                  ),"&
     "  39 (BC_4, mcmrxp2       ,  observe_only   , X                  ),"&
     "  38 (BC_4, mcmrxn3       ,  observe_only   , X                  ),"&
     "  37 (BC_4, mcmrxp3       ,  observe_only   , X                  ),"&
     "  36 (BC_1, mcmtxp0       ,  output2        , X                  ),"&
     "  35 (BC_1, mcmtxp1       ,  output2        , X                  ),"&
     "  34 (BC_1, mcmtxp2       ,  output2        , X                  ),"&
     "  33 (BC_1, mcmtxp3       ,  output2        , X                  ),"&
     "  32 (BC_4, aifrxn4       ,  observe_only   , X                  ),"&
     "  31 (BC_4, aifrxp4       ,  observe_only   , X                  ),"&
     "  30 (BC_4, aifrxn5       ,  observe_only   , X                  ),"&
     "  29 (BC_4, aifrxp5       ,  observe_only   , X                  ),"&
     "  28 (BC_1, aiftxp4       ,  output2        , X                  ),"&
     "  27 (BC_1, aiftxp5       ,  output2        , X                  ),"&
     "  26 (BC_4, aifrxn0       ,  observe_only   , X                  ),"&
     "  25 (BC_4, aifrxp0       ,  observe_only   , X                  ),"&
     "  24 (BC_4, aifrxn1       ,  observe_only   , X                  ),"&
     "  23 (BC_4, aifrxp1       ,  observe_only   , X                  ),"&
     "  22 (BC_4, aifrxn2       ,  observe_only   , X                  ),"&
     "  21 (BC_4, aifrxp2       ,  observe_only   , X                  ),"&
     "  20 (BC_4, aifrxn3       ,  observe_only   , X                  ),"&
     "  19 (BC_4, aifrxp3       ,  observe_only   , X                  ),"&
     "  18 (BC_1, aiftxp0       ,  output2        , X                  ),"&
     "  17 (BC_1, aiftxp1       ,  output2        , X                  ),"&
     "  16 (BC_1, aiftxp2       ,  output2        , X                  ),"&
     "  15 (BC_1, aiftxp3       ,  output2        , X                  ),"&
     "  14 (BC_1, rp1fbp        ,  input          , X                  ),"&
     "  13 (BC_7, physync       ,  bidir          , X,   12, 1, PULL0  ),"&
     "  12 (BC_2, *             ,  control        , 1                  ),"&
     "  11 (BC_7, radsync       ,  bidir          , X,   10, 1, PULL0  ),"&
     "  10 (BC_2, *             ,  control        , 1                  ),"&
     "   9 (BC_1, rp1clkp       ,  input          , X                  ),"&
     "   8 (BC_7, sysclkout     ,  bidir          , X,    7, 1, PULL0  ),"&
     "   7 (BC_2, *             ,  control        , 1                  ),"&
     "   6 (BC_2, *             ,  internal       , X                  ),"&
     "   5 (BC_2, *             ,  internal       , X                  ),"&
     "   4 (BC_1, rsv04         ,  output2        , X                  ),"&
     "   3 (BC_7, rsv20         ,  bidir          , X,    2, 1, PULL0  ),"&
     "   2 (BC_2, *             ,  control        , 1                  ),"&
     "   1 (BC_1, sysclkp       ,  input          , X                  ),"&
     "   0 (BC_1, altcoreclkp   ,  input          , X                  )";

 attribute DESIGN_WARNING of tms320tci6614 : entity is
      "According to simulation, BSD JTAG TAP may not work correctly unless  "&
      " device has completed RESET sequence first.                          "&
      "Forcing PORz and RESETFULLz low then release (no clock pulses        "&
      " required) would meet the requirement.                               "&
      "                                                                     "&
      "                                                                     "&
      "Note that boundary scan registers with disable result WEAK1 are      "&
      "open drain type pins, which require exteral pull-ups for tests to    "&
      "perform correctly.                                                   "&
      "                                                                     "&
      "In order to enter bscan mode correctly, TMS must be low at the       "&
      "rising edge of TRSTz and at least one cycle after TRSTz is high.     ";

end tms320tci6614;