-- **********************************************************************
--
-- FILE : zl30131ggg.bsd
-- generated by Cz.P. as zl30131 on Fri Jun 1 09:43:17 EDT 2007
-- using p.jtag.bsd rev 3.5 - 9 May, 2007
--
-- BSDL description for top level entity zl30131
-- Device : ZL30131 Multi-Rate Line Card Synchronizer
-- Package : 100-pin CABGA
--
-- Number of BSC cells: 160
--
-- **********************************************************************
-- Modification History:
-- rev.2: Fri Jun 1 09:43:17 EDT 2007
-- - upgrade Device Version in the JTAG ID to "0001"
-- - ASEL1 name assigned to cell 138 (from 139)
-- - ASEL2 name assigned to cell 139 (from 138)
--
-- Initial release: Wed Mar 21 08:18:22 EDT 2007
-- **********************************************************************
--
-- IMPORTANT NOTICE
--
-- This information is for modeling purposes only, and is not guaranteed.
--
-- This information is provided "as is" without warranty of any kind.
-- It may contain technical inaccuracies or typographical errors.
--
-- ZARLINK and ZL30131 are trademarks of ZARLINK Semiconductor. ZARLINK
-- products, marketed under trademarks, are protected under numerous US
-- and foreign patents and pending applications, maskwork rights, and
-- copyrights.
--
-- ZARLINK reserves the right to make changes to any products and
-- services at any time without notice. ZARLINK assumes no
-- responsibility or liability arising out of the application or use of
-- any information, product, or service described herein except as
-- expressly agreed to in writing by ZARLINK Corporation. ZARLINK
-- customers are advised to obtain the latest version of device
-- specifications before relying on any published information and before
-- placing orders for products or services.
--
-- ======================================================================
-- This BSDL model has been validated for syntax and semantics compliance
-- to IEEE 1149.1 using ASSET/Agilent BSDL Validation Service.
-- ======================================================================
--
-- ********************************************************************
--
-- SPECIAL NOTES
--
-- 1. All instruction opcodes other than those defined in this file
-- should be considered PRIVATE.
--
-- ********************************************************************
entity zl30131 is
generic(PHYSICAL_PIN_MAP : string := "BGA131_PACKAGE");
port (
ASEL1: in bit;
ASEL2: in bit;
CS_B_ASEL0: in bit;
DIFF0_EN: in bit;
DIFF0_N: linkage bit;
DIFF0_P: linkage bit;
DIFF1_EN: in bit;
DIFF1_N: linkage bit;
DIFF1_P: linkage bit;
DPLL1_HOLDOVER: out bit;
DPLL1_LOCK: out bit;
DPLL1_MOD_SEL0: in bit;
DPLL1_MOD_SEL1: in bit;
I2C_EN: in bit;
IC_GND: in bit;
IC_OPEN: linkage bit_vector (1 to 4);
INT0_B: out bit;
NC: linkage bit_vector (1 to 5);
OSC_I: linkage bit;
OSC_O: linkage bit;
P0_CLK0: out bit;
P0_CLK1: out bit;
P0_FP0: out bit;
P0_FP1: out bit;
P1_CLK0: out bit;
P1_CLK1: out bit;
REF: in bit_vector (0 to 7);
RST_B: in bit;
SCK_SCL: inout bit;
SDH_CLK0: out bit;
SDH_CLK1: out bit;
SDH_FIL_REF0: linkage bit;
SDH_FIL_REF1: linkage bit;
SDH_FILTER_I: linkage bit;
SI_SDA: inout bit;
SO: out bit;
SYNC: in bit_vector (0 to 2);
T4_REF: out bit;
TCK: in bit;
TDI: in bit;
TDO: out bit;
TIE_CLR_B: in bit;
TMS: in bit;
TRST_B: in bit;
AVDD18A: linkage bit_vector (1 to 3);
AVDD33A: linkage bit_vector (1 to 2);
AVSS: linkage bit_vector (1 to 6);
VDD18CORE: linkage bit_vector (1 to 2);
VDD33IO: linkage bit_vector (1 to 9);
VSS: linkage bit_vector (1 to 18)
);
use STD_1149_1_2001.all;
attribute COMPONENT_CONFORMANCE of zl30131 : entity is
"STD_1149_1_2001";
attribute PIN_MAP of zl30131 : entity is PHYSICAL_PIN_MAP;
constant BGA131_PACKAGE : PIN_MAP_STRING :=
"ASEL1 : F3 , " &
"ASEL2 : F2 , " &
"CS_B_ASEL0 : E3 , " &
"DIFF0_EN : K1 , " &
"DIFF0_N : B10 , " &
"DIFF0_P : A9 , " &
"DIFF1_EN : D3 , " &
"DIFF1_N : B9 , " &
"DIFF1_P : A10 , " &
"DPLL1_HOLDOVER : J1 , " &
"DPLL1_LOCK : H1 , " &
"DPLL1_MOD_SEL0 : C2 , " &
"DPLL1_MOD_SEL1 : D2 , " &
"I2C_EN : J2 , " &
"IC_GND : J6 , " &
"IC_OPEN :(K6 , " & -- IC_OPEN[1]
"C5 , " & -- IC_OPEN[2]
"B5 , " & -- IC_OPEN[3]
"H10 ), " & -- IC_OPEN[4]
"INT0_B : G2 , " &
"NC :(H7 , " & -- NC[1]
"G3 , " & -- NC[2]
"D1 , " & -- NC[3]
"E10 , " & -- NC[4]
"F10 ), " & -- NC[5]
"OSC_I : K4 , " &
"OSC_O : K5 , " &
"P0_CLK0 : K9 , " &
"P0_CLK1 : K7 , " &
"P0_FP0 : K8 , " &
"P0_FP1 : J7 , " &
"P1_CLK0 : J10 , " &
"P1_CLK1 : K10 , " &
"REF :(C1 , " & -- REF[0]
"B2 , " & -- REF[1]
"A3 , " & -- REF[2]
"C3 , " & -- REF[3]
"B3 , " & -- REF[4]
"B4 , " & -- REF[5]
"C4 , " & -- REF[6]
"A4 ), " & -- REF[7]
"RST_B : H5 , " &
"SCK_SCL : E2 , " &
"SDH_CLK0 : D10 , " &
"SDH_CLK1 : G10 , " &
"SDH_FIL_REF0 : B6 , " &
"SDH_FIL_REF1 : C6 , " &
"SDH_FILTER_I : A6 , " &
"SI_SDA : F1 , " &
"SO : G1 , " &
"SYNC :(B1 , " & -- SYNC[0]
"A1 , " & -- SYNC[1]
"A2 ), " & -- SYNC[2]
"T4_REF : E1 , " &
"TCK : K3 , " &
"TDI : K2 , " &
"TDO : J4 , " &
"TIE_CLR_B : J5 , " &
"TMS : J3 , " &
"TRST_B : H4 , " &
"AVDD18A :(B8, B7, H2)," &
"AVDD33A :(C10, A8)," &
"AVSS :(D8, C9, C8, A7, C7, H3)," &
"VDD18CORE :(F4, E8)," &
"VDD33IO :(E4, J8, J9, H8, G8, H6, G9, D9, A5)," &
"VSS :(G5, D6, E6, H9, G6, F6, F9, F8, E9, D4, G7, F7," &
"E7, G4, D5, E5, F5, D7)";
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_CLOCK of TCK : signal is (10.0e6,BOTH);
attribute TAP_SCAN_RESET of TRST_B : signal is true;
--
-- NOTE: All instruction opcodes other than those defined in this file
-- should be considered PRIVATE.
--
attribute INSTRUCTION_LENGTH of zl30131 : entity is 4;
attribute INSTRUCTION_OPCODE of zl30131 : entity is
"bypass (1111)," &
"extest (0000)," &
"idcode (0010)," &
"preload (0001)," &
"sample (0001)";
attribute INSTRUCTION_CAPTURE of zl30131 : entity is "xx01";
attribute IDCODE_REGISTER of zl30131 : entity is
"0001" & -- version
"0111010110110011" & -- part number
"00010100101" & -- manufacturer id
"1";
attribute REGISTER_ACCESS of zl30131 : entity is
"boundary (extest, sample, preload)," &
"bypass (bypass)," &
"device_id (idcode)" ;
attribute BOUNDARY_LENGTH of zl30131 : entity is 160;
attribute BOUNDARY_REGISTER of zl30131 : entity is
-- num cell port function safe ccel disval rslt
" 0 ( BC_0, *, internal, X) ," &
" 1 ( BC_0, *, internal, X) ," &
" 2 ( BC_0, *, internal, X) ," &
" 3 ( BC_0, *, internal, X) ," &
" 4 ( BC_0, *, internal, X) ," &
" 5 ( BC_0, *, internal, X) ," &
" 6 ( BC_0, *, internal, X) ," &
" 7 ( BC_0, *, internal, X) ," &
" 8 ( BC_0, *, internal, X) ," &
" 9 ( BC_0, *, internal, X) ," &
" 10 ( BC_0, *, internal, 1) ," &
" 11 ( BC_0, *, internal, X) ," &
" 12 ( BC_0, *, internal, X) ," &
" 13 ( BC_0, *, internal, X) ," &
" 14 ( BC_0, *, internal, X) ," &
" 15 ( BC_0, *, internal, 1) ," &
" 16 ( BC_0, *, internal, X) ," &
" 17 ( BC_0, *, internal, 1) ," &
" 18 ( BC_0, *, internal, X) ," &
" 19 ( BC_0, *, internal, X) ," &
" 20 ( BC_0, *, internal, X) ," &
" 21 ( BC_0, *, internal, X) ," &
" 22 ( BC_0, *, internal, X) ," &
" 23 ( BC_0, *, internal, X) ," &
" 24 ( BC_0, *, internal, X) ," &
" 25 ( BC_0, *, internal, X) ," &
" 26 ( BC_0, *, internal, X) ," &
" 27 ( BC_0, *, internal, X) ," &
" 28 ( BC_0, *, internal, X) ," &
" 29 ( BC_4, TIE_CLR_B, input, X) ," &
" 30 ( BC_4, RST_B, input, X) ," &
" 31 ( BC_4, IC_GND, input, X) ," &
" 32 ( BC_0, *, internal, X) ," &
" 33 ( BC_2, *, control, 1) ," &
" 34 ( BC_1, P0_CLK1, output3, X, 33, 1, Z) ," &
" 35 ( BC_2, *, control, 1) ," &
" 36 ( BC_1, P0_FP1, output3, X, 35, 1, Z) ," &
" 37 ( BC_2, *, control, 1) ," &
" 38 ( BC_1, P0_FP0, output3, X, 37, 1, Z) ," &
" 39 ( BC_2, *, control, 1) ," &
" 40 ( BC_1, P0_CLK0, output3, X, 39, 1, Z) ," &
" 41 ( BC_2, *, control, 1) ," &
" 42 ( BC_1, P1_CLK1, output3, X, 41, 1, Z) ," &
" 43 ( BC_2, *, control, 1) ," &
" 44 ( BC_1, P1_CLK0, output3, X, 43, 1, Z) ," &
" 45 ( BC_0, *, internal, 1) ," &
" 46 ( BC_0, *, internal, X) ," &
" 47 ( BC_0, *, internal, X) ," &
" 48 ( BC_0, *, internal, X) ," &
" 49 ( BC_0, *, internal, X) ," &
" 50 ( BC_0, *, internal, X) ," &
" 51 ( BC_0, *, internal, X) ," &
" 52 ( BC_0, *, internal, X) ," &
" 53 ( BC_2, *, control, 1) ," &
" 54 ( BC_1, SDH_CLK1, output3, X, 53, 1, Z) ," &
" 55 ( BC_0, *, internal, 1) ," &
" 56 ( BC_0, *, internal, X) ," &
" 57 ( BC_0, *, internal, 1) ," &
" 58 ( BC_0, *, internal, X) ," &
" 59 ( BC_2, *, control, 1) ," &
" 60 ( BC_1, SDH_CLK0, output3, X, 59, 1, Z) ," &
" 61 ( BC_0, *, internal, 1) ," &
" 62 ( BC_0, *, internal, X) ," &
" 63 ( BC_0, *, internal, 1) ," &
" 64 ( BC_0, *, internal, X) ," &
" 65 ( BC_0, *, internal, X) ," &
" 66 ( BC_0, *, internal, 1) ," &
" 67 ( BC_0, *, internal, X) ," &
" 68 ( BC_0, *, internal, 1) ," &
" 69 ( BC_0, *, internal, X) ," &
" 70 ( BC_0, *, internal, X) ," &
" 71 ( BC_0, *, internal, X) ," &
" 72 ( BC_0, *, internal, X) ," &
" 73 ( BC_0, *, internal, X) ," &
" 74 ( BC_0, *, internal, X) ," &
" 75 ( BC_0, *, internal, X) ," &
" 76 ( BC_0, *, internal, X) ," &
" 77 ( BC_0, *, internal, X) ," &
" 78 ( BC_4, REF(7), input, X) ," &
" 79 ( BC_4, REF(6), input, X) ," &
" 80 ( BC_4, REF(5), input, X) ," &
" 81 ( BC_4, REF(4), input, X) ," &
" 82 ( BC_4, REF(3), input, X) ," &
" 83 ( BC_4, REF(2), input, X) ," &
" 84 ( BC_4, SYNC(2), input, X) ," &
" 85 ( BC_4, REF(1), input, X) ," &
" 86 ( BC_4, SYNC(1), input, X) ," &
" 87 ( BC_4, SYNC(0), input, X) ," &
" 88 ( BC_4, REF(0), input, X) ," &
" 89 ( BC_0, *, internal, 1) ," &
" 90 ( BC_0, *, internal, X) ," &
" 91 ( BC_0, *, internal, 1) ," &
" 92 ( BC_0, *, internal, X) ," &
" 93 ( BC_0, *, internal, 1) ," &
" 94 ( BC_0, *, internal, X) ," &
" 95 ( BC_0, *, internal, 1) ," &
" 96 ( BC_0, *, internal, X) ," &
" 97 ( BC_0, *, internal, 1) ," &
" 98 ( BC_0, *, internal, X) ," &
" 99 ( BC_4, DPLL1_MOD_SEL0, input, X) ," &
" 100 ( BC_4, DPLL1_MOD_SEL1, input, X) ," &
" 101 ( BC_4, DIFF1_EN, input, X) ," &
" 102 ( BC_0, *, internal, X) ," &
" 103 ( BC_0, *, internal, X) ," &
" 104 ( BC_2, *, control, 1) ," &
" 105 ( BC_1, T4_REF, output3, X, 104, 1, Z) ," &
" 106 ( BC_0, *, internal, X) ," &
" 107 ( BC_0, *, internal, X) ," &
" 108 ( BC_0, *, internal, X) ," &
" 109 ( BC_0, *, internal, X) ," &
" 110 ( BC_0, *, internal, X) ," &
" 111 ( BC_0, *, internal, X) ," &
" 112 ( BC_0, *, internal, X) ," &
" 113 ( BC_0, *, internal, X) ," &
" 114 ( BC_0, *, internal, X) ," &
" 115 ( BC_0, *, internal, X) ," &
" 116 ( BC_0, *, internal, 1) ," &
" 117 ( BC_0, *, internal, X) ," &
" 118 ( BC_0, *, internal, X) ," &
" 119 ( BC_0, *, internal, X) ," &
" 120 ( BC_0, *, internal, X) ," &
" 121 ( BC_0, *, internal, 1) ," &
" 122 ( BC_0, *, internal, X) ," &
" 123 ( BC_0, *, internal, 1) ," &
" 124 ( BC_0, *, internal, X) ," &
" 125 ( BC_0, *, internal, X) ," &
" 126 ( BC_0, *, internal, X) ," &
" 127 ( BC_0, *, internal, X) ," &
" 128 ( BC_0, *, internal, X) ," &
" 129 ( BC_0, *, internal, X) ," &
" 130 ( BC_0, *, internal, X) ," &
" 131 ( BC_0, *, internal, X) ," &
" 132 ( BC_0, *, internal, X) ," &
" 133 ( BC_0, *, internal, X) ," &
" 134 ( BC_0, *, internal, X) ," &
" 135 ( BC_2, *, control, 1) ," &
" 136 ( BC_7, SCK_SCL, bidir, X, 135, 1, Z) ," &
" 137 ( BC_4, CS_B_ASEL0, input, X) ," &
" 138 ( BC_4, ASEL1, input, X) ," &
" 139 ( BC_4, ASEL2, input, X) ," &
" 140 ( BC_2, *, control, 1) ," &
" 141 ( BC_7, SI_SDA, bidir, X, 140, 1, Z) ," &
" 142 ( BC_2, *, control, 1) ," &
" 143 ( BC_1, SO, output3, X, 142, 1, Z) ," &
" 144 ( BC_0, *, internal, 1) ," &
" 145 ( BC_0, *, internal, X) ," &
" 146 ( BC_2, *, control, 1) ," &
" 147 ( BC_1, INT0_B, output3, X, 146, 1, Z) ," &
" 148 ( BC_0, *, internal, X) ," &
" 149 ( BC_2, *, control, 1) ," &
" 150 ( BC_1, DPLL1_LOCK, output3, X, 149, 1, Z) ," &
" 151 ( BC_2, *, control, 1) ," &
" 152 ( BC_1, DPLL1_HOLDOVER, output3, X, 151, 1, Z) ," &
" 153 ( BC_0, *, internal, X) ," &
" 154 ( BC_0, *, internal, X) ," &
" 155 ( BC_0, *, internal, X) ," &
" 156 ( BC_4, DIFF0_EN, input, X) ," &
" 157 ( BC_4, I2C_EN, input, X) ," &
" 158 ( BC_0, *, internal, X) ," &
" 159 ( BC_0, *, internal, X) ";
end zl30131;
------------- end of BSDL description for the zl30131 ----------