-- *****************************************************************************
-- BSDL file for design BCM82391A0
-- Company: Broadcom Corporation
-- Author : thienn
-- Date : Tue Mar 29 21:53:23 2016
-- *****************************************************************************
entity BCM82391A0 is
generic (PHYSICAL_PIN_MAP : string := "BGA256");
port (
SRD3N : in bit;
SRD3P : in bit;
SRD2N : in bit;
SRD2P : in bit;
SRD1P : in bit;
SRD1N : in bit;
SRD0P : in bit;
SRD0N : in bit;
SYNC_IN_AB : in bit;
RESETB : in bit;
MOD_RXLOS_A : in bit;
PLL_RESETB : in bit;
SERBOOT : in bit;
MISO_SROM : in bit;
PLL_REFSEL : in bit;
TDI : in bit;
TMS : in bit;
TRSTB : in bit;
TCK : in bit;
DVSS : linkage bit_vector(0 to 15);
ADR_1 : in bit;
ADR_2 : in bit;
ADR_3 : in bit;
ADR_4 : in bit;
LRD0P : in bit;
LRD0N : in bit;
LRD1P : in bit;
LRD1N : in bit;
LRD2N : in bit;
LRD2P : in bit;
LRD3N : in bit;
LRD3P : in bit;
SRD7N : in bit;
SRD7P : in bit;
SRD6N : in bit;
SRD6P : in bit;
SRD5N : in bit;
SRD5P : in bit;
SRD4N : in bit;
SRD4P : in bit;
MOD_RXLOS_B : in bit;
DVDDIO : linkage bit_vector(0 to 1);
LRD4N : in bit;
LRD4P : in bit;
LRD5N : in bit;
LRD5P : in bit;
LRD6N : in bit;
LRD6P : in bit;
LRD7N : in bit;
LRD7P : in bit;
GPIO_0_A : inout bit;
GPIO_1_A : inout bit;
SYNC_OUT_AB : inout bit;
EXT_INTRB_A : inout bit;
SCL_M_A : inout bit;
SDA_M_A : inout bit;
GPIO_2_A : inout bit;
GPIO_4_A : inout bit;
GPIO_3_A : inout bit;
MDIO_A : inout bit;
MDC_A : inout bit;
GPIO_0_B : inout bit;
GPIO_1_B : inout bit;
EXT_INTRB_B : inout bit;
SCL_M_B : inout bit;
SDA_M_B : inout bit;
GPIO_2_B : inout bit;
GPIO_4_B : inout bit;
GPIO_3_B : inout bit;
MDIO_B : inout bit;
MDC_B : inout bit;
STD3N : out bit;
STD3P : out bit;
STD2N : out bit;
STD2P : out bit;
STD1N : out bit;
STD1P : out bit;
STD0N : out bit;
STD0P : out bit;
TEST_PAD_A : out bit;
OPTTXENB_A : out bit;
MOD_ABS_A : out bit;
SS_N_SROM : out bit;
SCK_SROM : out bit;
MOSI_SROM : out bit;
LTD0P : out bit;
LTD0N : out bit;
LTD1N : out bit;
LTD1P : out bit;
LTD2N : out bit;
LTD2P : out bit;
LTD3N : out bit;
LTD3P : out bit;
STD7P : out bit;
STD7N : out bit;
STD6N : out bit;
STD6P : out bit;
STD5N : out bit;
STD5P : out bit;
STD4N : out bit;
STD4P : out bit;
TEST_PAD_B : out bit;
OPTTXENB_B : out bit;
MOD_ABS_B : out bit;
TDO : out bit;
LTD4N : out bit;
LTD4P : out bit;
LTD5N : out bit;
LTD5P : out bit;
LTD6N : out bit;
LTD6P : out bit;
LTD7N : out bit;
LTD7P : out bit;
AVSS : linkage bit_vector(0 to 121);
REFCLKIN_P : linkage bit;
REFCLKIN_N : linkage bit;
PLL_TESTN_A : linkage bit;
PLL_TESTP_A : linkage bit;
VREGOUT_A : linkage bit;
SPTEST_N : linkage bit;
AVDDPLL : linkage bit_vector(0 to 1);
SPTEST_P : linkage bit;
AVDDTX : linkage bit_vector(0 to 3);
AVDDRX : linkage bit_vector(0 to 9);
AVDDTXDRV : linkage bit_vector(0 to 4);
DVDD : linkage bit_vector(0 to 6);
DVDDIOLVL : linkage bit;
VDDIOSYSLVL : linkage bit;
TEST : linkage bit;
LPTEST_P : linkage bit;
LPTEST_N : linkage bit;
PLL_TESTN_B : linkage bit;
PLL_TESTP_B : linkage bit;
VREGOUT_B : linkage bit;
NC : linkage bit_vector(0 to 28)
);
use STD_1149_1_2001.all;
use STD_1149_6_2003.all;
use LVS_BSCAN_CELLS.all;
attribute COMPONENT_CONFORMANCE of BCM82391A0: entity is "STD_1149_1_2001";
attribute PIN_MAP of BCM82391A0: entity is PHYSICAL_PIN_MAP;
constant BGA256: PIN_MAP_STRING :=
"SRD3N : P17 , " &
"SRD3P : P18 , " &
"SRD2N : R15 , " &
"SRD2P : P15 , " &
"SRD1P : P13 , " &
"SRD1N : R13 , " &
"SRD0P : P11 , " &
"SRD0N : R11 , " &
"SYNC_IN_AB : K15 , " &
"RESETB : T10 , " &
"MOD_RXLOS_A : M14 , " &
"PLL_RESETB : J16 , " &
"SERBOOT : G15 , " &
"MISO_SROM : G14 , " &
"PLL_REFSEL : J12 , " &
"TDI : F16 , " &
"TMS : C10 , " &
"TRSTB : C9 , " &
"TCK : G4 , " &
"DVSS : (F21 ,F23 ,G9 ,H7 ,H9 ,H11 ,J6 ,J8 ,J10 ,K6 ,K8 ," &
"K10 ,K12 ,L7 ,L9 ,L11) , " &
"ADR_1 : U1 , " &
"ADR_2 : G1 , " &
"ADR_3 : F2 , " &
"ADR_4 : B1 , " &
"LRD0P : E11 , " &
"LRD0N : D11 , " &
"LRD1P : E13 , " &
"LRD1N : D13 , " &
"LRD2N : D15 , " &
"LRD2P : E15 , " &
"LRD3N : E17 , " &
"LRD3P : E18 , " &
"SRD7N : P7 , " &
"SRD7P : R7 , " &
"SRD6N : P5 , " &
"SRD6P : R5 , " &
"SRD5N : P3 , " &
"SRD5P : R3 , " &
"SRD4N : P1 , " &
"SRD4P : R1 , " &
"MOD_RXLOS_B : M1 , " &
"DVDDIO : (K9 ,K11) , " &
"LRD4N : E1 , " &
"LRD4P : D1 , " &
"LRD5N : E3 , " &
"LRD5P : D3 , " &
"LRD6N : E5 , " &
"LRD6P : D5 , " &
"LRD7N : E7 , " &
"LRD7P : D7 , " &
"GPIO_0_A : H18 , " &
"GPIO_1_A : H17 , " &
"SYNC_OUT_AB : K16 , " &
"EXT_INTRB_A : M8 , " &
"SCL_M_A : M17 , " &
"SDA_M_A : M18 , " &
"GPIO_2_A : G18 , " &
"GPIO_4_A : G17 , " &
"GPIO_3_A : G16 , " &
"MDIO_A : J5 , " &
"MDC_A : K5 , " &
"GPIO_0_B : L2 , " &
"GPIO_1_B : M2 , " &
"EXT_INTRB_B : K1 , " &
"SCL_M_B : G2 , " &
"SDA_M_B : H2 , " &
"GPIO_2_B : K3 , " &
"GPIO_4_B : J2 , " &
"GPIO_3_B : K2 , " &
"MDIO_B : H1 , " &
"MDC_B : J1 , " &
"STD3N : T18 , " &
"STD3P : U18 , " &
"STD2N : U16 , " &
"STD2P : V16 , " &
"STD1N : U14 , " &
"STD1P : V14 , " &
"STD0N : U12 , " &
"STD0P : V12 , " &
"TEST_PAD_A : M12 , " &
"OPTTXENB_A : M15 , " &
"MOD_ABS_A : N16 , " &
"SS_N_SROM : G12 , " &
"SCK_SROM : G10 , " &
"MOSI_SROM : F9 , " &
"LTD0P : A12 , " &
"LTD0N : B12 , " &
"LTD1N : B14 , " &
"LTD1P : A14 , " &
"LTD2N : B16 , " &
"LTD2P : A16 , " &
"LTD3N : C18 , " &
"LTD3P : B18 , " &
"STD7P : U8 , " &
"STD7N : V8 , " &
"STD6N : V6 , " &
"STD6P : U6 , " &
"STD5N : V4 , " &
"STD5P : U4 , " &
"STD4N : V2 , " &
"STD4P : U2 , " &
"TEST_PAD_B : M6 , " &
"OPTTXENB_B : N2 , " &
"MOD_ABS_B : M4 , " &
"TDO : G8 , " &
"LTD4N : A2 , " &
"LTD4P : B2 , " &
"LTD5N : A4 , " &
"LTD5P : B4 , " &
"LTD6N : A6 , " &
"LTD6P : B6 , " &
"LTD7N : A8 , " &
"LTD7P : B8 , " &
"AVSS : (A1 ,A3 ,A5 ,A7 ,A9 ,A11 ,A13 ,A15 ,A17 ,A18 ,B3 ," &
"B5 ,B7 ,B9 ,B11 ,B13 ,B15 ,B17 ,C1 ,C2 ,C3 ," &
"C4 ,C5 ,C6 ,C7 ,C8 ,C11 ,C12 ,C13 ,C14 ,C15 ," &
"C16 ,C17 ,D2 ,D4 ,D6 ,D8 ,D10 ,D12 ,D14 ,D16 ," &
"D17 ,D18 ,E2 ,E4 ,E6 ,E8 ,E10 ,E12 ,E14 ,E16 ," &
"E21 ,E23 ,F1 ,F3 ,F5 ,F7 ,F11 ,F13 ,F15 ,F17 ," &
"F18 ,N1 ,N3 ,N5 ,N7 ,N11 ,N13 ,N15 ,N17 ,N18 ," &
"P2 ,P4 ,P6 ,P8 ,P10 ,P12 ,P14 ,P16 ,R2 ,R4 ," &
"R6 ,R8 ,R10 ,R12 ,R14 ,R16 ,R17 ,R18 ,T1 ,T2 ," &
"T3 ,T4 ,T5 ,T6 ,T7 ,T8 ,T11 ,T12 ,T13 ,T14 ," &
"T15 ,T16 ,T17 ,U3 ,U5 ,U7 ,U9 ,U11 ,U13 ,U15 ," &
"U17 ,V1 ,V3 ,V5 ,V7 ,V9 ,V11 ,V13 ,V15 ,V17 ,V18) , " &
"REFCLKIN_P : B10 , " &
"REFCLKIN_N : A10 , " &
"PLL_TESTN_A : K14 , " &
"PLL_TESTP_A : J14 , " &
"VREGOUT_A : J13 , " &
"SPTEST_N : R9 , " &
"AVDDPLL : (F6 ,N6) , " &
"SPTEST_P : P9 , " &
"AVDDTX : (G5 ,G13 ,M5 ,M13) , " &
"AVDDRX : (F4 ,F8 ,F10 ,F12 ,F14 ,N4 ,N8 ,N10 ,N12 ,N14) , " &
"AVDDTXDRV : (G7 ,G11 ,M7 ,M9 ,M11) , " &
"DVDD : (H10 ,H12 ,J7 ,K7 ,L8 ,L10 ,L12) , " &
"DVDDIOLVL : T9 , " &
"VDDIOSYSLVL : M10 , " &
"TEST : G6 , " &
"LPTEST_P : E9 , " &
"LPTEST_N : D9 , " &
"PLL_TESTN_B : H3 , " &
"PLL_TESTP_B : G3 , " &
"VREGOUT_B : K13 , " &
"NC : (H4 ,H5 ,H13 ,H14 ,H15 ,H16 ,J3 ,J4 ,J15 ,J17 ,J18 ," &
"K4 ,K17 ,K18 ,L1 ,L3 ,L4 ,L5 ,L13 ,L14 ,L15 ," &
"L16 ,L17 ,L18 ,M3 ,M16 ,N9 ,U10 ,V10) " ;
attribute PORT_GROUPING of BCM82391A0 : entity is
"Differential_Current ( (STD3N, STD3P), " &
"(SRD3N, SRD3P), " &
"(STD2N, STD2P), " &
"(SRD2N, SRD2P), " &
"(STD1N, STD1P), " &
"(SRD1P, SRD1N), " &
"(STD0N, STD0P), " &
"(SRD0P, SRD0N), " &
"(LRD0P, LRD0N), " &
"(LTD0P, LTD0N), " &
"(LRD1P, LRD1N), " &
"(LTD1N, LTD1P), " &
"(LRD2N, LRD2P), " &
"(LTD2N, LTD2P), " &
"(LRD3N, LRD3P), " &
"(LTD3N, LTD3P), " &
"(STD7P, STD7N), " &
"(SRD7N, SRD7P), " &
"(STD6N, STD6P), " &
"(SRD6N, SRD6P), " &
"(STD5N, STD5P), " &
"(SRD5N, SRD5P), " &
"(STD4N, STD4P), " &
"(SRD4N, SRD4P), " &
"(LRD4N, LRD4P), " &
"(LTD4N, LTD4P), " &
"(LRD5N, LRD5P), " &
"(LTD5N, LTD5P), " &
"(LRD6N, LRD6P), " &
"(LTD6N, LTD6P), " &
"(LRD7N, LRD7P), " &
"(LTD7N, LTD7P)) " ;
attribute TAP_SCAN_RESET of TRSTB : signal is true;
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_CLOCK of TCK : signal is (5.0000000000000000000e+07, BOTH);
attribute INSTRUCTION_LENGTH of BCM82391A0: entity is 39;
attribute INSTRUCTION_OPCODE of BCM82391A0: entity is
"TAP_INT_DR_SELECT (111111111111111111111111111111111111101)," &
"IDCODE (111111111111111111111111111111111111110)," &
"BYPASS (111111111111111111111111111111111111111)," &
"EXTEST (111111111111111111111111111111111101000)," &
"EXTEST_PULSE (111111111111111111111101111111111101000)," &
"EXTEST_TRAIN (111111111111111111111011111111111101000)," &
"SAMPLE (111111111111111111111111111111111111000)," &
"PRELOAD (111111111111111111111111111111111111000)," &
-- Standard HIGHZ instruction not supported because some output2 pins can't be disabled during HIGHZ
-- The LV_HIGHZ instruction informs etVerify to generate an IO HIGHZ TEST which only compares output3 and inout pins to <high-impedance>.
"LV_HIGHZ (111111111111111111111111111111111001111)," &
"CLAMP (111111111111111111111111111111111101111) " ;
attribute INSTRUCTION_CAPTURE of BCM82391A0: entity is "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx01";
attribute IDCODE_REGISTER of BCM82391A0: entity is
"XXXX" & -- version
"XXXXXXXXXXXXXXXX" & -- part number
"00010111111" & -- manufacturer's identity
"1"; -- required by 1149.1
attribute REGISTER_ACCESS of BCM82391A0: entity is
"DEVICE_ID ( IDCODE )," &
"BOUNDARY ( EXTEST_PULSE, EXTEST_TRAIN )," &
"DEVICE_ID ( IDCODE ), " &
"DEVICE_ID ( IDCODE )," &
"INT_DR[380] ( TAP_INT_DR_SELECT )," &
"BOUNDARY ( SAMPLE, PRELOAD, EXTEST )," &
"BYPASS ( LV_HIGHZ, CLAMP, BYPASS ) " ;
attribute BOUNDARY_LENGTH of BCM82391A0: entity is 140;
attribute BOUNDARY_REGISTER of BCM82391A0: entity is
-- num cell port function safe [ccell disval rslt]
" 139 (AC_2 , STD3N , output2 , X ) ,"&
" 138 (BC_4 , SRD3P , observe_only , X ) ,"&
" 137 (BC_4 , SRD3N , observe_only , X ) ,"&
" 136 (AC_2 , STD2N , output2 , X ) ,"&
" 135 (BC_4 , SRD2P , observe_only , X ) ,"&
" 134 (BC_4 , SRD2N , observe_only , X ) ,"&
" 133 (AC_2 , STD1N , output2 , X ) ,"&
" 132 (BC_4 , SRD1N , observe_only , X ) ,"&
" 131 (BC_4 , SRD1P , observe_only , X ) ,"&
" 130 (AC_2 , STD0N , output2 , X ) ,"&
" 129 (BC_4 , SRD0N , observe_only , X ) ,"&
" 128 (BC_4 , SRD0P , observe_only , X ) ,"&
" 127 (BC_2 , * , control , 1 ) ,"&
" 126 (LV_BC_7 , GPIO_0_A , bidir , X , 127 , 1 , Z ) ,"&
" 125 (BC_2 , * , control , 1 ) ,"&
" 124 (LV_BC_7 , GPIO_1_A , bidir , X , 125 , 1 , Z ) ,"&
" 123 (BC_2 , * , control , 1 ) ,"&
" 122 (LV_BC_7 , SYNC_OUT_AB , bidir , X , 123 , 1 , Z ) ,"&
" 121 (BC_2 , SYNC_IN_AB , input , X ) ,"&
" 120 (BC_2 , * , control , 1 ) ,"&
" 119 (BC_2 , TEST_PAD_A , output3 , X , 120 , 1 , Z ) ,"&
" 118 (BC_4 , RESETB , observe_only , X ) ,"&
" 117 (BC_2 , * , control , 1 ) ,"&
" 116 (LV_BC_7 , EXT_INTRB_A , bidir , X , 117 , 1 , Z ) ,"&
" 115 (BC_2 , * , control , 1 ) ,"&
" 114 (BC_2 , OPTTXENB_A , output3 , X , 115 , 1 , Z ) ,"&
" 113 (BC_2 , * , control , 1 ) ,"&
" 112 (BC_2 , MOD_ABS_A , output3 , X , 113 , 1 , Z ) ,"&
" 111 (BC_2 , * , control , 1 ) ,"&
" 110 (BC_2 , SS_N_SROM , output3 , X , 111 , 1 , Z ) ,"&
" 109 (BC_2 , MOD_RXLOS_A , input , X ) ,"&
" 108 (BC_2 , SCK_SROM , output3 , X , 111 , 1 , Z ) ,"&
" 107 (LV_BC_7 , SCL_M_A , bidir , 1 , 107 , 1 , weak1 ) ,"&
" 106 (LV_BC_7 , SDA_M_A , bidir , 1 , 106 , 1 , weak1 ) ,"&
" 105 (BC_2 , MOSI_SROM , output3 , X , 111 , 1 , Z ) ,"&
" 104 (BC_2 , PLL_RESETB , input , X ) ,"&
" 103 (BC_2 , SERBOOT , input , X ) ,"&
" 102 (BC_2 , MISO_SROM , input , X ) ,"&
" 101 (BC_4 , PLL_REFSEL , observe_only , X ) ,"&
" 100 (BC_2 , * , control , 1 ) ,"&
" 99 (LV_BC_7 , GPIO_2_A , bidir , X , 100 , 1 , Z ) ,"&
" 98 (BC_2 , * , control , 1 ) ,"&
" 97 (LV_BC_7 , GPIO_4_A , bidir , X , 98 , 1 , Z ) ,"&
" 96 (BC_2 , * , control , 1 ) ,"&
" 95 (LV_BC_7 , GPIO_3_A , bidir , X , 96 , 1 , Z ) ,"&
" 94 (BC_2 , * , internal , 1 ) ,"&
" 93 (BC_2 , * , internal , X ) ,"&
" 92 (BC_2 , * , internal , X ) ,"&
" 91 (BC_2 , ADR_1 , input , X ) ,"&
" 90 (BC_2 , ADR_2 , input , X ) ,"&
" 89 (BC_2 , ADR_3 , input , X ) ,"&
" 88 (BC_2 , * , internal , 1 ) ,"&
" 87 (BC_2 , * , internal , X ) ,"&
" 86 (BC_2 , * , control , 1 ) ,"&
" 85 (LV_BC_7 , MDIO_A , bidir , X , 86 , 1 , Z ) ,"&
" 84 (BC_2 , ADR_4 , input , X ) ,"&
" 83 (BC_2 , * , control , 1 ) ,"&
" 82 (LV_BC_7 , MDC_A , bidir , X , 83 , 1 , Z ) ,"&
" 81 (BC_4 , LRD0N , observe_only , X ) ,"&
" 80 (BC_4 , LRD0P , observe_only , X ) ,"&
" 79 (AC_2 , LTD0P , output2 , X ) ,"&
" 78 (BC_4 , LRD1N , observe_only , X ) ,"&
" 77 (BC_4 , LRD1P , observe_only , X ) ,"&
" 76 (AC_2 , LTD1N , output2 , X ) ,"&
" 75 (BC_4 , LRD2P , observe_only , X ) ,"&
" 74 (BC_4 , LRD2N , observe_only , X ) ,"&
" 73 (AC_2 , LTD2N , output2 , X ) ,"&
" 72 (BC_4 , LRD3P , observe_only , X ) ,"&
" 71 (BC_4 , LRD3N , observe_only , X ) ,"&
" 70 (AC_2 , LTD3N , output2 , X ) ,"&
" 69 (AC_2 , STD7P , output2 , X ) ,"&
" 68 (BC_4 , SRD7P , observe_only , X ) ,"&
" 67 (BC_4 , SRD7N , observe_only , X ) ,"&
" 66 (AC_2 , STD6N , output2 , X ) ,"&
" 65 (BC_4 , SRD6P , observe_only , X ) ,"&
" 64 (BC_4 , SRD6N , observe_only , X ) ,"&
" 63 (AC_2 , STD5N , output2 , X ) ,"&
" 62 (BC_4 , SRD5P , observe_only , X ) ,"&
" 61 (BC_4 , SRD5N , observe_only , X ) ,"&
" 60 (AC_2 , STD4N , output2 , X ) ,"&
" 59 (BC_4 , SRD4P , observe_only , X ) ,"&
" 58 (BC_4 , SRD4N , observe_only , X ) ,"&
" 57 (BC_2 , * , control , 1 ) ,"&
" 56 (LV_BC_7 , GPIO_0_B , bidir , X , 57 , 1 , Z ) ,"&
" 55 (BC_2 , * , control , 1 ) ,"&
" 54 (LV_BC_7 , GPIO_1_B , bidir , X , 55 , 1 , Z ) ,"&
" 53 (BC_2 , * , internal , 1 ) ,"&
" 52 (BC_2 , * , internal , X ) ,"&
" 51 (BC_2 , SYNC_IN_AB , input , X ) ,"&
" 50 (BC_2 , * , control , 1 ) ,"&
" 49 (BC_2 , TEST_PAD_B , output3 , X , 50 , 1 , Z ) ,"&
" 48 (BC_4 , RESETB , observe_only , X ) ,"&
" 47 (BC_2 , * , control , 1 ) ,"&
" 46 (LV_BC_7 , EXT_INTRB_B , bidir , X , 47 , 1 , Z ) ,"&
" 45 (BC_2 , * , control , 1 ) ,"&
" 44 (BC_2 , OPTTXENB_B , output3 , X , 45 , 1 , Z ) ,"&
" 43 (BC_2 , * , control , 1 ) ,"&
" 42 (BC_2 , MOD_ABS_B , output3 , X , 43 , 1 , Z ) ,"&
" 41 (BC_2 , * , control , 1 ) ,"&
" 40 (BC_2 , SS_N_SROM , output3 , X , 41 , 1 , Z ) ,"&
" 39 (BC_2 , MOD_RXLOS_B , input , X ) ,"&
" 38 (BC_2 , SCK_SROM , output3 , X , 41 , 1 , Z ) ,"&
" 37 (LV_BC_7 , SCL_M_B , bidir , 1 , 37 , 1 , weak1 ) ,"&
" 36 (LV_BC_7 , SDA_M_B , bidir , 1 , 36 , 1 , weak1 ) ,"&
" 35 (BC_2 , MOSI_SROM , output3 , X , 41 , 1 , Z ) ,"&
" 34 (BC_2 , PLL_RESETB , input , X ) ,"&
" 33 (BC_2 , SERBOOT , input , X ) ,"&
" 32 (BC_2 , MISO_SROM , input , X ) ,"&
" 31 (BC_4 , PLL_REFSEL , observe_only , X ) ,"&
" 30 (BC_2 , * , control , 1 ) ,"&
" 29 (LV_BC_7 , GPIO_2_B , bidir , X , 30 , 1 , Z ) ,"&
" 28 (BC_2 , * , control , 1 ) ,"&
" 27 (LV_BC_7 , GPIO_4_B , bidir , X , 28 , 1 , Z ) ,"&
" 26 (BC_2 , * , control , 1 ) ,"&
" 25 (LV_BC_7 , GPIO_3_B , bidir , X , 26 , 1 , Z ) ,"&
" 24 (BC_2 , * , internal , 1 ) ,"&
" 23 (BC_2 , * , internal , X ) ,"&
" 22 (BC_2 , * , internal , X ) ,"&
" 21 (BC_2 , ADR_1 , input , X ) ,"&
" 20 (BC_2 , ADR_2 , input , X ) ,"&
" 19 (BC_2 , ADR_3 , input , X ) ,"&
" 18 (BC_2 , * , internal , 1 ) ,"&
" 17 (BC_2 , * , internal , X ) ,"&
" 16 (BC_2 , * , control , 1 ) ,"&
" 15 (LV_BC_7 , MDIO_B , bidir , X , 16 , 1 , Z ) ,"&
" 14 (BC_2 , ADR_4 , input , X ) ,"&
" 13 (BC_2 , * , control , 1 ) ,"&
" 12 (LV_BC_7 , MDC_B , bidir , X , 13 , 1 , Z ) ,"&
" 11 (BC_4 , LRD4P , observe_only , X ) ,"&
" 10 (BC_4 , LRD4N , observe_only , X ) ,"&
" 9 (AC_2 , LTD4N , output2 , X ) ,"&
" 8 (BC_4 , LRD5P , observe_only , X ) ,"&
" 7 (BC_4 , LRD5N , observe_only , X ) ,"&
" 6 (AC_2 , LTD5N , output2 , X ) ,"&
" 5 (BC_4 , LRD6P , observe_only , X ) ,"&
" 4 (BC_4 , LRD6N , observe_only , X ) ,"&
" 3 (AC_2 , LTD6N , output2 , X ) ,"&
" 2 (BC_4 , LRD7P , observe_only , X ) ,"&
" 1 (BC_4 , LRD7N , observe_only , X ) ,"&
" 0 (AC_2 , LTD7N , output2 , X ) ";
attribute AIO_COMPONENT_CONFORMANCE of BCM82391A0: entity is "STD_1149_6_2003";
attribute AIO_EXTEST_Pulse_Execution of BCM82391A0: entity is
"Wait_Duration 1.00001e-06" ;
attribute AIO_EXTEST_Train_Execution of BCM82391A0: entity is
"train 10, maximum_time 1.00001e-05" ;
attribute AIO_Pin_Behavior of BCM82391A0: entity is
"STD3N ;"&
"SRD3N[137] : LP_Time=7.50e-09 HP_Time=1.50e-08;"&
"STD2N ;"&
"SRD2N[134] : LP_Time=7.50e-09 HP_Time=1.50e-08;"&
"STD1N ;"&
"SRD1P[131] : LP_Time=7.50e-09 HP_Time=1.50e-08;"&
"STD0N ;"&
"SRD0P[128] : LP_Time=7.50e-09 HP_Time=1.50e-08;"&
"LRD0P[80] : LP_Time=7.50e-09 HP_Time=1.50e-08;"&
"LTD0P ;"&
"LRD1P[77] : LP_Time=7.50e-09 HP_Time=1.50e-08;"&
"LTD1N ;"&
"LRD2N[74] : LP_Time=7.50e-09 HP_Time=1.50e-08;"&
"LTD2N ;"&
"LRD3N[71] : LP_Time=7.50e-09 HP_Time=1.50e-08;"&
"LTD3N ;"&
"STD7P ;"&
"SRD7N[67] : LP_Time=7.50e-09 HP_Time=1.50e-08;"&
"STD6N ;"&
"SRD6N[64] : LP_Time=7.50e-09 HP_Time=1.50e-08;"&
"STD5N ;"&
"SRD5N[61] : LP_Time=7.50e-09 HP_Time=1.50e-08;"&
"STD4N ;"&
"SRD4N[58] : LP_Time=7.50e-09 HP_Time=1.50e-08;"&
"LRD4N[10] : LP_Time=7.50e-09 HP_Time=1.50e-08;"&
"LTD4N ;"&
"LRD5N[7] : LP_Time=7.50e-09 HP_Time=1.50e-08;"&
"LTD5N ;"&
"LRD6N[4] : LP_Time=7.50e-09 HP_Time=1.50e-08;"&
"LTD6N ;"&
"LRD7N[1] : LP_Time=7.50e-09 HP_Time=1.50e-08;"&
"LTD7N ";
end BCM82391A0;