-- TI TMS320VC5401 16-Bit 144-pin Fixed-Point DSP with Boundary Scan --
-------------------------------------------------------------------------------
-- Supported Devices: TMS320VC5401PGE 144-pin Silicon Rev 1.1 and above --
-------------------------------------------------------------------------------
-- Created by : Texas Instruments Incorporated --
-- Documentation : TMS320LC54x Users Guides --
-- BSDL Revision : 1.0 - Original --
-- BSDL status : Preliminary --
-- Date created : 07/27/99 --
-------------------------------------------------------------------------------
--
-- Notes:
-- ======
--
-- Silicon Revision Requirements
-- -----------------------------
-- This BSDL file applies to 5401 silicon revisions 1.1 and later.
-- Silicon revisions prior to 1.1 had a bug associated with the
-- operation of the TDO signal that prevents boundary scan tests
-- from being performed properly. This bug has been corrected as
-- of revision 1.1.
--
--
-- Initialization Requirements for Boundary Scan Test
-- --------------------------------------------------
--
-- The 5401 uses the JTAG port for boundary scan tests, emulation
-- capability and factory test purposes. To use boundary scan test,
-- the EMU0 and EMU1/OFF pins must be held high through a rising edge
-- of the TRST- signal prior to the first scan. This operation
-- selects the appropriate TAP control for boundary scan. If at any
-- time during a boundary scan test a rising edge of TRST occurs when
-- EMU0 or EMU1 are not high, a factory test mode may be selected
-- preventing boundary scan test from being completed. For this reason,
-- it is recommended that EMU0 and EMU1/OFF be pulled or driven high at
-- all times during boundary scan test.
--
--
-- Device Pins not Covered by Boundary Scan
-- ----------------------------------------
-- The following pins do not have cells in the boundary register:
-- EMU0, EMU1/OFF, X2/CLKIN
--
--
-------------------------------------------------------------------------------
-- --
-- IMPORTANT NOTICE --
-- Texas Instruments Incorporated (TI) reserves the right to make changes --
-- to its products or to discontinue any semiconductor product or service --
-- without notice, and advises its customers to obtain the latest version --
-- of the relevant information to verify, before placing orders, that the --
-- information being relied on is current. --
-- --
-- TI warrants performance of its semiconductor products and related --
-- software to the specifications applicable at the time of sale in --
-- accordance with TI's standard warranty. Testing and other quality control--
-- techniques are utilized to the extent TI deems necessary to support this --
-- warranty. Specific testing of all parameters of each device is not --
-- necessarily performed, except those mandated by government requirements. --
-- --
-- Certain applications using semiconductor devices may involve potential --
-- risks of death, personal injury, or severe property or environmental --
-- damage ("Critical Applications"). --
-- --
-- TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, --
-- OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, --
-- DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. --
-- --
-- Inclusion of TI products in such applications is understood to be fully --
-- at the risk of the customer. Use of TI products in such applications --
-- requires the written approval of an appropriate TI officer. Questions --
-- concerning potential risk applications should be directed to TI through --
-- a local SC sales office. --
-- --
-- In order to minimize risks associated with the customer's applications, --
-- adequate design and operating safeguards should be provided by the --
-- customer to minimize inherent or procedural hazards. --
-- --
-- TI assumes no liability for applications assistance, customer product --
-- design, software performance, or infringement of patents or services --
-- described herein. Nor does TI warrant or represent that any license, --
-- either express or implied, is granted under any patent right, copyright, --
-- mask work right, or other intellectual property right of TI covering or --
-- relating to any combination, machine, or process in which such --
-- semiconductor products or services might be or are used. --
-- --
-- Copyright (c) 1999, Texas Instruments Incorporated --
-------------------------------------------------------------------------------
--***************************************************************************--
--* W A R N I N G *--
--* *--
--* This BSDL file has been checked for correct syntax and semantics *--
--* using several commercial tools, but it has NOT been validated against *--
--* the device. Without validation many structural errors could be *--
--* present, leading to possible damage of the device when using its *--
--* boundary scan logic. *--
--* *--
--***************************************************************************--
entity TMS320VC5401 is
generic (PHYSICAL_PIN_MAP : string := "PGE");
port (A : out bit_vector(0 to 19);
D : inout bit_vector(0 to 15);
INT_NEG : in bit_vector(0 to 3);
NMI_NEG : in bit;
IACK_NEG : out bit;
BDX : out bit_vector(0 to 1);
BFSX : inout bit_vector(0 to 1);
BCLKX : inout bit_vector(0 to 1);
BDR : in bit_vector(0 to 1);
BFSR : inout bit_vector(0 to 1);
BCLKR : inout bit_vector(0 to 1);
MP_MC_NEG : in bit;
BIO_NEG : in bit;
HOLD_NEG : in bit;
IAQ_NEG : out bit;
HOLDA_NEG : out bit;
XF : out bit;
MSC_NEG : out bit;
IOSTRB_NEG : out bit;
MSTRB_NEG : out bit;
R_W_NEG : out bit;
IS_NEG : out bit;
DS_NEG : out bit;
PS_NEG : out bit;
READY : in bit;
RS_NEG : in bit;
HD : inout bit_vector(0 to 7);
HBIL : in bit;
HRDY : out bit;
HINT : out bit;
HCNTL : in bit_vector(0 to 1);
HRW_NEG : in bit;
HCS_NEG : in bit;
HAS_NEG : in bit;
HDS2_NEG : in bit;
HDS1_NEG : in bit;
HPIENA : in bit;
X2_CLKIN : in bit;
X1 : linkage bit;
CLKOUT : out bit;
EMU1_OFF_NEG : in bit;
EMU0 : in bit;
TOUT0 : out bit;
NC : linkage bit_vector(1 to 18);
CLKMD : in bit_vector(1 to 3);
VSS : linkage bit_vector(1 to 12);
CVDD : linkage bit_vector(1 to 6);
DVDD : linkage bit_vector(1 to 6);
TCK : in bit;
TDI : in bit;
TDO : out bit;
TMS : in bit;
TRST_NEG : in bit);
use STD_1149_1_1994.all; -- Get standard attributes and definitions
use TI_BIDIR.all; -- Get C54X BIDIR cell attributes
----------------------------------------------------------------------
-- This package type TI_BIDIR must be available to your toolset. --
-- In most cases this text should be placed in a separate file --
-- named 'TI_BIDIR' that can be referenced via the previous --
-- 'use TI_BIDIR.all' statement. --
--
-- package TI_BIDIR is
-- use STD_1149_1_1990.all;
-- constant BC_BIDIR : CELL_INFO;
-- end TI_BIDIR;
--
-- package body TI_BIDIR is
-- constant BC_BIDIR : CELL_INFO :=
-- ((BIDIR_IN, EXTEST, PI), (BIDIR_OUT, EXTEST, PI),
-- (BIDIR_IN, SAMPLE, PI), (BIDIR_OUT, SAMPLE, PI),
-- (BIDIR_IN, INTEST, PI), (BIDIR_OUT, INTEST, PI));
-- end TI_BIDIR;
----------------------------------------------------------------------
attribute COMPONENT_CONFORMANCE of TMS320VC5401: entity is "STD_1149_1_1993";
attribute PIN_MAP of TMS320VC5401 : entity is PHYSICAL_PIN_MAP;
-- PGE Pinout --------------------------------------------------------
constant PGE : PIN_MAP_STRING :=
--Address and Data
" A:(131,132,133,134,136,137,138,139, " &
" 140,141, 5, 7, 8, 9, 10, 11, " &
" 105,107,108,109), " &
" D:( 99,100,101,102,103,104,113,114, " &
" 115,116,117,118,119,121,122,123), " &
--Control Signals
" DS_NEG: 21, PS_NEG: 20, IS_NEG: 22, " &
" READY: 19, R_W_NEG:23, " &
" MSTRB_NEG:24, IOSTRB_NEG:25, " &
" HOLD_NEG:30, HOLDA_NEG:28, " &
" IAQ_NEG:29, MSC_NEG:26, " &
--General Purpose I/O
" BIO_NEG:31, XF:27, " &
--Init., Int. and Reset
" IACK_NEG:61, " &
" NMI_NEG:63, INT_NEG:(64,65,66,67), " &
" RS_NEG:98, MP_MC_NEG:32, " &
--Ocillator Signals
" X1:96, X2_CLKIN:97, " &
" CLKOUT:94, CLKMD:(77,78,79), " &
--Timer Signal
" TOUT0:82, " &
--Multi-channel Buffered Serial Port
" BCLKR:(41,42), BCLKX:(48,49), " &
" BDR:(45,47), BDX:(59,60), " &
" BFSR:(43,44), BFSX:(53,54), " &
--Host Port Interface
" HPIENA:92, " &
" HD:(58,69,81,95,120,124,135,6), " &
" HINT:51, HCNTL:(39,46), HRW_NEG:18, " &
" HCS_NEG:17, HAS_NEG:13, HBIL:62, " &
" HDS1_NEG:127, HDS2_NEG:129, HRDY:55, " &
--JTAG Signals
" TCK:88, TDI:86, TDO:85, " &
" TMS:89, TRST_NEG:87, " &
--Emulation Signals
" EMU0:83, EMU1_OFF_NEG:84, " &
-- No connection
" NC:(1,2,12,15,35,36,37,38,71,72, " &
" 73,74,80,90,110,126,143,144), " &
--Power and Ground
"VSS:(3,14,34,40,50,57,70,76,93,106, " &
" 111,128), " &
"CVDD:(16,52,68,91,125,142), " &
"DVDD:(4,33,56,75,112,130)";
-- GGU Pinout --------------------------------------------------------
constant GGU : PIN_MAP_STRING :=
--Address and Data
" A:(C6,D6,A5,B5,D5,A4,B4,C4, " &
" A3,B3,D4,D2,D1,E4,E3,E2, " &
" C12,B13,B12,A13), " &
" D:(E11,E10,D13,D12,D11,C13,D10,C10, " &
" B10,A10,D9,C9,B9,D8,C8,B8), " &
--Control Signals
" DS_NEG: H1, PS_NEG: G4, IS_NEG: H2, " &
" READY: G3, R_W_NEG:H3, " &
" MSTRB_NEG:H4, IOSTRB_NEG:J1, " &
" HOLD_NEG:K2, HOLDA_NEG:J4, " &
" IAQ_NEG:K1, MSC_NEG:J2, " &
--General Purpose I/O
" BIO_NEG:K3, XF:J3, " &
--Init., Int. and Reset
" IACK_NEG:N9, " &
" NMI_NEG:L9, INT_NEG:(K9,N10,M10,L10), " &
" RS_NEG:E12, MP_MC_NEG:L1, " &
--Clock/Ocillator Signals
" X1:F10, X2_CLKIN:E13, " &
" CLKOUT:F12, CLKMD:(K10,K11,K12), " &
--Timer Signal
" TOUT0:J11, " &
--Multi-channel Buffered Serial Port
" BCLKR:(K4,L4), BCLKX:(N5,K6), " &
" BDR:(K5,M5), BDX:(L8,K8), " &
" BFSR:(M4,N4), BFSX:(M7,N7), " &
--Host Port Interface
" HPIENA:G10, " &
" HD:(M8,M11,J10,F11,A9,A8,C5,D3), " &
" HINT:M6, HCNTL:(M3,L5), HRW_NEG:G1, " &
" HCS_NEG:G2, HAS_NEG:F4, HBIL:M9, " &
" HDS1_NEG:C7, HDS2_NEG:A6, HRDY:L7, " &
--JTAG Signals
" TCK:H13, TDI:H11, TDO:H10, " &
" TMS:G12, TRST_NEG:H12, " &
--Emulation Signals
" EMU0:J12, EMU1_OFF_NEG:J13, " &
-- No connection
" NC:(A1,B1,E1,F2,M1,M2,N13,M13,K13,G13, " &
" N1,N2,N12,M12,A12,A7,A2,B2), " &
--Power and Ground
"VSS:(C2,F3,L3,L13,F13,C11,N3,L6,N8,L11, " &
" B11,D7), " &
"CVDD:(F1,G11,N6,N11,B7,C3), " &
"DVDD:(C1,L2,L12,K7,A11,B6) ";
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_RESET of TRST_NEG : signal is true;
attribute TAP_SCAN_CLOCK of TCK : signal is (25.00e6, BOTH);
attribute COMPLIANCE_PATTERNS of TMS320VC5401 : entity is "(EMU1_OFF_NEG,EMU0)(11)";
attribute INSTRUCTION_LENGTH of TMS320VC5401 : entity is 8;
attribute INSTRUCTION_OPCODE of TMS320VC5401 : entity is
"EXTEST (00000000), " &
"BYPASS (11111111), " &
"SAMPLE (00000010), " &
"HIGHZ (00000110) " ;
attribute INSTRUCTION_CAPTURE of TMS320VC5401 : entity is "XXXXXX01";
attribute REGISTER_ACCESS of TMS320VC5401 : entity is
"BOUNDARY (EXTEST, SAMPLE)," &
"BYPASS (BYPASS, HIGHZ) " ;
-- attribute BOUNDARY_CELLS of TMS320VC5401 : entity is
-- "BC_1, BC_2, BC_BIDIR";
attribute BOUNDARY_LENGTH of TMS320VC5401 : entity is 114;
attribute BOUNDARY_REGISTER of TMS320VC5401 : entity is
----------------------------------------------------------------
-- CELL CELL PIN CELL CNTRL
-- # NAME ,NAME ,TYPE , ,CELL
----------------------------------------------------------------
"0 (BC_2 ,HCS_NEG ,INPUT ,X ), " &
"1 (BC_2 ,HPIENA ,INPUT ,X ), " &
"2 (BC_2 ,HBIL ,INPUT ,X ), " &
"3 (BC_2 ,HRW_NEG ,INPUT ,X ), " &
"4 (BC_2 ,HAS_NEG ,INPUT ,X ), " &
"5 (BC_2 ,HCNTL(0) ,INPUT ,X ), " &
"6 (BC_2 ,HCNTL(1) ,INPUT ,X ), " &
"7 (BC_2 ,HDS1_NEG ,INPUT ,X ), " &
"8 (BC_2 ,HDS2_NEG ,INPUT ,X ), " &
"9 (BC_1 ,* ,CONTROL ,1 ), " &
"10 (BC_1 ,* ,CONTROL ,1 ), " &
"11 (BC_1 ,* ,CONTROL ,1 ), " &
"12 (BC_1 ,* ,CONTROL ,1 ), " &
"13 (BC_1 ,* ,CONTROL ,1 ), " &
"14 (BC_1 ,* ,CONTROL ,1 ), " &
"15 (BC_1 ,* ,CONTROL ,1 ), " &
"16 (BC_1 ,* ,CONTROL ,1 ), " &
"17 (BC_BIDIR ,HD(0) ,BIDIR ,X ,9 ,1 ,Z), " &
"18 (BC_BIDIR ,HD(1) ,BIDIR ,X ,10 ,1 ,Z), " &
"19 (BC_BIDIR ,HD(2) ,BIDIR ,X ,11 ,1 ,Z), " &
"20 (BC_BIDIR ,HD(3) ,BIDIR ,X ,12 ,1 ,Z), " &
"21 (BC_BIDIR ,HD(4) ,BIDIR ,X ,13 ,1 ,Z), " &
"22 (BC_BIDIR ,HD(5) ,BIDIR ,X ,14 ,1 ,Z), " &
"23 (BC_BIDIR ,HD(6) ,BIDIR ,X ,15 ,1 ,Z), " &
"24 (BC_BIDIR ,HD(7) ,BIDIR ,X ,16 ,1 ,Z), " &
"25 (BC_1 ,HINT ,OUTPUT3 ,X ,63 ,1 ,Z), " &
"26 (BC_1 ,HRDY ,OUTPUT3 ,X ,63 ,1 ,Z), " &
"27 (BC_1 ,* ,CONTROL ,1 ), " &
"28 (BC_1 ,* ,CONTROL ,1 ), " &
"29 (BC_1 ,* ,CONTROL ,1 ), " &
"30 (BC_1 ,* ,CONTROL ,1 ), " &
"31 (BC_1 ,* ,CONTROL ,1 ), " &
"32 (BC_BIDIR ,BFSX(1) ,BIDIR ,X ,29 ,1 ,Z), " &
"33 (BC_1 ,BDX(1) ,OUTPUT3 ,X ,28 ,1 ,Z), " &
"34 (BC_BIDIR ,BFSR(1) ,BIDIR ,X ,31 ,1 ,Z), " &
"35 (BC_2 ,BDR(1) ,INPUT ,X ), " &
"36 (BC_BIDIR ,BCLKR(1) ,BIDIR ,X ,27 ,1 ,Z), " &
"37 (BC_BIDIR ,BCLKX(1) ,BIDIR ,X ,30 ,1 ,Z), " &
"38 (BC_1 ,* ,CONTROL ,1 ), " &
"39 (BC_1 ,* ,CONTROL ,1 ), " &
"40 (BC_1 ,* ,CONTROL ,1 ), " &
"41 (BC_1 ,* ,CONTROL ,1 ), " &
"42 (BC_1 ,* ,CONTROL ,1 ), " &
"43 (BC_BIDIR ,BFSX(0) ,BIDIR ,X ,40 ,1 ,Z), " &
"44 (BC_1 ,BDX(0) ,OUTPUT3 ,X ,39 ,1 ,Z), " &
"45 (BC_BIDIR ,BFSR(0) ,BIDIR ,X ,42 ,1 ,Z), " &
"46 (BC_2 ,BDR(0) ,INPUT ,X ), " &
"47 (BC_BIDIR ,BCLKR(0) ,BIDIR ,X, 38 ,1 ,Z), " &
"48 (BC_BIDIR ,BCLKX(0) ,BIDIR ,X ,41 ,1 ,Z), " &
"49 (BC_2 ,CLKMD(3) ,INPUT ,X ), " &
"50 (BC_2 ,CLKMD(2) ,INPUT ,X ), " &
"51 (BC_2 ,CLKMD(1) ,INPUT ,X ), " &
"52 (BC_2 ,NMI_NEG ,INPUT ,X ), " &
"53 (BC_2 ,INT_NEG(3) ,INPUT ,X ), " &
"54 (BC_2 ,INT_NEG(2) ,INPUT ,X ), " &
"55 (BC_2 ,INT_NEG(1) ,INPUT ,X ), " &
"56 (BC_2 ,INT_NEG(0) ,INPUT ,X ), " &
"57 (BC_2 ,READY ,INPUT ,X ), " &
"58 (BC_2 ,RS_NEG ,INPUT ,X ), " &
"59 (BC_2 ,MP_MC_NEG ,INPUT ,X ), " &
"60 (BC_2 ,BIO_NEG ,INPUT ,X ), " &
"61 (BC_1 ,* ,CONTROL ,1 ), " &
"62 (BC_2 ,HOLD_NEG ,INPUT ,X ), " &
"63 (BC_1 ,* ,CONTROL ,1 ), " &
"64 (BC_1 ,* ,CONTROL ,1 ), " &
"65 (BC_1 ,A(16) ,OUTPUT3 ,X ,61 ,1 ,Z), " &
"66 (BC_1 ,A(17) ,OUTPUT3 ,X ,61 ,1 ,Z), " &
"67 (BC_1 ,A(18) ,OUTPUT3 ,X ,61 ,1 ,Z), " &
"68 (BC_1 ,A(19) ,OUTPUT3 ,X ,61 ,1 ,Z), " &
"69 (BC_BIDIR ,D(0) ,BIDIR ,X ,64 ,1 ,Z), " &
"70 (BC_BIDIR ,D(1) ,BIDIR ,X ,64 ,1 ,Z), " &
"71 (BC_BIDIR ,D(2) ,BIDIR ,X ,64 ,1 ,Z), " &
"72 (BC_BIDIR ,D(3) ,BIDIR ,X ,64 ,1 ,Z), " &
"73 (BC_BIDIR ,D(4) ,BIDIR ,X ,64 ,1 ,Z), " &
"74 (BC_BIDIR ,D(5) ,BIDIR ,X ,64 ,1 ,Z), " &
"75 (BC_BIDIR ,D(6) ,BIDIR ,X ,64 ,1 ,Z), " &
"76 (BC_BIDIR ,D(7) ,BIDIR ,X ,64 ,1 ,Z), " &
"77 (BC_BIDIR ,D(8) ,BIDIR ,X ,64 ,1 ,Z), " &
"78 (BC_BIDIR ,D(9) ,BIDIR ,X ,64 ,1 ,Z), " &
"79 (BC_BIDIR ,D(10) ,BIDIR ,X ,64 ,1 ,Z), " &
"80 (BC_BIDIR ,D(11) ,BIDIR ,X ,64 ,1 ,Z), " &
"81 (BC_BIDIR ,D(12) ,BIDIR ,X ,64 ,1 ,Z), " &
"82 (BC_BIDIR ,D(13) ,BIDIR ,X ,64 ,1 ,Z), " &
"83 (BC_BIDIR ,D(14) ,BIDIR ,X ,64 ,1 ,Z), " &
"84 (BC_BIDIR ,D(15) ,BIDIR ,X ,64 ,1 ,Z), " &
"85 (BC_1 ,TOUT0 ,OUTPUT3 ,X ,63 ,1 ,Z), " &
"86 (BC_1 ,CLKOUT ,OUTPUT3 ,X ,63 ,1 ,Z), " &
"87 (BC_1 ,IAQ_NEG ,OUTPUT3 ,X ,63 ,1 ,Z), " &
"88 (BC_1 ,MSC_NEG ,OUTPUT3 ,X ,63 ,1 ,Z), " &
"89 (BC_1 ,HOLDA_NEG ,OUTPUT3 ,X ,63 ,1 ,Z), " &
"90 (BC_1 ,IOSTRB_NEG ,OUTPUT3 ,X ,61 ,1 ,Z), " &
"91 (BC_1 ,R_W_NEG ,OUTPUT3 ,X ,61 ,1 ,Z), " &
"92 (BC_1 ,MSTRB_NEG ,OUTPUT3 ,X ,61 ,1 ,Z), " &
"93 (BC_1 ,IS_NEG ,OUTPUT3 ,X ,61 ,1 ,Z), " &
"94 (BC_1 ,PS_NEG ,OUTPUT3 ,X ,61 ,1 ,Z), " &
"95 (BC_1 ,DS_NEG ,OUTPUT3 ,X ,61 ,1 ,Z), " &
"96 (BC_1 ,XF ,OUTPUT3 ,X ,63 ,1 ,Z), " &
"97 (BC_1 ,IACK_NEG ,OUTPUT3 ,X ,63 ,1 ,Z), " &
"98 (BC_1 ,A(0) ,OUTPUT3 ,X ,61 ,1 ,Z), " &
"99 (BC_1 ,A(1) ,OUTPUT3 ,X ,61 ,1 ,Z), " &
"100 (BC_1 ,A(2) ,OUTPUT3 ,X ,61 ,1 ,Z), " &
"101 (BC_1 ,A(3) ,OUTPUT3 ,X ,61 ,1 ,Z), " &
"102 (BC_1 ,A(4) ,OUTPUT3 ,X ,61 ,1 ,Z), " &
"103 (BC_1 ,A(5) ,OUTPUT3 ,X ,61 ,1 ,Z), " &
"104 (BC_1 ,A(6) ,OUTPUT3 ,X ,61 ,1 ,Z), " &
"105 (BC_1 ,A(7) ,OUTPUT3 ,X ,61 ,1 ,Z), " &
"106 (BC_1 ,A(8) ,OUTPUT3 ,X ,61 ,1 ,Z), " &
"107 (BC_1 ,A(9) ,OUTPUT3 ,X ,61 ,1 ,Z), " &
"108 (BC_1 ,A(10) ,OUTPUT3 ,X ,61 ,1 ,Z), " &
"109 (BC_1 ,A(11) ,OUTPUT3 ,X ,61 ,1 ,Z), " &
"110 (BC_1 ,A(12) ,OUTPUT3 ,X ,61 ,1 ,Z), " &
"111 (BC_1 ,A(13) ,OUTPUT3 ,X ,61 ,1 ,Z), " &
"112 (BC_1 ,A(14) ,OUTPUT3 ,X ,61 ,1 ,Z), " &
"113 (BC_1 ,A(15) ,OUTPUT3 ,X ,61 ,1 ,Z) " ;
end TMS320VC5401;
