-- PMC_Sierra_Cells VHDL Package and Package Body
-- for PMC - Sierra
--
-- revision : 1.0
--
-- created by : James Lamond (Hewlett Packard Canada Ltd)
--
-- date : 20 December 1995
package PMC_Sierra_Cells is
use STD_1149_1_1990.all;
constant cele0 : CELL_INFO;
end PMC_Sierra_Cells;
package body PMC_Sierra_Cells is
constant cele0 : CELL_INFO :=
((BIDIR_IN, EXTEST, PI), (BIDIR_OUT, EXTEST, PO),
(BIDIR_IN, SAMPLE, PI), (BIDIR_OUT, SAMPLE, PI),
(BIDIR_IN, RUNBIST, PI), (BIDIR_OUT, RUNBIST, PO) );
end PMC_Sierra_Cells; -- End of PMC_Sierra_Cells Package Body
------------------------------------------------------------------------------
--
--
-- BSDL file for: PMC-Sierra PM73122 AAL1GATOR-32
-- ATM ADAPTATION LAYER 1
-- SEGMENTATION AND REASSEMBLY PROCESSOR-32
--
-- Electrical verification was performed on the following device:
-- Part number: PM73122-BI-P
-- Lot number: CD623680C
-- Date Code: M0110
-- Using Agilent 3070 Software revision B.03.60
--
------------------------------------------------------------------------------
--
--
-- BSDL Revision: 1.0
-- Date: Jun 20, 2001
-- Agilent Technologies Canada Inc
--
-- Notes
--
-- (1) The following pins may be flagged as errors by some BSDL compilers
-- because they are not part of the boundary-scan register. You may have
-- to determine how your compiler handles these non-compliant pins.
-- For example, declare them as linkage bits in the "PORT" statement.
-- Signal SCAN_ENB Pin C12
-- Signal SCAN_MODEB Pin AC24
--
-- (2) The following input signals have the boundary scan cells implemented
-- with a cell that supports bidirectional pins, so they are declared as
inout.
-- Signal CGC_SER_D
-- Signal CGC_VALID
-- Signal RATM_D_0_TPHY_D_0
-- Signal RATM_D_1_TPHY_D_1
-- Signal RATM_D_2_TPHY_D_2
-- Signal RATM_D_3_TPHY_D_3
-- Signal RATM_D_4_TPHY_D_4
-- Signal RATM_D_5_TPHY_D_5
-- Signal RATM_D_6_TPHY_D_6
-- Signal RATM_D_7_TPHY_D_7
-- Signal RATM_D_8_TPHY_D_8
-- Signal RATM_D_9_TPHY_D_9
-- Signal RATM_D_10_TPHY_D_10
-- Signal RATM_D_11_TPHY_D_11
-- Signal RATM_D_12_TPHY_D_12
-- Signal RATM_D_13_TPHY_D_13
-- Signal RATM_D_14_TPHY_D_14
-- Signal RATM_D_15_TPHY_D_15
-- Signal RATM_PAR_TPHY_PAR
-- Signal RATM_SOC_TPHY_SOC_TSOP
-- Signal RL_SIG_0
-- Signal RL_SYNC_0_TL_CLK_16
-- Signal RPHY_ADD_0
-- Signal RPHY_ADD_1
-- Signal RPHY_ADD_2
-- Signal RPHY_ADD_3_RCSB
-- Signal TL_CLK_OE
-- Signal TPHY_ADD_0
-- Signal TPHY_ADD_1
-- Signal TPHY_ADD_2
-- Signal TPHY_ADD_3_TCSB
-- Signal TPHY_ADD_4_TSX
--
-- (3) The following output signals have the boundary scan cells implemented
-- with a cell that supports bidirectional pins, so they are declared as
inout.
-- Signal RAM1_A_0
-- Signal RAM1_A_1
-- Signal RAM1_A_2
-- Signal RAM1_A_3
-- Signal RAM1_A_4
-- Signal RAM1_A_5
-- Signal RAM1_A_6
-- Signal RAM1_A_7
-- Signal RAM1_A_8
-- Signal RAM1_A_9
-- Signal RAM1_A_10
-- Signal RAM1_A_11
-- Signal RAM1_A_12
-- Signal RAM1_A_13
-- Signal TATM_D_0_RPHY_D_0
-- Signal TATM_D_1_RPHY_D_1
-- Signal TATM_D_2_RPHY_D_2
-- Signal TATM_D_3_RPHY_D_3
-- Signal TATM_D_4_RPHY_D_4
-- Signal TATM_D_5_RPHY_D_5
-- Signal TATM_D_6_RPHY_D_6
-- Signal TATM_D_7_RPHY_D_7
-- Signal TATM_D_8_RPHY_D_8
-- Signal TATM_D_9_RPHY_D_9
-- Signal TATM_D_10_RPHY_D_10
-- Signal TATM_D_11_RPHY_D_11
-- Signal TATM_D_12_RPHY_D_12
-- Signal TATM_D_13_RPHY_D_13
-- Signal TATM_D_14_RPHY_D_14
-- Signal TATM_D_15_RPHY_D_15
-- Signal TATM_PAR_RPHY_PAR
-- Signal TATM_SOC_RPHY_SOC_RSOP
--
------------------------------------------------------------------------------
--
entity PM73122 is
generic(PHYSICAL_PIN_MAP : string := "SBGA_352");
port(
A_0 : in bit;
A_1 : in bit;
A_2 : in bit;
A_3 : in bit;
A_4 : in bit;
A_5 : in bit;
A_6 : in bit;
A_7 : in bit;
A_8 : in bit;
A_9 : in bit;
A_10 : in bit;
A_11 : in bit;
A_12 : in bit;
A_13 : in bit;
A_14 : in bit;
A_15 : in bit;
A_16 : in bit;
A_17 : in bit;
A_18 : in bit;
A_19 : in bit;
ACKB : out bit;
ADAP_STBH : out bit;
ALE : in bit;
CGC_DOUT_0 : out bit;
CGC_DOUT_1 : out bit;
CGC_DOUT_2 : out bit;
CGC_DOUT_3 : out bit;
CGC_LINE_0 : out bit;
CGC_LINE_1 : out bit;
CGC_LINE_2 : out bit;
CGC_LINE_3 : out bit;
CGC_LINE_4 : out bit;
CGC_SER_D : inout bit; -- See note (2)
CGC_VALID : inout bit; -- See note (2)
CRL_CLK_C4B : in bit;
CSB : in bit;
CTL_CLK_C16B_REFCLK : in bit;
D_0 : inout bit;
D_1 : inout bit;
D_2 : inout bit;
D_3 : inout bit;
D_4 : inout bit;
D_5 : inout bit;
D_6 : inout bit;
D_7 : inout bit;
D_8 : inout bit;
D_9 : inout bit;
D_10 : inout bit;
D_11 : inout bit;
D_12 : inout bit;
D_13 : inout bit;
D_14 : inout bit;
D_15 : inout bit;
INTB : out bit;
LINE_MODE_0 : in bit;
LINE_MODE_1 : in bit;
NCLK_SRTS_DISB : in bit;
RAM1_A_0 : inout bit; -- See note (3)
RAM1_A_1 : inout bit; -- See note (3)
RAM1_A_2 : inout bit; -- See note (3)
RAM1_A_3 : inout bit; -- See note (3)
RAM1_A_4 : inout bit; -- See note (3)
RAM1_A_5 : inout bit; -- See note (3)
RAM1_A_6 : inout bit; -- See note (3)
RAM1_A_7 : inout bit; -- See note (3)
RAM1_A_8 : inout bit; -- See note (3)
RAM1_A_9 : inout bit; -- See note (3)
RAM1_A_10 : inout bit; -- See note (3)
RAM1_A_11 : inout bit; -- See note (3)
RAM1_A_12 : inout bit; -- See note (3)
RAM1_A_13 : inout bit; -- See note (3)
RAM1_A_14 : out bit;
RAM1_A_15 : out bit;
RAM1_A_16 : out bit;
RAM1_A_17 : out bit;
RAM1_ADSCB_RAM1_R_WB : out bit;
RAM1_CSB : out bit;
RAM1_D_0 : inout bit;
RAM1_D_1 : inout bit;
RAM1_D_2 : inout bit;
RAM1_D_3 : inout bit;
RAM1_D_4 : inout bit;
RAM1_D_5 : inout bit;
RAM1_D_6 : inout bit;
RAM1_D_7 : inout bit;
RAM1_D_8 : inout bit;
RAM1_D_9 : inout bit;
RAM1_D_10 : inout bit;
RAM1_D_11 : inout bit;
RAM1_D_12 : inout bit;
RAM1_D_13 : inout bit;
RAM1_D_14 : inout bit;
RAM1_D_15 : inout bit;
RAM1_OEB : out bit;
RAM1_PAR_0 : inout bit;
RAM1_PAR_1 : inout bit;
RAM1_WEB_0 : out bit;
RAM1_WEB_1 : out bit;
RATM_CLAV_TPHY_CLAV : inout bit;
RATM_CLK_TPHY_CLK : in bit;
RATM_D_0_TPHY_D_0 : inout bit; -- See note (2)
RATM_D_1_TPHY_D_1 : inout bit; -- See note (2)
RATM_D_2_TPHY_D_2 : inout bit; -- See note (2)
RATM_D_3_TPHY_D_3 : inout bit; -- See note (2)
RATM_D_4_TPHY_D_4 : inout bit; -- See note (2)
RATM_D_5_TPHY_D_5 : inout bit; -- See note (2)
RATM_D_6_TPHY_D_6 : inout bit; -- See note (2)
RATM_D_7_TPHY_D_7 : inout bit; -- See note (2)
RATM_D_8_TPHY_D_8 : inout bit; -- See note (2)
RATM_D_9_TPHY_D_9 : inout bit; -- See note (2)
RATM_D_10_TPHY_D_10 : inout bit; -- See note (2)
RATM_D_11_TPHY_D_11 : inout bit; -- See note (2)
RATM_D_12_TPHY_D_12 : inout bit; -- See note (2)
RATM_D_13_TPHY_D_13 : inout bit; -- See note (2)
RATM_D_14_TPHY_D_14 : inout bit; -- See note (2)
RATM_D_15_TPHY_D_15 : inout bit; -- See note (2)
RATM_ENB_TPHY_ENB : inout bit;
RATM_PAR_TPHY_PAR : inout bit; -- See note (2)
RATM_SOC_TPHY_SOC_TSOP : inout bit; -- See note (2)
RDB : in bit;
RL_CLK_0 : in bit;
RL_CLK_1 : in bit;
RL_CLK_2 : in bit;
RL_CLK_3 : in bit;
RL_CLK_4_TL_CLK_20 : in bit;
RL_CLK_5_TL_CLK_21 : in bit;
RL_CLK_6_TL_CLK_22 : in bit;
RL_CLK_7_TL_CLK_23 : in bit;
RL_CLK_8_TL_CLK_24 : in bit;
RL_CLK_9_TL_CLK_25 : in bit;
RL_CLK_10_TL_CLK_26 : in bit;
RL_CLK_11_TL_CLK_27 : in bit;
RL_CLK_12_TL_CLK_28 : in bit;
RL_CLK_13_TL_CLK_29 : in bit;
RL_CLK_14_TL_CLK_30 : in bit;
RL_CLK_15_TL_CLK_31 : in bit;
RL_DATA_0_AACTIVE : inout bit;
RL_DATA_1_AV5 : inout bit;
RL_DATA_2_ADP : inout bit;
RL_DATA_3_ADATA_1 : inout bit;
RL_DATA_4_ADATA_3 : inout bit;
RL_DATA_5_ADATA_6 : inout bit;
RL_DATA_6 : in bit;
RL_DATA_7 : in bit;
RL_DATA_8_RAM2_WEB_0 : inout bit;
RL_DATA_9_RAM2_A_0 : inout bit;
RL_DATA_10_RAM2_A_3 : inout bit;
RL_DATA_11_RAM2_A_4 : inout bit;
RL_DATA_12_RAM2_A_8 : inout bit;
RL_DATA_13_RAM2_A_12 : inout bit;
RL_DATA_14_RAM2_A_15 : inout bit;
RL_DATA_15_RAM2_A_17 : inout bit;
RL_SIG_0 : inout bit; -- See note (2)
RL_SIG_1_APL : inout bit;
RL_SIG_2_ADATA_0 : inout bit;
RL_SIG_3_ADATA_2 : inout bit;
RL_SIG_4_ADATA_5 : inout bit;
RL_SIG_5 : in bit;
RL_SIG_6 : in bit;
RL_SIG_7 : in bit;
RL_SIG_8_RAM2_ADSCB : inout bit;
RL_SIG_9_RAM2_WEB_1 : inout bit;
RL_SIG_10_RAM2_A_1 : inout bit;
RL_SIG_11_RAM2_A_5 : inout bit;
RL_SIG_12_RAM2_A_9 : inout bit;
RL_SIG_13_RAM2_A_10 : inout bit;
RL_SIG_14_RAM2_A_13 : inout bit;
RL_SIG_15_RAM2_A_16 : inout bit;
RL_SYNC_0_TL_CLK_16 : inout bit; -- See note (2)
RL_SYNC_1_TL_CLK_17 : in bit;
RL_SYNC_2_TL_CLK_18 : in bit;
RL_SYNC_3_TL_CLK_19 : in bit;
RL_SYNC_4_ADATA_4 : inout bit;
RL_SYNC_5_ADATA_7 : inout bit;
RL_SYNC_6 : in bit;
RL_SYNC_7 : in bit;
RL_SYNC_8_RAM2_CSB : inout bit;
RL_SYNC_9_RAM2_OEB : inout bit;
RL_SYNC_10_RAM2_A_2 : inout bit;
RL_SYNC_11_RAM2_A_6 : inout bit;
RL_SYNC_12_RAM2_A_7 : inout bit;
RL_SYNC_13_RAM2_A_11 : inout bit;
RL_SYNC_14_RAM2_A_14 : inout bit;
RL_SYNC_15 : in bit;
RPHY_ADD_0 : inout bit; -- See note (2)
RPHY_ADD_1 : inout bit; -- See note (2)
RPHY_ADD_2 : inout bit; -- See note (2)
RPHY_ADD_3_RCSB : inout bit; -- See note (2)
RPHY_ADD_RSX : inout bit;
RSTB : in bit;
SCAN_ENB : in bit;
SCAN_MODEB : in bit;
SRTS_STBH : out bit;
SYSCLK : in bit;
TATM_CLAV_RPHY_CLAV_RPA : inout bit;
TATM_CLK_RPHY_CLK : in bit;
TATM_D_0_RPHY_D_0 : inout bit; -- See note (3)
TATM_D_1_RPHY_D_1 : inout bit; -- See note (3)
TATM_D_2_RPHY_D_2 : inout bit; -- See note (3)
TATM_D_3_RPHY_D_3 : inout bit; -- See note (3)
TATM_D_4_RPHY_D_4 : inout bit; -- See note (3)
TATM_D_5_RPHY_D_5 : inout bit; -- See note (3)
TATM_D_6_RPHY_D_6 : inout bit; -- See note (3)
TATM_D_7_RPHY_D_7 : inout bit; -- See note (3)
TATM_D_8_RPHY_D_8 : inout bit; -- See note (3)
TATM_D_9_RPHY_D_9 : inout bit; -- See note (3)
TATM_D_10_RPHY_D_10 : inout bit; -- See note (3)
TATM_D_11_RPHY_D_11 : inout bit; -- See note (3)
TATM_D_12_RPHY_D_12 : inout bit; -- See note (3)
TATM_D_13_RPHY_D_13 : inout bit; -- See note (3)
TATM_D_14_RPHY_D_14 : inout bit; -- See note (3)
TATM_D_15_RPHY_D_15 : inout bit; -- See note (3)
TATM_ENB_RPHY_ENB_RENB : inout bit;
TATM_PAR_RPHY_PAR : inout bit; -- See note (3)
TATM_SOC_RPHY_SOC_RSOP : inout bit; -- See note (3)
TCLK : in bit;
TDI : in bit;
TDO : out bit;
TL_CLK_0 : inout bit;
TL_CLK_1 : inout bit;
TL_CLK_2 : inout bit;
TL_CLK_3 : inout bit;
TL_CLK_4 : inout bit;
TL_CLK_5 : inout bit;
TL_CLK_6 : inout bit;
TL_CLK_7 : inout bit;
TL_CLK_8 : inout bit;
TL_CLK_9 : inout bit;
TL_CLK_10 : inout bit;
TL_CLK_11 : inout bit;
TL_CLK_12 : inout bit;
TL_CLK_13 : inout bit;
TL_CLK_14 : inout bit;
TL_CLK_15 : inout bit;
TL_CLK_OE : inout bit; -- See note (2)
TL_DATA_0_C1FP : inout bit;
TL_DATA_1_AJUST_REQ : inout bit;
TL_DATA_2_DV5 : inout bit;
TL_DATA_3_DDATA_0 : inout bit;
TL_DATA_4_DDATA_2 : inout bit;
TL_DATA_5_DDATA_4 : inout bit;
TL_DATA_6_DDATA_6 : inout bit;
TL_DATA_7_C1FP_ADD : out bit;
TL_DATA_8_RAM2_D_1 : inout bit;
TL_DATA_9_RAM2_D_4 : inout bit;
TL_DATA_10_RAM2_D_6 : inout bit;
TL_DATA_11_RAM2_D_8 : inout bit;
TL_DATA_12_RAM2_D_12 : inout bit;
TL_DATA_13_RAM2_D_14 : inout bit;
TL_DATA_14 : out bit;
TL_DATA_15 : out bit;
TL_SIG_0_ADETECT : inout bit;
TL_SIG_1_DPL : inout bit;
TL_SIG_2_DDP : inout bit;
TL_SIG_3_DDATA_1 : inout bit;
TL_SIG_4_DDATA_3 : inout bit;
TL_SIG_5_DDATA_5 : inout bit;
TL_SIG_6_DDATA_7 : inout bit;
TL_SIG_7 : out bit;
TL_SIG_8_RAM2_D_0 : inout bit;
TL_SIG_9_RAM2_D_3 : inout bit;
TL_SIG_10_RAM2_D_5 : inout bit;
TL_SIG_11_RAM2_P_1 : inout bit;
TL_SIG_12_RAM2_D_11 : inout bit;
TL_SIG_13_RAM2_D_13 : inout bit;
TL_SIG_14 : out bit;
TL_SIG_15 : out bit;
TL_SYNC_0_F0B : inout bit;
TL_SYNC_1 : inout bit;
TL_SYNC_2 : inout bit;
TL_SYNC_3 : inout bit;
TL_SYNC_4 : inout bit;
TL_SYNC_5 : inout bit;
TL_SYNC_6 : inout bit;
TL_SYNC_7 : inout bit;
TL_SYNC_8_RAM2_P_0 : inout bit;
TL_SYNC_9_RAM2_D_2 : inout bit;
TL_SYNC_10_RAM2_D_7 : inout bit;
TL_SYNC_11_RAM2_D_9 : inout bit;
TL_SYNC_12_RAM2_D_10 : inout bit;
TL_SYNC_13_RAM2_D_15 : inout bit;
TL_SYNC_14 : inout bit;
TL_SYNC_15 : inout bit;
TMS : in bit;
TPHY_ADD_0 : inout bit; -- See note (2)
TPHY_ADD_1 : inout bit; -- See note (2)
TPHY_ADD_2 : inout bit; -- See note (2)
TPHY_ADD_3_TCSB : inout bit; -- See note (2)
TPHY_ADD_4_TSX : inout bit; -- See note (2)
TRSTB : in bit;
VDD2_5_1 : linkage bit;
VDD2_5_2 : linkage bit;
VDD2_5_3 : linkage bit;
VDD2_5_4 : linkage bit;
VDD2_5_5 : linkage bit;
VDD2_5_6 : linkage bit;
VDD2_5_7 : linkage bit;
VDD2_5_8 : linkage bit;
VDD2_5_9 : linkage bit;
VDD3_3_1 : linkage bit;
VDD3_3_2 : linkage bit;
VDD3_3_3 : linkage bit;
VDD3_3_4 : linkage bit;
VDD3_3_5 : linkage bit;
VDD3_3_6 : linkage bit;
VDD3_3_7 : linkage bit;
VDD3_3_8 : linkage bit;
VDD3_3_9 : linkage bit;
VDD3_3_10 : linkage bit;
VDD3_3_11 : linkage bit;
VDD3_3_12 : linkage bit;
VDD3_3_13 : linkage bit;
VDD3_3_14 : linkage bit;
VDD3_3_15 : linkage bit;
VDD3_3_16 : linkage bit;
VDD3_3_17 : linkage bit;
VDD3_3_18 : linkage bit;
VDD3_3_19 : linkage bit;
VDD3_3_20 : linkage bit;
VDD3_3_21 : linkage bit;
VDD3_3_22 : linkage bit;
VDD3_3_23 : linkage bit;
VDD3_3_24 : linkage bit;
VSS_1 : linkage bit;
VSS_2 : linkage bit;
VSS_3 : linkage bit;
VSS_4 : linkage bit;
VSS_5 : linkage bit;
VSS_6 : linkage bit;
VSS_7 : linkage bit;
VSS_8 : linkage bit;
VSS_9 : linkage bit;
VSS_10 : linkage bit;
VSS_11 : linkage bit;
VSS_12 : linkage bit;
VSS_13 : linkage bit;
VSS_14 : linkage bit;
VSS_15 : linkage bit;
VSS_16 : linkage bit;
VSS_17 : linkage bit;
VSS_18 : linkage bit;
VSS_19 : linkage bit;
VSS_20 : linkage bit;
VSS_21 : linkage bit;
VSS_22 : linkage bit;
VSS_23 : linkage bit;
VSS_24 : linkage bit;
VSS_25 : linkage bit;
VSS_26 : linkage bit;
VSS_27 : linkage bit;
VSS_28 : linkage bit;
WRB : in bit);
use STD_1149_1_1990.all;
use PMC_Sierra_Cells.all;
attribute PIN_MAP of PM73122 : entity is PHYSICAL_PIN_MAP;
constant SBGA_352 : PIN_MAP_STRING :=
"A_0 : AE12," &
"A_1 : AF12," &
"A_2 : AD13," &
"A_3 : AE13," &
"A_4 : AC16," &
"A_5 : AF18," &
"A_6 : AD17," &
"A_7 : AE18," &
"A_8 : AF20," &
"A_9 : AD19," &
"A_10 : AE20," &
"A_11 : AC19," &
"A_12 : AD21," &
"A_13 : AE22," &
"A_14 : AF23," &
"A_15 : AC21," &
"A_16 : AD23," &
"A_17 : AB23," &
"A_18 : AD26," &
"A_19 : AC25," &
"ACKB : AD11," &
"ADAP_STBH : AE4," &
"ALE : AD12," &
"CGC_DOUT_0 : AD8," &
"CGC_DOUT_1 : AE7," &
"CGC_DOUT_2 : AF10," &
"CGC_DOUT_3 : AC8," &
"CGC_LINE_0 : AD6," &
"CGC_LINE_1 : AE5," &
"CGC_LINE_2 : AF4," &
"CGC_LINE_3 : AC6," &
"CGC_LINE_4 : AD5," &
"CGC_SER_D : AC7," &
"CGC_VALID : AF5," &
"CRL_CLK_C4B : B7," &
"CSB : AE11," &
"CTL_CLK_C16B_REFCLK : C8," &
"D_0 : AE14," &
"D_1 : AD14," &
"D_2 : AF21," &
"D_3 : AE17," &
"D_4 : AF19," &
"D_5 : AC17," &
"D_6 : AD18," &
"D_7 : AE19," &
"D_8 : AD20," &
"D_9 : AE21," &
"D_10 : AF22," &
"D_11 : AC20," &
"D_12 : AD22," &
"D_13 : AE23," &
"D_14 : AF24," &
"D_15 : AC22," &
"INTB : AE10," &
"LINE_MODE_0 : AC1," &
"LINE_MODE_1 : B5," &
"NCLK_SRTS_DISB : AD7," &
"RAM1_A_0 : C22," &
"RAM1_A_1 : D21," &
"RAM1_A_2 : B22," &
"RAM1_A_3 : C21," &
"RAM1_A_4 : D20," &
"RAM1_A_5 : A22," &
"RAM1_A_6 : C20," &
"RAM1_A_7 : D19," &
"RAM1_A_8 : A17," &
"RAM1_A_9 : B20," &
"RAM1_A_10 : A20," &
"RAM1_A_11 : B19," &
"RAM1_A_12 : C18," &
"RAM1_A_13 : D17," &
"RAM1_A_14 : A19," &
"RAM1_A_15 : B18," &
"RAM1_A_16 : C17," &
"RAM1_A_17 : A18," &
"RAM1_ADSCB_RAM1_R_WB : B21," &
"RAM1_CSB : C19," &
"RAM1_D_0 : D15," &
"RAM1_D_1 : C14," &
"RAM1_D_2 : B14," &
"RAM1_D_3 : B13," &
"RAM1_D_4 : C13," &
"RAM1_D_5 : D13," &
"RAM1_D_6 : A12," &
"RAM1_D_7 : B12," &
"RAM1_D_8 : A11," &
"RAM1_D_9 : A6," &
"RAM1_D_10 : C10," &
"RAM1_D_11 : B9," &
"RAM1_D_12 : D10," &
"RAM1_D_13 : C9," &
"RAM1_D_14 : B8," &
"RAM1_D_15 : A7," &
"RAM1_OEB : A8," &
"RAM1_PAR_0 : B17," &
"RAM1_PAR_1 : C16," &
"RAM1_WEB_0 : D16," &
"RAM1_WEB_1 : B16," &
"RATM_CLAV_TPHY_CLAV : U23," &
"RATM_CLK_TPHY_CLK : Y26," &
"RATM_D_0_TPHY_D_0 : R26," &
"RATM_D_1_TPHY_D_1 : T25," &
"RATM_D_2_TPHY_D_2 : U26," &
"RATM_D_3_TPHY_D_3 : T24," &
"RATM_D_4_TPHY_D_4 : T23," &
"RATM_D_5_TPHY_D_5 : V26," &
"RATM_D_6_TPHY_D_6 : U24," &
"RATM_D_7_TPHY_D_7 : V25," &
"RATM_D_8_TPHY_D_8 : Y24," &
"RATM_D_9_TPHY_D_9 : AA25," &
"RATM_D_10_TPHY_D_10 : AB26," &
"RATM_D_11_TPHY_D_11 : Y23," &
"RATM_D_12_TPHY_D_12 : AB25," &
"RATM_D_13_TPHY_D_13 : AC26," &
"RATM_D_14_TPHY_D_14 : AA23," &
"RATM_D_15_TPHY_D_15 : AB24," &
"RATM_ENB_TPHY_ENB : U25," &
"RATM_PAR_TPHY_PAR : Y25," &
"RATM_SOC_TPHY_SOC_TSOP : W26," &
"RDB : AC12," &
"RL_CLK_0 : AD1," &
"RL_CLK_1 : V3," &
"RL_CLK_2 : T3," &
"RL_CLK_3 : L1," &
"RL_CLK_4_TL_CLK_20 : J2," &
"RL_CLK_5_TL_CLK_21 : F1," &
"RL_CLK_6_TL_CLK_22 : D1," &
"RL_CLK_7_TL_CLK_23 : D5," &
"RL_CLK_8_TL_CLK_24 : A16," &
"RL_CLK_9_TL_CLK_25 : B15," &
"RL_CLK_10_TL_CLK_26 : H25," &
"RL_CLK_11_TL_CLK_27 : K23," &
"RL_CLK_12_TL_CLK_28 : R23," &
"RL_CLK_13_TL_CLK_29 : R24," &
"RL_CLK_14_TL_CLK_30 : P25," &
"RL_CLK_15_TL_CLK_31 : N23," &
"RL_DATA_0_AACTIVE : AC3," &
"RL_DATA_1_AV5 : Y1," &
"RL_DATA_2_ADP : T4," &
"RL_DATA_3_ADATA_1 : R2," &
"RL_DATA_4_ADATA_3 : J1," &
"RL_DATA_5_ADATA_6 : H3," &
"RL_DATA_6 : F3," &
"RL_DATA_7 : D3," &
"RL_DATA_8_RAM2_WEB_0 : C11," &
"RL_DATA_9_RAM2_A_0 : B6," &
"RL_DATA_10_RAM2_A_3 : M1," &
"RL_DATA_11_RAM2_A_4 : Y3," &
"RL_DATA_12_RAM2_A_8 : AA3," &
"RL_DATA_13_RAM2_A_12 : AE9," &
"RL_DATA_14_RAM2_A_15 : AD15," &
"RL_DATA_15_RAM2_A_17 : AD16," &
"RL_SIG_0 : AC2," &
"RL_SIG_1_APL : U4," &
"RL_SIG_2_ADATA_0 : U1," &
"RL_SIG_3_ADATA_2 : P3," &
"RL_SIG_4_ADATA_5 : H1," &
"RL_SIG_5 : H4," &
"RL_SIG_6 : F4," &
"RL_SIG_7 : A3," &
"RL_SIG_8_RAM2_ADSCB : D12," &
"RL_SIG_9_RAM2_WEB_1 : D8," &
"RL_SIG_10_RAM2_A_1 : M3," &
"RL_SIG_11_RAM2_A_5 : AA2," &
"RL_SIG_12_RAM2_A_9 : AB2," &
"RL_SIG_13_RAM2_A_10 : AC10," &
"RL_SIG_14_RAM2_A_13 : AF15," &
"RL_SIG_15_RAM2_A_16 : AE16," &
"RL_SYNC_0_TL_CLK_16 : AB4," &
"RL_SYNC_1_TL_CLK_17 : W2," &
"RL_SYNC_2_TL_CLK_18 : U2," &
"RL_SYNC_3_TL_CLK_19 : R1," &
"RL_SYNC_4_ADATA_4 : K3," &
"RL_SYNC_5_ADATA_7 : G2," &
"RL_SYNC_6 : E2," &
"RL_SYNC_7 : C4," &
"RL_SYNC_8_RAM2_CSB : B11," &
"RL_SYNC_9_RAM2_OEB : C7," &
"RL_SYNC_10_RAM2_A_2 : M2," &
"RL_SYNC_11_RAM2_A_6 : AB1," &
"RL_SYNC_12_RAM2_A_7 : Y4," &
"RL_SYNC_13_RAM2_A_11 : AF8," &
"RL_SYNC_14_RAM2_A_14 : AE15," &
"RL_SYNC_15 : N24," &
"RPHY_ADD_0 : G25," &
"RPHY_ADD_1 : H23," &
"RPHY_ADD_2 : F25," &
"RPHY_ADD_3_RCSB : G24," &
"RPHY_ADD_RSX : E24," &
"RSTB : AD4," &
"SCAN_ENB : C12," &
"SCAN_MODEB : AC24," &
"SRTS_STBH : AF3," &
"SYSCLK : B23," &
"TATM_CLAV_RPHY_CLAV_RPA : M23," &
"TATM_CLK_RPHY_CLK : F26," &
"TATM_D_0_RPHY_D_0 : M26," &
"TATM_D_1_RPHY_D_1 : M25," &
"TATM_D_2_RPHY_D_2 : M24," &
"TATM_D_3_RPHY_D_3 : P24," &
"TATM_D_4_RPHY_D_4 : L25," &
"TATM_D_5_RPHY_D_5 : K26," &
"TATM_D_6_RPHY_D_6 : L24," &
"TATM_D_7_RPHY_D_7 : K25," &
"TATM_D_8_RPHY_D_8 : F24," &
"TATM_D_9_RPHY_D_9 : E25," &
"TATM_D_10_RPHY_D_10 : D26," &
"TATM_D_11_RPHY_D_11 : F23," &
"TATM_D_12_RPHY_D_12 : D25," &
"TATM_D_13_RPHY_D_13 : C26," &
"TATM_D_14_RPHY_D_14 : E23," &
"TATM_D_15_RPHY_D_15 : D24," &
"TATM_ENB_RPHY_ENB_RENB : H24," &
"TATM_PAR_RPHY_PAR : E26," &
"TATM_SOC_RPHY_SOC_RSOP : G26," &
"TCLK : D22," &
"TDI : C23," &
"TDO : A23," &
"TL_CLK_0 : Y2," &
"TL_CLK_1 : U3," &
"TL_CLK_2 : T1," &
"TL_CLK_3 : K2," &
"TL_CLK_4 : H2," &
"TL_CLK_5 : E1," &
"TL_CLK_6 : C1," &
"TL_CLK_7 : D6," &
"TL_CLK_8 : C15," &
"TL_CLK_9 : A15," &
"TL_CLK_10 : J24," &
"TL_CLK_11 : H26," &
"TL_CLK_12 : T26," &
"TL_CLK_13 : R25," &
"TL_CLK_14 : N25," &
"TL_CLK_15 : J25," &
"TL_CLK_OE : AE6," &
"TL_DATA_0_C1FP : AB3," &
"TL_DATA_1_AJUST_REQ : W1," &
"TL_DATA_2_DV5 : T2," &
"TL_DATA_3_DDATA_0 : K1," &
"TL_DATA_4_DDATA_2 : K4," &
"TL_DATA_5_DDATA_4 : G3," &
"TL_DATA_6_DDATA_6 : E3," &
"TL_DATA_7_C1FP_ADD : B4," &
"TL_DATA_8_RAM2_D_1 : A9," &
"TL_DATA_9_RAM2_D_4 : C6," &
"TL_DATA_10_RAM2_D_6 : M4," &
"TL_DATA_11_RAM2_D_8 : P2," &
"TL_DATA_12_RAM2_D_12 : AD9," &
"TL_DATA_13_RAM2_D_14 : AF9," &
"TL_DATA_14 : AF16," &
"TL_DATA_15 : J26," &
"TL_SIG_0_ADETECT : AA4," &
"TL_SIG_1_DPL : V2," &
"TL_SIG_2_DDP : R4," &
"TL_SIG_3_DDATA_1 : L3," &
"TL_SIG_4_DDATA_3 : J3," &
"TL_SIG_5_DDATA_5 : F2," &
"TL_SIG_6_DDATA_7 : D2," &
"TL_SIG_7 : C5," &
"TL_SIG_8_RAM2_D_0 : D11," &
"TL_SIG_9_RAM2_D_3 : D7," &
"TL_SIG_10_RAM2_D_5 : L2," &
"TL_SIG_11_RAM2_P_1 : N2," &
"TL_SIG_12_RAM2_D_11 : AE8," &
"TL_SIG_13_RAM2_D_13 : AD10," &
"TL_SIG_14 : AC14," &
"TL_SIG_15 : L23," &
"TL_SYNC_0_F0B : W3," &
"TL_SYNC_1 : V1," &
"TL_SYNC_2 : R3," &
"TL_SYNC_3 : L4," &
"TL_SYNC_4 : G1," &
"TL_SYNC_5 : G4," &
"TL_SYNC_6 : E4," &
"TL_SYNC_7 : A4," &
"TL_SYNC_8_RAM2_P_0 : B10," &
"TL_SYNC_9_RAM2_D_2 : A5," &
"TL_SYNC_10_RAM2_D_7 : N3," &
"TL_SYNC_11_RAM2_D_9 : AA1," &
"TL_SYNC_12_RAM2_D_10 : AF7," &
"TL_SYNC_13_RAM2_D_15 : AC11," &
"TL_SYNC_14 : AC15," &
"TL_SYNC_15 : K24," &
"TMS : A24," &
"TPHY_ADD_0 : V24," &
"TPHY_ADD_1 : W25," &
"TPHY_ADD_2 : W24," &
"TPHY_ADD_3_TCSB : W23," &
"TPHY_ADD_4_TSX : AA24," &
"TRSTB : AC5," &
"VDD2_5_1 : AF17," &
"VDD2_5_2 : AF6," &
"VDD2_5_3 : W4," &
"VDD2_5_4 : AA26," &
"VDD2_5_5 : L26," &
"VDD2_5_6 : P4," &
"VDD2_5_7 : G23," &
"VDD2_5_8 : A21," &
"VDD2_5_9 : A10," &
"VDD3_3_1 : AD24," &
"VDD3_3_2 : AD3," &
"VDD3_3_3 : AC23," &
"VDD3_3_4 : AC18," &
"VDD3_3_5 : AC13," &
"VDD3_3_6 : AC9," &
"VDD3_3_7 : AC4," &
"VDD3_3_8 : V23," &
"VDD3_3_9 : V4," &
"VDD3_3_10 : P23," &
"VDD3_3_11 : N4," &
"VDD3_3_12 : J23," &
"VDD3_3_13 : J4," &
"VDD3_3_14 : D23," &
"VDD3_3_15 : D18," &
"VDD3_3_16 : D14," &
"VDD3_3_17 : D9," &
"VDD3_3_18 : D4," &
"VDD3_3_19 : C24," &
"VDD3_3_20 : C3," &
"VDD3_3_21 : B25," &
"VDD3_3_22 : B2," &
"VDD3_3_23 : AE25," &
"VDD3_3_24 : AE2," &
"VSS_1 : AF26," &
"VSS_2 : AF25," &
"VSS_3 : AF14," &
"VSS_4 : AF13," &
"VSS_5 : AF2," &
"VSS_6 : AF1," &
"VSS_7 : AE26," &
"VSS_8 : AE24," &
"VSS_9 : AE3," &
"VSS_10 : AE1," &
"VSS_11 : AD25," &
"VSS_12 : AD2," &
"VSS_13 : P26," &
"VSS_14 : P1," &
"VSS_15 : N26," &
"VSS_16 : N1," &
"VSS_17 : C25," &
"VSS_18 : C2," &
"VSS_19 : B26," &
"VSS_20 : B24," &
"VSS_21 : B3," &
"VSS_22 : B1," &
"VSS_23 : A26," &
"VSS_24 : A25," &
"VSS_25 : A14," &
"VSS_26 : A13," &
"VSS_27 : A2," &
"VSS_28 : A1," &
"WRB : AF11";
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_RESET of TRSTB : signal is true;
attribute TAP_SCAN_CLOCK of TCLK : signal is (1.0e6,BOTH);
attribute INSTRUCTION_LENGTH of PM73122 : entity is 3;
attribute INSTRUCTION_OPCODE of PM73122 : entity is
"EXTEST (000)," &
"SAMPLE (010)," &
"IDCODE (001)," &
"BYPASS (011,100,110,111)," &
"STCTEST (101)";
attribute INSTRUCTION_CAPTURE of PM73122 : entity is "001";
attribute IDCODE_REGISTER of PM73122 : entity is
"0010" & -- 4 bit version = 2h
"0111001100010010" & -- 16 bit part number = 7312h
"00001100110" & -- 11 bit manufacturer's code = 0CDh
"1"; -- mandatory LSB by the standard
attribute REGISTER_ACCESS of PM73122 : entity is "Boundary (STCTEST)";
attribute BOUNDARY_CELLS of PM73122 : entity is "BC_1,BC_4,cele0";
attribute BOUNDARY_LENGTH of PM73122 : entity is 508;
attribute BOUNDARY_REGISTER of PM73122 : entity is
--num cell port function safe [ccell disval rslt]
"0 (BC_4, SYSCLK, INPUT, X)," &
"1 (BC_1, *, CONTROL, 1)," &
"2 (CELE0, RAM1_A_0, BIDIR, X, 1, 1, Z)," &
"3 (BC_1, *, CONTROL, 1)," &
"4 (CELE0, RAM1_A_1, BIDIR, X, 3, 1, Z)," &
"5 (BC_1, *, CONTROL, 1)," &
"6 (CELE0, RAM1_A_2, BIDIR, X, 5, 1, Z)," &
"7 (BC_1, *, CONTROL, 1)," &
"8 (CELE0, RAM1_A_3, BIDIR, X, 7, 1, Z)," &
"9 (BC_1, *, CONTROL, 1)," &
"10 (CELE0, RAM1_A_4, BIDIR, X, 9, 1, Z)," &
"11 (BC_1, *, CONTROL, 1)," &
"12 (CELE0, RAM1_A_5, BIDIR, X, 11, 1, Z)," &
"13 (BC_1, *, CONTROL, 1)," &
"14 (BC_1, RAM1_ADSCB_RAM1_R_WB, OUTPUT3, X, 13, 1, Z)," &
"15 (BC_1, *, CONTROL, 1)," &
"16 (CELE0, RAM1_A_6, BIDIR, X, 15, 1, Z)," &
"17 (BC_1, *, CONTROL, 1)," &
"18 (CELE0, RAM1_A_7, BIDIR, X, 17, 1, Z)," &
"19 (BC_1, *, CONTROL, 1)," &
"20 (CELE0, RAM1_A_9, BIDIR, X, 19, 1, Z)," &
"21 (BC_1, *, CONTROL, 1)," &
"22 (BC_1, RAM1_CSB, OUTPUT3, X, 21, 1, Z)," &
"23 (BC_1, *, CONTROL, 1)," &
"24 (CELE0, RAM1_A_10, BIDIR, X, 23, 1, Z)," &
"25 (BC_1, *, CONTROL, 1)," &
"26 (CELE0, RAM1_A_11, BIDIR, X, 25, 1, Z)," &
"27 (BC_1, *, CONTROL, 1)," &
"28 (CELE0, RAM1_A_12, BIDIR, X, 27, 1, Z)," &
"29 (BC_1, *, CONTROL, 1)," &
"30 (CELE0, RAM1_A_13, BIDIR, X, 29, 1, Z)," &
"31 (BC_1, *, CONTROL, 1)," &
"32 (BC_1, RAM1_A_14, OUTPUT3, X, 31, 1, Z)," &
"33 (BC_1, *, CONTROL, 1)," &
"34 (BC_1, RAM1_A_15, OUTPUT3, X, 33, 1, Z)," &
"35 (BC_1, *, CONTROL, 1)," &
"36 (BC_1, RAM1_A_16, OUTPUT3, X, 35, 1, Z)," &
"37 (BC_1, *, CONTROL, 1)," &
"38 (BC_1, RAM1_A_17, OUTPUT3, X, 37, 1, Z)," &
"39 (BC_1, *, CONTROL, 1)," &
"40 (BC_1, RAM1_WEB_0, OUTPUT3, X, 39, 1, Z)," &
"41 (BC_1, *, CONTROL, 1)," &
"42 (CELE0, RAM1_PAR_0, BIDIR, X, 41, 1, Z)," &
"43 (BC_1, *, CONTROL, 1)," &
"44 (CELE0, RAM1_PAR_1, BIDIR, X, 43, 1, Z)," &
"45 (BC_1, *, CONTROL, 1)," &
"46 (CELE0, RAM1_A_8, BIDIR, X, 45, 1, Z)," &
"47 (BC_1, *, CONTROL, 1)," &
"48 (BC_1, RAM1_WEB_1, OUTPUT3, X, 47, 1, Z)," &
"49 (BC_1, *, CONTROL, 1)," &
"50 (CELE0, RAM1_D_0, BIDIR, X, 49, 1, Z)," &
"51 (BC_4, RL_CLK_8_TL_CLK_24, INPUT, X)," &
"52 (BC_1, *, CONTROL, 1)," &
"53 (CELE0, TL_CLK_8, BIDIR, X, 52, 1, Z)," &
"54 (BC_4, RL_CLK_9_TL_CLK_25, INPUT, X)," &
"55 (BC_1, *, CONTROL, 1)," &
"56 (CELE0, TL_CLK_9, BIDIR, X, 55, 1, Z)," &
"57 (BC_1, *, CONTROL, 1)," &
"58 (CELE0, RAM1_D_1, BIDIR, X, 57, 1, Z)," &
"59 (BC_1, *, CONTROL, 1)," &
"60 (CELE0, RAM1_D_2, BIDIR, X, 59, 1, Z)," &
"61 (BC_1, *, CONTROL, 1)," &
"62 (CELE0, RAM1_D_3, BIDIR, X, 61, 1, Z)," &
"63 (BC_1, *, CONTROL, 1)," &
"64 (CELE0, RAM1_D_4, BIDIR, X, 63, 1, Z)," &
"65 (BC_1, *, CONTROL, 1)," &
"66 (CELE0, RAM1_D_5, BIDIR, X, 65, 1, Z)," &
"67 (BC_1, *, CONTROL, 1)," &
"68 (CELE0, RAM1_D_6, BIDIR, X, 67, 1, Z)," &
"69 (BC_1, *, CONTROL, 1)," &
"70 (CELE0, RAM1_D_7, BIDIR, X, 69, 1, Z)," &
"71 (BC_1, *, CONTROL, 1)," &
"72 (CELE0, RAM1_D_8, BIDIR, X, 71, 1, Z)," &
"73 (BC_1, *, CONTROL, 1)," &
"74 (CELE0, RL_SIG_8_RAM2_ADSCB, BIDIR, X, 73, 1, Z)," &
"75 (BC_1, *, CONTROL, 1)," &
"76 (CELE0, RL_SYNC_8_RAM2_CSB, BIDIR, X, 75, 1, Z)," &
"77 (BC_1, *, CONTROL, 1)," &
"78 (CELE0, RL_DATA_8_RAM2_WEB_0, BIDIR, X, 77, 1, Z)," &
"79 (BC_1, *, CONTROL, 1)," &
"80 (CELE0, TL_SYNC_8_RAM2_P_0, BIDIR, X, 79, 1, Z)," &
"81 (BC_1, *, CONTROL, 1)," &
"82 (CELE0, TL_SIG_8_RAM2_D_0, BIDIR, X, 81, 1, Z)," &
"83 (BC_1, *, CONTROL, 1)," &
"84 (CELE0, TL_DATA_8_RAM2_D_1, BIDIR, X, 83, 1, Z)," &
"85 (BC_1, *, CONTROL, 1)," &
"86 (CELE0, RAM1_D_10, BIDIR, X, 85, 1, Z)," &
"87 (BC_1, *, CONTROL, 1)," &
"88 (CELE0, RAM1_D_11, BIDIR, X, 87, 1, Z)," &
"89 (BC_1, *, CONTROL, 1)," &
"90 (BC_1, RAM1_OEB, OUTPUT3, X, 89, 1, Z)," &
"91 (BC_1, *, CONTROL, 1)," &
"92 (CELE0, RAM1_D_12, BIDIR, X, 91, 1, Z)," &
"93 (BC_1, *, CONTROL, 1)," &
"94 (CELE0, RAM1_D_13, BIDIR, X, 93, 1, Z)," &
"95 (BC_1, *, CONTROL, 1)," &
"96 (CELE0, RAM1_D_14, BIDIR, X, 95, 1, Z)," &
"97 (BC_1, *, CONTROL, 1)," &
"98 (CELE0, RAM1_D_15, BIDIR, X, 97, 1, Z)," &
"99 (BC_4, CTL_CLK_C16B_REFCLK, INPUT, X)," &
"100 (BC_4, CRL_CLK_C4B, INPUT, X)," &
"101 (BC_1, *, CONTROL, 1)," &
"102 (CELE0, RAM1_D_9, BIDIR, X, 101, 1, Z)," &
"103 (BC_1, *, CONTROL, 1)," &
"104 (CELE0, RL_SIG_9_RAM2_WEB_1, BIDIR, X, 103, 1, Z)," &
"105 (BC_1, *, CONTROL, 1)," &
"106 (CELE0, RL_SYNC_9_RAM2_OEB, BIDIR, X, 105, 1, Z)," &
"107 (BC_1, *, CONTROL, 1)," &
"108 (CELE0, RL_DATA_9_RAM2_A_0, BIDIR, X, 107, 1, Z)," &
"109 (BC_1, *, CONTROL, 1)," &
"110 (CELE0, TL_SYNC_9_RAM2_D_2, BIDIR, X, 109, 1, Z)," &
"111 (BC_1, *, CONTROL, 1)," &
"112 (CELE0, TL_SIG_9_RAM2_D_3, BIDIR, X, 111, 1, Z)," &
"113 (BC_1, *, CONTROL, 1)," &
"114 (CELE0, TL_DATA_9_RAM2_D_4, BIDIR, X, 113, 1, Z)," &
"115 (BC_4, LINE_MODE_1, INPUT, X)," &
"116 (BC_1, *, CONTROL, 1)," &
"117 (CELE0, TL_SYNC_7, BIDIR, X, 116, 1, Z)," &
"118 (BC_1, *, CONTROL, 1)," &
"119 (CELE0, TL_CLK_7, BIDIR, X, 118, 1, Z)," &
"120 (BC_1, *, CONTROL, 1)," &
"121 (BC_1, TL_SIG_7, OUTPUT3, X, 120, 1, Z)," &
"122 (BC_1, *, CONTROL, 1)," &
"123 (BC_1, TL_DATA_7_C1FP_ADD, OUTPUT3, X, 122, 1, Z)," &
"124 (BC_4, RL_SIG_7, INPUT, X)," &
"125 (BC_4, RL_CLK_7_TL_CLK_23, INPUT, X)," &
"126 (BC_4, RL_SYNC_7, INPUT, X)," &
"127 (BC_4, RL_DATA_7, INPUT, X)," &
"128 (BC_1, *, CONTROL, 1)," &
"129 (CELE0, TL_SYNC_6, BIDIR, X, 128, 1, Z)," &
"130 (BC_1, *, CONTROL, 1)," &
"131 (CELE0, TL_CLK_6, BIDIR, X, 130, 1, Z)," &
"132 (BC_1, *, CONTROL, 1)," &
"133 (CELE0, TL_SIG_6_DDATA_7, BIDIR, X, 132, 1, Z)," &
"134 (BC_1, *, CONTROL, 1)," &
"135 (CELE0, TL_DATA_6_DDATA_6, BIDIR, X, 134, 1, Z)," &
"136 (BC_4, RL_SIG_6, INPUT, X)," &
"137 (BC_4, RL_CLK_6_TL_CLK_22, INPUT, X)," &
"138 (BC_4, RL_SYNC_6, INPUT, X)," &
"139 (BC_4, RL_DATA_6, INPUT, X)," &
"140 (BC_1, *, CONTROL, 1)," &
"141 (CELE0, TL_SYNC_5, BIDIR, X, 140, 1, Z)," &
"142 (BC_1, *, CONTROL, 1)," &
"143 (CELE0, TL_CLK_5, BIDIR, X, 142, 1, Z)," &
"144 (BC_1, *, CONTROL, 1)," &
"145 (CELE0, TL_SIG_5_DDATA_5, BIDIR, X, 144, 1, Z)," &
"146 (BC_1, *, CONTROL, 1)," &
"147 (CELE0, TL_DATA_5_DDATA_4, BIDIR, X, 146, 1, Z)," &
"148 (BC_4, RL_SIG_5, INPUT, X)," &
"149 (BC_4, RL_CLK_5_TL_CLK_21, INPUT, X)," &
"150 (BC_1, *, CONTROL, 1)," &
"151 (CELE0, RL_SYNC_5_ADATA_7, BIDIR, X, 150, 1, Z)," &
"152 (BC_1, *, CONTROL, 1)," &
"153 (CELE0, RL_DATA_5_ADATA_6, BIDIR, X, 152, 1, Z)," &
"154 (BC_1, *, CONTROL, 1)," &
"155 (CELE0, TL_SYNC_4, BIDIR, X, 154, 1, Z)," &
"156 (BC_1, *, CONTROL, 1)," &
"157 (CELE0, TL_CLK_4, BIDIR, X, 156, 1, Z)," &
"158 (BC_1, *, CONTROL, 1)," &
"159 (CELE0, TL_SIG_4_DDATA_3, BIDIR, X, 158, 1, Z)," &
"160 (BC_1, *, CONTROL, 1)," &
"161 (CELE0, TL_DATA_4_DDATA_2, BIDIR, X, 160, 1, Z)," &
"162 (BC_1, *, CONTROL, 1)," &
"163 (CELE0, RL_SIG_4_ADATA_5, BIDIR, X, 162, 1, Z)," &
"164 (BC_4, RL_CLK_4_TL_CLK_20, INPUT, X)," &
"165 (BC_1, *, CONTROL, 1)," &
"166 (CELE0, RL_SYNC_4_ADATA_4, BIDIR, X, 165, 1, Z)," &
"167 (BC_1, *, CONTROL, 1)," &
"168 (CELE0, RL_DATA_4_ADATA_3, BIDIR, X, 167, 1, Z)," &
"169 (BC_1, *, CONTROL, 1)," &
"170 (CELE0, TL_SYNC_3, BIDIR, X, 169, 1, Z)," &
"171 (BC_1, *, CONTROL, 1)," &
"172 (CELE0, TL_CLK_3, BIDIR, X, 171, 1, Z)," &
"173 (BC_1, *, CONTROL, 1)," &
"174 (CELE0, TL_SIG_3_DDATA_1, BIDIR, X, 173, 1, Z)," &
"175 (BC_1, *, CONTROL, 1)," &
"176 (CELE0, TL_DATA_3_DDATA_0, BIDIR, X, 175, 1, Z)," &
"177 (BC_1, *, CONTROL, 1)," &
"178 (CELE0, TL_SIG_10_RAM2_D_5, BIDIR, X, 177, 1, Z)," &
"179 (BC_1, *, CONTROL, 1)," &
"180 (CELE0, TL_DATA_10_RAM2_D_6, BIDIR, X, 179, 1, Z)," &
"181 (BC_4, RL_CLK_3, INPUT, X)," &
"182 (BC_1, *, CONTROL, 1)," &
"183 (CELE0, RL_SIG_10_RAM2_A_1, BIDIR, X, 182, 1, Z)," &
"184 (BC_1, *, CONTROL, 1)," &
"185 (CELE0, RL_SYNC_10_RAM2_A_2, BIDIR, X, 184, 1, Z)," &
"186 (BC_1, *, CONTROL, 1)," &
"187 (CELE0, RL_DATA_10_RAM2_A_3, BIDIR, X, 186, 1, Z)," &
"188 (BC_1, *, CONTROL, 1)," &
"189 (CELE0, TL_SYNC_10_RAM2_D_7, BIDIR, X, 188, 1, Z)," &
"190 (BC_1, *, CONTROL, 1)," &
"191 (CELE0, TL_SIG_11_RAM2_P_1, BIDIR, X, 190, 1, Z)," &
"192 (BC_1, *, CONTROL, 1)," &
"193 (CELE0, TL_DATA_11_RAM2_D_8, BIDIR, X, 192, 1, Z)," &
"194 (BC_1, *, CONTROL, 1)," &
"195 (CELE0, RL_SIG_3_ADATA_2, BIDIR, X, 194, 1, Z)," &
"196 (BC_4, RL_SYNC_3_TL_CLK_19, INPUT, X)," &
"197 (BC_1, *, CONTROL, 1)," &
"198 (CELE0, RL_DATA_3_ADATA_1, BIDIR, X, 197, 1, Z)," &
"199 (BC_1, *, CONTROL, 1)," &
"200 (CELE0, TL_SYNC_2, BIDIR, X, 199, 1, Z)," &
"201 (BC_1, *, CONTROL, 1)," &
"202 (CELE0, TL_CLK_2, BIDIR, X, 201, 1, Z)," &
"203 (BC_1, *, CONTROL, 1)," &
"204 (CELE0, TL_SIG_2_DDP, BIDIR, X, 203, 1, Z)," &
"205 (BC_1, *, CONTROL, 1)," &
"206 (CELE0, TL_DATA_2_DV5, BIDIR, X, 205, 1, Z)," &
"207 (BC_1, *, CONTROL, 1)," &
"208 (CELE0, RL_SIG_2_ADATA_0, BIDIR, X, 207, 1, Z)," &
"209 (BC_4, RL_CLK_2, INPUT, X)," &
"210 (BC_4, RL_SYNC_2_TL_CLK_18, INPUT, X)," &
"211 (BC_1, *, CONTROL, 1)," &
"212 (CELE0, RL_DATA_2_ADP, BIDIR, X, 211, 1, Z)," &
"213 (BC_1, *, CONTROL, 1)," &
"214 (CELE0, TL_SYNC_1, BIDIR, X, 213, 1, Z)," &
"215 (BC_1, *, CONTROL, 1)," &
"216 (CELE0, TL_CLK_1, BIDIR, X, 215, 1, Z)," &
"217 (BC_1, *, CONTROL, 1)," &
"218 (CELE0, TL_SIG_1_DPL, BIDIR, X, 217, 1, Z)," &
"219 (BC_1, *, CONTROL, 1)," &
"220 (CELE0, TL_DATA_1_AJUST_REQ, BIDIR, X, 219, 1, Z)," &
"221 (BC_1, *, CONTROL, 1)," &
"222 (CELE0, RL_SIG_1_APL, BIDIR, X, 221, 1, Z)," &
"223 (BC_4, RL_CLK_1, INPUT, X)," &
"224 (BC_4, RL_SYNC_1_TL_CLK_17, INPUT, X)," &
"225 (BC_1, *, CONTROL, 1)," &
"226 (CELE0, RL_DATA_1_AV5, BIDIR, X, 225, 1, Z)," &
"227 (BC_1, *, CONTROL, 1)," &
"228 (CELE0, TL_SYNC_0_F0B, BIDIR, X, 227, 1, Z)," &
"229 (BC_1, *, CONTROL, 1)," &
"230 (CELE0, TL_CLK_0, BIDIR, X, 229, 1, Z)," &
"231 (BC_1, *, CONTROL, 1)," &
"232 (CELE0, TL_SYNC_11_RAM2_D_9, BIDIR, X, 231, 1, Z)," &
"233 (BC_1, *, CONTROL, 1)," &
"234 (CELE0, RL_DATA_11_RAM2_A_4, BIDIR, X, 233, 1, Z)," &
"235 (BC_1, *, CONTROL, 1)," &
"236 (CELE0, RL_SIG_11_RAM2_A_5, BIDIR, X, 235, 1, Z)," &
"237 (BC_1, *, CONTROL, 1)," &
"238 (CELE0, RL_SYNC_11_RAM2_A_6, BIDIR, X, 237, 1, Z)," &
"239 (BC_1, *, CONTROL, 1)," &
"240 (CELE0, RL_SYNC_12_RAM2_A_7, BIDIR, X, 239, 1, Z)," &
"241 (BC_1, *, CONTROL, 1)," &
"242 (CELE0, RL_DATA_12_RAM2_A_8, BIDIR, X, 241, 1, Z)," &
"243 (BC_1, *, CONTROL, 1)," &
"244 (CELE0, RL_SIG_12_RAM2_A_9, BIDIR, X, 243, 1, Z)," &
"245 (BC_4, LINE_MODE_0, INPUT, X)," &
"246 (BC_1, *, CONTROL, 1)," &
"247 (CELE0, TL_SIG_0_ADETECT, BIDIR, X, 246, 1, Z)," &
"248 (BC_1, *, CONTROL, 1)," &
"249 (CELE0, TL_DATA_0_C1FP, BIDIR, X, 248, 1, Z)," &
"250 (BC_1, *, CONTROL, 1)," &
"251 (CELE0, RL_SIG_0, BIDIR, X, 250, 1, Z)," &
"252 (BC_4, RL_CLK_0, INPUT, X)," &
"253 (BC_1, *, CONTROL, 1)," &
"254 (CELE0, RL_SYNC_0_TL_CLK_16, BIDIR, X, 253, 1, Z)," &
"255 (BC_1, *, CONTROL, 1)," &
"256 (CELE0, RL_DATA_0_AACTIVE, BIDIR, X, 255, 1, Z)," &
"257 (BC_4, RSTB, INPUT, X)," &
"258 (BC_1, *, CONTROL, 1)," &
"259 (BC_1, SRTS_STBH, OUTPUT3, X, 258, 1, Z)," &
"260 (BC_1, *, CONTROL, 1)," &
"261 (BC_1, ADAP_STBH, OUTPUT3, X, 260, 1, Z)," &
"262 (BC_1, *, CONTROL, 1)," &
"263 (BC_1, CGC_LINE_4, OUTPUT3, X, 262, 1, Z)," &
"264 (BC_1, *, CONTROL, 1)," &
"265 (BC_1, CGC_LINE_3, OUTPUT3, X, 264, 1, Z)," &
"266 (BC_1, *, CONTROL, 1)," &
"267 (BC_1, CGC_LINE_2, OUTPUT3, X, 266, 1, Z)," &
"268 (BC_1, *, CONTROL, 1)," &
"269 (BC_1, CGC_LINE_1, OUTPUT3, X, 268, 1, Z)," &
"270 (BC_1, *, CONTROL, 1)," &
"271 (BC_1, CGC_LINE_0, OUTPUT3, X, 270, 1, Z)," &
"272 (BC_1, *, CONTROL, 1)," &
"273 (CELE0, CGC_SER_D, BIDIR, X, 272, 1, Z)," &
"274 (BC_1, *, CONTROL, 1)," &
"275 (CELE0, CGC_VALID, BIDIR, X, 274, 1, Z)," &
"276 (BC_1, *, CONTROL, 1)," &
"277 (CELE0, TL_CLK_OE, BIDIR, X, 276, 1, Z)," &
"278 (BC_4, NCLK_SRTS_DISB, INPUT, X)," &
"279 (BC_1, *, CONTROL, 1)," &
"280 (BC_1, CGC_DOUT_3, OUTPUT3, X, 279, 1, Z)," &
"281 (BC_1, *, CONTROL, 1)," &
"282 (BC_1, CGC_DOUT_1, OUTPUT3, X, 281, 1, Z)," &
"283 (BC_1, *, CONTROL, 1)," &
"284 (BC_1, CGC_DOUT_0, OUTPUT3, X, 283, 1, Z)," &
"285 (BC_1, *, CONTROL, 1)," &
"286 (CELE0, TL_SYNC_12_RAM2_D_10, BIDIR, X, 285, 1, Z)," &
"287 (BC_1, *, CONTROL, 1)," &
"288 (CELE0, TL_SIG_12_RAM2_D_11, BIDIR, X, 287, 1, Z)," &
"289 (BC_1, *, CONTROL, 1)," &
"290 (CELE0, TL_DATA_12_RAM2_D_12, BIDIR, X, 289, 1, Z)," &
"291 (BC_1, *, CONTROL, 1)," &
"292 (CELE0, RL_SIG_13_RAM2_A_10, BIDIR, X, 291, 1, Z)," &
"293 (BC_1, *, CONTROL, 1)," &
"294 (CELE0, RL_SYNC_13_RAM2_A_11, BIDIR, X, 293, 1, Z)," &
"295 (BC_1, *, CONTROL, 1)," &
"296 (CELE0, RL_DATA_13_RAM2_A_12, BIDIR, X, 295, 1, Z)," &
"297 (BC_1, *, CONTROL, 1)," &
"298 (CELE0, TL_SIG_13_RAM2_D_13, BIDIR, X, 297, 1, Z)," &
"299 (BC_1, *, CONTROL, 1)," &
"300 (CELE0, TL_DATA_13_RAM2_D_14, BIDIR, X, 299, 1, Z)," &
"301 (BC_1, *, CONTROL, 1)," &
"302 (CELE0, TL_SYNC_13_RAM2_D_15, BIDIR, X, 301, 1, Z)," &
"303 (BC_1, *, CONTROL, 1)," &
"304 (BC_1, INTB, OUTPUT3, X, 303, 1, WEAK1)," &
"305 (BC_1, *, CONTROL, 1)," &
"306 (BC_1, ACKB, OUTPUT3, X, 305, 1, WEAK1)," &
"307 (BC_1, *, CONTROL, 1)," &
"308 (BC_1, CGC_DOUT_2, OUTPUT3, X, 307, 1, Z)," &
"309 (BC_4, CSB, INPUT, X)," &
"310 (BC_4, RDB, INPUT, X)," &
"311 (BC_4, WRB, INPUT, X)," &
"312 (BC_4, ALE, INPUT, X)," &
"313 (BC_4, A_0, INPUT, X)," &
"314 (BC_4, A_1, INPUT, X)," &
"315 (BC_4, A_2, INPUT, X)," &
"316 (BC_4, A_3, INPUT, X)," &
"317 (BC_1, *, CONTROL, 1)," &
"318 (CELE0, D_0, BIDIR, X, 317, 1, Z)," &
"319 (BC_1, *, CONTROL, 1)," &
"320 (CELE0, D_1, BIDIR, X, 319, 1, Z)," &
"321 (BC_1, *, CONTROL, 1)," &
"322 (BC_1, TL_SIG_14, OUTPUT3, X, 321, 1, Z)," &
"323 (BC_1, *, CONTROL, 1)," &
"324 (CELE0, RL_SIG_14_RAM2_A_13, BIDIR, X, 323, 1, Z)," &
"325 (BC_1, *, CONTROL, 1)," &
"326 (CELE0, RL_SYNC_14_RAM2_A_14, BIDIR, X, 325, 1, Z)," &
"327 (BC_1, *, CONTROL, 1)," &
"328 (CELE0, RL_DATA_14_RAM2_A_15, BIDIR, X, 327, 1, Z)," &
"329 (BC_1, *, CONTROL, 1)," &
"330 (BC_1, TL_DATA_14, OUTPUT3, X, 329, 1, Z)," &
"331 (BC_1, *, CONTROL, 1)," &
"332 (CELE0, TL_SYNC_14, BIDIR, X, 331, 1, Z)," &
"333 (BC_1, *, CONTROL, 1)," &
"334 (CELE0, RL_SIG_15_RAM2_A_16, BIDIR, X, 333, 1, Z)," &
"335 (BC_1, *, CONTROL, 1)," &
"336 (CELE0, RL_DATA_15_RAM2_A_17, BIDIR, X, 335, 1, Z)," &
"337 (BC_1, *, CONTROL, 1)," &
"338 (CELE0, D_3, BIDIR, X, 337, 1, Z)," &
"339 (BC_4, A_4, INPUT, X)," &
"340 (BC_4, A_5, INPUT, X)," &
"341 (BC_4, A_6, INPUT, X)," &
"342 (BC_4, A_7, INPUT, X)," &
"343 (BC_1, *, CONTROL, 1)," &
"344 (CELE0, D_4, BIDIR, X, 343, 1, Z)," &
"345 (BC_1, *, CONTROL, 1)," &
"346 (CELE0, D_5, BIDIR, X, 345, 1, Z)," &
"347 (BC_1, *, CONTROL, 1)," &
"348 (CELE0, D_6, BIDIR, X, 347, 1, Z)," &
"349 (BC_1, *, CONTROL, 1)," &
"350 (CELE0, D_7, BIDIR, X, 349, 1, Z)," &
"351 (BC_4, A_8, INPUT, X)," &
"352 (BC_4, A_9, INPUT, X)," &
"353 (BC_4, A_10, INPUT, X)," &
"354 (BC_1, *, CONTROL, 1)," &
"355 (CELE0, D_2, BIDIR, X, 354, 1, Z)," &
"356 (BC_4, A_11, INPUT, X)," &
"357 (BC_1, *, CONTROL, 1)," &
"358 (CELE0, D_8, BIDIR, X, 357, 1, Z)," &
"359 (BC_1, *, CONTROL, 1)," &
"360 (CELE0, D_9, BIDIR, X, 359, 1, Z)," &
"361 (BC_1, *, CONTROL, 1)," &
"362 (CELE0, D_10, BIDIR, X, 361, 1, Z)," &
"363 (BC_1, *, CONTROL, 1)," &
"364 (CELE0, D_11, BIDIR, X, 363, 1, Z)," &
"365 (BC_4, A_12, INPUT, X)," &
"366 (BC_4, A_13, INPUT, X)," &
"367 (BC_4, A_14, INPUT, X)," &
"368 (BC_4, A_15, INPUT, X)," &
"369 (BC_1, *, CONTROL, 1)," &
"370 (CELE0, D_12, BIDIR, X, 369, 1, Z)," &
"371 (BC_1, *, CONTROL, 1)," &
"372 (CELE0, D_13, BIDIR, X, 371, 1, Z)," &
"373 (BC_1, *, CONTROL, 1)," &
"374 (CELE0, D_14, BIDIR, X, 373, 1, Z)," &
"375 (BC_1, *, CONTROL, 1)," &
"376 (CELE0, D_15, BIDIR, X, 375, 1, Z)," &
"377 (BC_4, A_16, INPUT, X)," &
"378 (BC_4, A_17, INPUT, X)," &
"379 (BC_4, A_18, INPUT, X)," &
"380 (BC_4, A_19, INPUT, X)," &
"381 (BC_1, *, CONTROL, 1)," &
"382 (CELE0, RATM_D_15_TPHY_D_15, BIDIR, X, 381, 1, Z)," &
"383 (BC_1, *, CONTROL, 1)," &
"384 (CELE0, RATM_D_14_TPHY_D_14, BIDIR, X, 383, 1, Z)," &
"385 (BC_1, *, CONTROL, 1)," &
"386 (CELE0, RATM_D_13_TPHY_D_13, BIDIR, X, 385, 1, Z)," &
"387 (BC_1, *, CONTROL, 1)," &
"388 (CELE0, RATM_D_12_TPHY_D_12, BIDIR, X, 387, 1, Z)," &
"389 (BC_1, *, CONTROL, 1)," &
"390 (CELE0, TPHY_ADD_4_TSX, BIDIR, X, 389, 1, Z)," &
"391 (BC_1, *, CONTROL, 1)," &
"392 (CELE0, RATM_D_11_TPHY_D_11, BIDIR, X, 391, 1, Z)," &
"393 (BC_1, *, CONTROL, 1)," &
"394 (CELE0, RATM_D_10_TPHY_D_10, BIDIR, X, 393, 1, Z)," &
"395 (BC_1, *, CONTROL, 1)," &
"396 (CELE0, RATM_D_9_TPHY_D_9, BIDIR, X, 395, 1, Z)," &
"397 (BC_1, *, CONTROL, 1)," &
"398 (CELE0, RATM_D_8_TPHY_D_8, BIDIR, X, 397, 1, Z)," &
"399 (BC_1, *, CONTROL, 1)," &
"400 (CELE0, TPHY_ADD_3_TCSB, BIDIR, X, 399, 1, Z)," &
"401 (BC_1, *, CONTROL, 1)," &
"402 (CELE0, RATM_PAR_TPHY_PAR, BIDIR, X, 401, 1, Z)," &
"403 (BC_1, *, CONTROL, 1)," &
"404 (CELE0, TPHY_ADD_2, BIDIR, X, 403, 1, Z)," &
"405 (BC_4, RATM_CLK_TPHY_CLK, INPUT, X)," &
"406 (BC_1, *, CONTROL, 1)," &
"407 (CELE0, TPHY_ADD_1, BIDIR, X, 406, 1, Z)," &
"408 (BC_1, *, CONTROL, 1)," &
"409 (CELE0, TPHY_ADD_0, BIDIR, X, 408, 1, Z)," &
"410 (BC_1, *, CONTROL, 1)," &
"411 (CELE0, RATM_CLAV_TPHY_CLAV, BIDIR, X, 410, 1, Z)," &
"412 (BC_1, *, CONTROL, 1)," &
"413 (CELE0, RATM_SOC_TPHY_SOC_TSOP, BIDIR, X, 412, 1, Z)," &
"414 (BC_1, *, CONTROL, 1)," &
"415 (CELE0, RATM_D_7_TPHY_D_7, BIDIR, X, 414, 1, Z)," &
"416 (BC_1, *, CONTROL, 1)," &
"417 (CELE0, RATM_D_6_TPHY_D_6, BIDIR, X, 416, 1, Z)," &
"418 (BC_1, *, CONTROL, 1)," &
"419 (CELE0, RATM_D_5_TPHY_D_5, BIDIR, X, 418, 1, Z)," &
"420 (BC_1, *, CONTROL, 1)," &
"421 (CELE0, RATM_D_4_TPHY_D_4, BIDIR, X, 420, 1, Z)," &
"422 (BC_1, *, CONTROL, 1)," &
"423 (CELE0, RATM_ENB_TPHY_ENB, BIDIR, X, 422, 1, Z)," &
"424 (BC_1, *, CONTROL, 1)," &
"425 (CELE0, RATM_D_3_TPHY_D_3, BIDIR, X, 424, 1, Z)," &
"426 (BC_1, *, CONTROL, 1)," &
"427 (CELE0, RATM_D_2_TPHY_D_2, BIDIR, X, 426, 1, Z)," &
"428 (BC_1, *, CONTROL, 1)," &
"429 (CELE0, RATM_D_1_TPHY_D_1, BIDIR, X, 428, 1, Z)," &
"430 (BC_4, RL_CLK_12_TL_CLK_28, INPUT, X)," &
"431 (BC_1, *, CONTROL, 1)," &
"432 (CELE0, TL_CLK_12, BIDIR, X, 431, 1, Z)," &
"433 (BC_4, RL_CLK_13_TL_CLK_29, INPUT, X)," &
"434 (BC_1, *, CONTROL, 1)," &
"435 (CELE0, TL_CLK_13, BIDIR, X, 434, 1, Z)," &
"436 (BC_1, *, CONTROL, 1)," &
"437 (CELE0, RATM_D_0_TPHY_D_0, BIDIR, X, 436, 1, Z)," &
"438 (BC_1, *, CONTROL, 1)," &
"439 (CELE0, TATM_D_3_RPHY_D_3, BIDIR, X, 438, 1, Z)," &
"440 (BC_4, RL_CLK_14_TL_CLK_30, INPUT, X)," &
"441 (BC_1, *, CONTROL, 1)," &
"442 (CELE0, TL_CLK_14, BIDIR, X, 441, 1, Z)," &
"443 (BC_4, RL_SYNC_15, INPUT, X)," &
"444 (BC_4, RL_CLK_15_TL_CLK_31, INPUT, X)," &
"445 (BC_1, *, CONTROL, 1)," &
"446 (CELE0, TATM_D_0_RPHY_D_0, BIDIR, X, 445, 1, Z)," &
"447 (BC_1, *, CONTROL, 1)," &
"448 (CELE0, TATM_D_1_RPHY_D_1, BIDIR, X, 447, 1, Z)," &
"449 (BC_1, *, CONTROL, 1)," &
"450 (CELE0, TATM_D_2_RPHY_D_2, BIDIR, X, 449, 1, Z)," &
"451 (BC_1, *, CONTROL, 1)," &
"452 (CELE0, TATM_CLAV_RPHY_CLAV_RPA, BIDIR, X, 451, 1, Z)," &
"453 (BC_1, *, CONTROL, 1)," &
"454 (CELE0, TATM_D_4_RPHY_D_4, BIDIR, X, 453, 1, Z)," &
"455 (BC_1, *, CONTROL, 1)," &
"456 (CELE0, TATM_D_5_RPHY_D_5, BIDIR, X, 455, 1, Z)," &
"457 (BC_1, *, CONTROL, 1)," &
"458 (CELE0, TATM_D_6_RPHY_D_6, BIDIR, X, 457, 1, Z)," &
"459 (BC_1, *, CONTROL, 1)," &
"460 (CELE0, TATM_D_7_RPHY_D_7, BIDIR, X, 459, 1, Z)," &
"461 (BC_1, *, CONTROL, 1)," &
"462 (BC_1, TL_SIG_15, OUTPUT3, X, 461, 1, Z)," &
"463 (BC_1, *, CONTROL, 1)," &
"464 (BC_1, TL_DATA_15, OUTPUT3, X, 463, 1, Z)," &
"465 (BC_1, *, CONTROL, 1)," &
"466 (CELE0, TL_SYNC_15, BIDIR, X, 465, 1, Z)," &
"467 (BC_1, *, CONTROL, 1)," &
"468 (CELE0, TL_CLK_15, BIDIR, X, 467, 1, Z)," &
"469 (BC_1, *, CONTROL, 1)," &
"470 (CELE0, TL_CLK_11, BIDIR, X, 469, 1, Z)," &
"471 (BC_4, RL_CLK_11_TL_CLK_27, INPUT, X)," &
"472 (BC_1, *, CONTROL, 1)," &
"473 (CELE0, TL_CLK_10, BIDIR, X, 472, 1, Z)," &
"474 (BC_4, RL_CLK_10_TL_CLK_26, INPUT, X)," &
"475 (BC_1, *, CONTROL, 1)," &
"476 (CELE0, TATM_SOC_RPHY_SOC_RSOP, BIDIR, X, 475, 1, Z)," &
"477 (BC_1, *, CONTROL, 1)," &
"478 (CELE0, TATM_ENB_RPHY_ENB_RENB, BIDIR, X, 477, 1, Z)," &
"479 (BC_1, *, CONTROL, 1)," &
"480 (CELE0, RPHY_ADD_0, BIDIR, X, 479, 1, Z)," &
"481 (BC_4, TATM_CLK_RPHY_CLK, INPUT, X)," &
"482 (BC_1, *, CONTROL, 1)," &
"483 (CELE0, RPHY_ADD_1, BIDIR, X, 482, 1, Z)," &
"484 (BC_1, *, CONTROL, 1)," &
"485 (CELE0, RPHY_ADD_3_RCSB, BIDIR, X, 484, 1, Z)," &
"486 (BC_1, *, CONTROL, 1)," &
"487 (CELE0, RPHY_ADD_2, BIDIR, X, 486, 1, Z)," &
"488 (BC_1, *, CONTROL, 1)," &
"489 (CELE0, TATM_PAR_RPHY_PAR, BIDIR, X, 488, 1, Z)," &
"490 (BC_1, *, CONTROL, 1)," &
"491 (CELE0, TATM_D_8_RPHY_D_8, BIDIR, X, 490, 1, Z)," &
"492 (BC_1, *, CONTROL, 1)," &
"493 (CELE0, TATM_D_9_RPHY_D_9, BIDIR, X, 492, 1, Z)," &
"494 (BC_1, *, CONTROL, 1)," &
"495 (CELE0, TATM_D_10_RPHY_D_10, BIDIR, X, 494, 1, Z)," &
"496 (BC_1, *, CONTROL, 1)," &
"497 (CELE0, TATM_D_11_RPHY_D_11, BIDIR, X, 496, 1, Z)," &
"498 (BC_1, *, CONTROL, 1)," &
"499 (CELE0, RPHY_ADD_RSX, BIDIR, X, 498, 1, Z)," &
"500 (BC_1, *, CONTROL, 1)," &
"501 (CELE0, TATM_D_12_RPHY_D_12, BIDIR, X, 500, 1, Z)," &
"502 (BC_1, *, CONTROL, 1)," &
"503 (CELE0, TATM_D_13_RPHY_D_13, BIDIR, X, 502, 1, Z)," &
"504 (BC_1, *, CONTROL, 1)," &
"505 (CELE0, TATM_D_14_RPHY_D_14, BIDIR, X, 504, 1, Z)," &
"506 (BC_1, *, CONTROL, 1)," &
"507 (CELE0, TATM_D_15_RPHY_D_15, BIDIR, X, 506, 1, Z)";
end PM73122;