-- ********************************************************
-- Document Number: 35A3010.BS001.02
-- Company: Integrated Device Technology, Inc.
-- BSDL file for design CA91C142D
-- Created by Testgen (Nov 27, 1998)
-- Designer: Bruno Latulippe
-- Date: Thursday March 19 1999
-- Revision History
-- 35A3010_BS001_02 release, Sept 3, 2009, Updated with IDT formatting
-- ********************************************************
entity CA91C142D is
-- BSDL file for Univ2d
-- This section identifies the default device package selected.
generic (PHYSICAL_PIN_MAP : string := "UNDEFINED");
-- This section declares all the ports in the design.
port (
trst :in bit;
lclk :linkage bit;
clk64 :in bit;
gnt :in bit;
idsel :in bit;
pwrrst :in bit;
rst :in bit;
tck :in bit;
tdi :in bit;
tmode_2 :in bit;
tmode_1 :in bit;
tmode_0 :in bit;
tms :in bit;
vme_reset :in bit;
vbgi_3 :in bit;
vbgi_2 :in bit;
vbgi_1 :in bit;
vbgi_0 :in bit;
viacki :in bit;
vracfail :in bit;
vrbbsy :in bit;
vrberr :in bit;
vrbr_3 :in bit;
vrbr_2 :in bit;
vrbr_1 :in bit;
vrbr_0 :in bit;
vrirq_7 :in bit;
vrirq_6 :in bit;
vrirq_5 :in bit;
vrirq_4 :in bit;
vrirq_3 :in bit;
vrirq_2 :in bit;
vrirq_1 :in bit;
vrsysfail :in bit;
vrsysrst :in bit;
pll_testsel :linkage bit;
bidir_ctl :linkage bit;
test_ram_we :linkage bit;
devsel :inout bit;
int_7 :inout bit;
int_6 :inout bit;
int_5 :inout bit;
int_4 :inout bit;
int_3 :inout bit;
int_2 :inout bit;
int_1 :inout bit;
int_0 :inout bit;
ack64 :inout bit;
ad_63 :inout bit;
ad_62 :inout bit;
ad_61 :inout bit;
ad_60 :inout bit;
ad_59 :inout bit;
ad_58 :inout bit;
ad_57 :inout bit;
ad_56 :inout bit;
ad_55 :inout bit;
ad_54 :inout bit;
ad_53 :inout bit;
ad_52 :inout bit;
ad_51 :inout bit;
ad_50 :inout bit;
ad_49 :inout bit;
ad_48 :inout bit;
ad_47 :inout bit;
ad_46 :inout bit;
ad_45 :inout bit;
ad_44 :inout bit;
ad_43 :inout bit;
ad_42 :inout bit;
ad_41 :inout bit;
ad_40 :inout bit;
ad_39 :inout bit;
ad_38 :inout bit;
ad_37 :inout bit;
ad_36 :inout bit;
ad_35 :inout bit;
ad_34 :inout bit;
ad_33 :inout bit;
ad_32 :inout bit;
ad_31 :inout bit;
ad_30 :inout bit;
ad_29 :inout bit;
ad_28 :inout bit;
ad_27 :inout bit;
ad_26 :inout bit;
ad_25 :inout bit;
ad_24 :inout bit;
ad_23 :inout bit;
ad_22 :inout bit;
ad_21 :inout bit;
ad_20 :inout bit;
ad_19 :inout bit;
ad_18 :inout bit;
ad_17 :inout bit;
ad_16 :inout bit;
ad_15 :inout bit;
ad_14 :inout bit;
ad_13 :inout bit;
ad_12 :inout bit;
ad_11 :inout bit;
ad_10 :inout bit;
ad_9 :inout bit;
ad_8 :inout bit;
ad_7 :inout bit;
ad_6 :inout bit;
ad_5 :inout bit;
ad_4 :inout bit;
ad_3 :inout bit;
ad_2 :inout bit;
ad_1 :inout bit;
ad_0 :inout bit;
cbe_7 :inout bit;
cbe_6 :inout bit;
cbe_5 :inout bit;
cbe_4 :inout bit;
cbe_3 :inout bit;
cbe_2 :inout bit;
cbe_1 :inout bit;
cbe_0 :inout bit;
frame :inout bit;
irdy :inout bit;
lock :inout bit;
par :inout bit;
par64 :inout bit;
perr :inout bit;
req64 :inout bit;
stop :inout bit;
trdy :inout bit;
va_31 :inout bit;
va_30 :inout bit;
va_29 :inout bit;
va_28 :inout bit;
va_27 :inout bit;
va_26 :inout bit;
va_25 :inout bit;
va_24 :inout bit;
va_23 :inout bit;
va_22 :inout bit;
va_21 :inout bit;
va_20 :inout bit;
va_19 :inout bit;
va_18 :inout bit;
va_17 :inout bit;
va_16 :inout bit;
va_15 :inout bit;
va_14 :inout bit;
va_13 :inout bit;
va_12 :inout bit;
va_11 :inout bit;
va_10 :inout bit;
va_9 :inout bit;
va_8 :inout bit;
va_7 :inout bit;
va_6 :inout bit;
va_5 :inout bit;
va_4 :inout bit;
va_3 :inout bit;
va_2 :inout bit;
va_1 :inout bit;
vam_5 :inout bit;
vam_4 :inout bit;
vam_3 :inout bit;
vam_2 :inout bit;
vam_1 :inout bit;
vam_0 :inout bit;
vas :inout bit;
vd_31 :inout bit;
vd_30 :inout bit;
vd_29 :inout bit;
vd_28 :inout bit;
vd_27 :inout bit;
vd_26 :inout bit;
vd_25 :inout bit;
vd_24 :inout bit;
vd_23 :inout bit;
vd_22 :inout bit;
vd_21 :inout bit;
vd_20 :inout bit;
vd_19 :inout bit;
vd_18 :inout bit;
vd_17 :inout bit;
vd_16 :inout bit;
vd_15 :inout bit;
vd_14 :inout bit;
vd_13 :inout bit;
vd_12 :inout bit;
vd_11 :inout bit;
vd_10 :inout bit;
vd_9 :inout bit;
vd_8 :inout bit;
vd_7 :inout bit;
vd_6 :inout bit;
vd_5 :inout bit;
vd_4 :inout bit;
vd_3 :inout bit;
vd_2 :inout bit;
vd_1 :inout bit;
vd_0 :inout bit;
vds_1 :inout bit;
vds_0 :inout bit;
vdtack :inout bit;
viack :inout bit;
vlword :inout bit;
vsysclk :inout bit;
vwrite :inout bit;
tdo :out bit;
lrst :out bit;
pll_testout :linkage bit;
req :out bit;
vbclr :out bit;
vscon_dir :out bit;
vxbbsy :out bit;
vxbr_0 :out bit;
vxbr_1 :out bit;
vxbr_2 :out bit;
vxbr_3 :out bit;
serr :out bit;
vas_dir :out bit;
vbgo_1 :out bit;
vbgo_2 :out bit;
vbgo_3 :out bit;
vbgo_0 :out bit;
vam_dir :out bit;
vds_dir :out bit;
vxsysrst :out bit;
vxberr :out bit;
va_dir :out bit;
voe :out bit;
vd_dir :out bit;
vxirq_3 :out bit;
vxirq_1 :out bit;
vxirq_2 :out bit;
vxirq_7 :out bit;
vxirq_6 :out bit;
vxirq_5 :out bit;
vxirq_4 :out bit;
vslave_dir :out bit;
viacko :out bit;
vxsysfail :out bit;
AVDD : linkage bit;
AVSS : linkage bit;
GND_pbga : linkage bit_vector (1 to 33);
PWR_pbga : linkage bit_vector (1 to 38);
GND_dbga : linkage bit_vector (1 to 57);
PWR_dbga : linkage bit_vector (1 to 49)
);
use STD_1149_1_1990.all;
attribute PIN_MAP of CA91C142D: entity is PHYSICAL_PIN_MAP;
-- This section specifies the pin map for each port.
constant pbga_package:PIN_MAP_STRING:=
" vxirq_1: J19," &
" vxirq_2: K24," &
" vxirq_3: K18," &
" vxirq_4: J25," &
" vxirq_5: L23," &
" vxirq_6: M22," &
" vxirq_7: R25," &
" vrsysfail: AC13," &
" viack: E7," &
" tck:H12," &
" vbclr:N3," &
" par:P8," &
" vrberr:A7," &
" va_1:H14," &
" va_2:A15," &
" va_3:F14," &
" va_4:J15," &
" va_5:D14," &
" va_6:G17," &
" va_7:H16," &
" va_8:B16," &
" va_9:C17," &
" va_10:D16," &
" va_11:A19," &
" va_12:B18," &
" va_13:F16," &
" va_14:E17," &
" va_15:A21," &
" va_16:F18," &
" va_17:D18," &
" va_18:C19," &
" va_19:B20," &
" va_20:B22," &
" va_21:D20," &
" va_22:F20," &
" va_23:E19," &
" va_24:A25," &
" va_25:E23," &
" va_26:C25," &
" va_27:G21," &
" va_28:E21," &
" va_29:F22," &
" va_30:D24," &
" va_31:F24," &
" vme_reset:V22," &
" int_0:K20," &
" int_1:AA5," &
" int_2:L9," &
" int_3:V6," &
" int_4:M4," &
" int_5:L3," &
" int_6:M8," &
" int_7:L1," &
" test_ram_we:AE21," &
" trdy:AD8," &
" ad_0:P16," &
" ad_1:P22," &
" ad_2:R19," &
" ad_3:T18," &
" ad_4:T22," &
" ad_5:T20," &
" ad_6:AA25," &
" ad_7:AB24," &
" ad_8:AB22," &
" ad_9:AE25," &
" ad_10:AC21," &
" ad_11:AB20," &
" ad_12:AC19," &
" ad_13:AA17," &
" ad_14:AA15," &
" ad_15:U15," &
" ad_16:AE11," &
" ad_17:AB12," &
" ad_18:W9," &
" ad_19:AD10," &
" ad_20:AE7," &
" ad_21:Y8," &
" ad_22:AD4," &
" ad_23:Y6," &
" ad_24:Y2," &
" ad_25:V4," &
" ad_26:U5," &
" ad_27:W1," &
" ad_28:U7," &
" ad_29:T8," &
" ad_30:P6," &
" ad_31:P10," &
" ad_32:L17," &
" ad_33:N19," &
" ad_34:R23," &
" ad_35:U19," &
" ad_36:U23," &
" ad_37:W25," &
" ad_38:U21," &
" ad_39:V20," &
" ad_40:Y22," &
" ad_41:W21," &
" ad_42:AD22," &
" ad_43:Y20," &
" ad_44:AD20," &
" ad_45:Y18," &
" ad_46:AE19," &
" ad_47:AD16," &
" ad_48:V12," &
" ad_49:Y12," &
" ad_50:AC11," &
" ad_51:V10," &
" ad_52:AB10," &
" ad_53:AA9," &
" ad_54:AB8," &
" ad_55:AB6," &
" ad_56:Y4," &
" ad_57:W3," &
" ad_58:AA1," &
" ad_59:V2," &
" ad_60:R5," &
" ad_61:T2," &
" ad_62:R9," &
" ad_63:N5," &
" vscon_dir:M2," &
" vd_0:J7," &
" vd_1:K8," &
" vd_2:K2," &
" vd_3:J3," &
" vd_4:K4," &
" vd_5:G1," &
" vd_6:H2," &
" vd_7:K6," &
" vd_8:J5," &
" vd_9:E1," &
" vd_10:H6," &
" vd_11:H4," &
" vd_12:G3," &
" vd_13:F2," &
" vd_14:D2," &
" vd_15:F4," &
" vd_16:F6," &
" vd_17:G5," &
" vd_18:B2," &
" vd_19:C1," &
" vd_20:E3," &
" vd_21:C3," &
" vd_22:A1," &
" vd_23:A3," &
" vd_24:C5," &
" vd_25:D6," &
" vd_26:B4," &
" vd_27:B6," &
" vd_28:C7," &
" vd_29:F8," &
" vd_30:A5," &
" vd_31:E9," &
" vam_dir:B8," &
" stop:AB18," &
" idsel:AB16," &
" par64:AE5," &
" vrbr_0:W5," &
" vrbr_1:U1," &
" vrbr_2:R3," &
" vrbr_3:L7," &
" vrbbsy:M6," &
" clk64:C23," &
" vxbr_0:G25," &
" vxbr_1:H24," &
" vxbr_2:P24," &
" vxbr_3:G23," &
" vam_0:E11," &
" vam_1:D10," &
" vam_2:G9," &
" vam_3:B10," &
" vam_4:H10," &
" vam_5:A9," &
" ack64:W11," &
" vxberr:D12," &
" vlword:K14," &
" vas:B14," &
" vbgo_0:M20," &
" vbgo_1:L25," &
" vbgo_2:M18," &
" vbgo_3:M24," &
" vracfail:P18," &
" pwrrst:T4," &
" trst:E13," &
" va_dir:G13," &
" vrirq_1:H22," &
" vrirq_2:H20," &
" vrirq_3:E25," &
" vrirq_4:J21," &
" vrirq_5:V16," &
" vrirq_6:P20," &
" vrirq_7:R17," &
" req64:AD18," &
" tms:C11," &
" lock:AA23," &
" vxbbsy:P2," &
" vxsysfail:M10," &
" vdtack:G15," &
" viacko:L21," &
" lclk:AA3," &
" vrsysrst:C21," &
" vsysclk:N7," &
" vxsysrst:A23," &
" gnt:AE17," &
" irdy:AC15," &
" pll_testsel:AC1," &
" perr:AB4," &
" tmode_0:AA13," &
" tmode_1:AA21," &
" tmode_2:W23," &
" vwrite:D8," &
" cbe_0:Y14," &
" cbe_1:V14," &
" cbe_2:T14," &
" cbe_3:W13," &
" cbe_4:AE15," &
" cbe_5:AD14," &
" cbe_6:T12," &
" cbe_7:AD12," &
" vbgi_0:N21," &
" vbgi_1:M16," &
" vbgi_2:N25," &
" vbgi_3:N23," &
" rst:AA19," &
" tdi:A13," &
" vd_dir:F10," &
" req:K22," &
" vas_dir:K12," &
" voe:B12," &
" pll_testout:AB2," &
" viacki:AE23," &
" vds_dir:J11," &
" tdo:C13," &
" serr:AA7," &
" vslave_dir:C15," &
" bidir_ctl:AE3," &
" vds_0:F12," &
" vds_1:A11," &
" frame:W17," &
" devsel:AC7," &
" lrst:R1," &
" AVDD:AC5," &
" AVSS:AE1," &
" GND_pbga: (AB14, AC9, AC25, AD6, AE13, J13, K10, K16, L11, " &
" L13, L15, M12, M14, N1, N9, N11, N13, N15, N17, P4, P12, P14," &
" R11, R13, R15, T6, T16, T24, U11, U13, V24, Y10, Y16)," &
" PWR_pbga: (A17, AA11, AC3, AC17, AC23, AD2, AD24, AE9, B24, " &
" C9, D4, D22, E5, E15, G7, G11, G19, H8, H18, J1, J9, J17, " &
" J23, L5, L19, R7, R21, T10, U3, U9, U17, U25, V8, V18, W7, " &
" W15, W19, Y24)";
constant dbga_package:PIN_MAP_STRING:=
" vd_20 : E05," &
" vd_19 : E04," &
" vd_18 : E06," &
" vd_17 : G08," &
" vd_16 : E03," &
" vd_15 : D02," &
" vd_14 : F04," &
" vd_13 : D03," &
" vd_12 : F02," &
" vd_11 : F05," &
" vd_10 : G02," &
" vd_9 : D01," &
" vd_8 : G05," &
" vd_7 : E02," &
" vd_6 : G03," &
" vd_5 : G06," &
" vd_4 : G09," &
" vd_3 : G01," &
" vd_2 : H05," &
" vd_1 : E01," &
" vd_0 : H04," &
" vrbr_3 : H02," &
" int_5 : H07," &
" int_4 : J03," &
" int_2 : J02," &
" vrbbsy : K02," &
" int_7 : J04," &
" int_6 : H06," &
" vscon_dir : J01," &
" vxsysfail : K07," &
" vsysclk : K04," &
" vbclr : J05," &
" ad_31 : K06," &
" ad_63 : K03 ," &
" vxbbsy : K05," &
" par : L02," &
" lrst : L01," &
" ad_30 : L06," &
" ad_62 : M07 ," &
" vrbr_2 : L03," &
" vrbr_1 : N01," &
" ad_29 : L04 ," &
" ad_61 : M02 ," &
" ad_28 : L05," &
" pwrrst : P02," &
" ad_60 : M04," &
" ad_27 : N02," &
" ad_59 : M05 ," &
" ad_26 : N03 ," &
" ad_58 : R01," &
" int_3 : P06," &
" ad_25 : P04 ," &
" ad_57 : V03 ," &
" ad_24 : N06," &
" vrbr_0 : T02," &
" ad_56 : P05," &
" int_1 : T03," &
" ad_23 : N04," &
" pll_testsel : R02," &
" lclk : W04," &
" pll_testout : V02," &
" AVSS : T04," &
" AVDD : T06," &
" bidir_ctl : R04," &
" serr : N10," &
" perr : Y05," &
" ad_55 : V05," &
" ad_22 : T05," &
" devsel : V07," &
" ad_54 : R06," &
" ad_21 : W07," &
" par64 : W05," &
" ad_53 : T08," &
" trdy : V06," &
" ad_20 : P07," &
" ad_52 : N13," &
" ad_19 : T09," &
" ad_51 : Y04," &
" ad_18 : V09," &
" ack64 : Y07," &
" ad_50 : N14," &
" ad_17 : R07," &
" ad_49 : W08," &
" ad_16 : R08," &
" ad_48 : N07," &
" cbe_7 : Y08," &
" cbe_6 : V11," &
" cbe_3 : W09," &
" vrsysfail : P08," &
" cbe_2 : R09," &
" tmode_0 : W11," &
" cbe_5 : T12 ," &
" cbe_1 : Y09," &
" cbe_4 : Y11," &
" cbe_0 : P09," &
" ad_15 : N16," &
" irdy : V13," &
" gnt : Y12," &
" vrirq_5 : R11," &
" ad_47 : W12," &
" frame : P11," &
" idsel : Y13," &
" ad_14 : T11," &
" ad_46 : W13," &
" req64 : P12," &
" ad_13 : T14," &
" test_ram_we : Y15," &
" ad_45 : T15," &
" stop : V14," &
" ad_12 : W17," &
" ad_44 : R12," &
" rst : W16," &
" ad_11 : V15," &
" tmode_1 : V17," &
" ad_43 : R13," &
" viacki : W15," &
" ad_10 : V18," &
" ad_42 : Y16," &
" ad_9 : R14," &
" lock : R16," &
" ad_41 : N17," &
" ad_8 : P13," &
" ad_40 : T16," &
" ad_7 : P14," &
" tmode_2 : P15," &
" vme_reset : R18," &
" ad_39 : P16," &
" ad_6 : T17," &
" ad_38 : N19," &
" ad_5 : R19," &
" ad_37 : N18," &
" ad_4 : M15," &
" ad_36 : P18," &
" ad_3 : T18," &
" ad_35 : M16," &
" ad_2 : M18," &
" ad_34 : M13 ," &
" ad_1 : L16," &
" vrirq_7 : L17," &
" vrirq_6 : L18," &
" vxirq_7 : K14," &
" vracfail : L15," &
" vxbr_2 : L19," &
" ad_0 : K15," &
" ad_33 : K18," &
" vbgi_3 : L14," &
" vbgi_2 : J13," &
" vbgi_1 : J15," &
" vbgi_0 : K16," &
" vbgo_3 : K13," &
" vbgo_2 : K17," &
" vbgo_1 : J19," &
" vbgo_0 : J14," &
" ad_32 : H13," &
" vxirq_6 : J18," &
" vxirq_5 : J17," &
" vxirq_4 : G15," &
" vxirq_3 : J16," &
" vxirq_2 : H18," &
" vxirq_1 : H14," &
" req : G19," &
" viacko : H16," &
" vxbr_0 : G14," &
" vxbr_1 : H15," &
" int_0 : G10," &
" vrirq_4 : G12," &
" vrirq_3 : F18," &
" vrirq_2 : F16," &
" vrirq_1 : G18," &
" vxbr_3 : C16," &
" va_31 : G11," &
" va_30 : E19," &
" va_29 : G17," &
" va_28 : E18," &
" va_27 : F15," &
" va_26 : E17," &
" va_25 : B17," &
" va_24 : C17," &
" clk64 : D12," &
" vrsysrst : C13," &
" vxsysrst : E16," &
" va_23 : F13," &
" va_22 : E15," &
" va_21 : C15," &
" va_20 : D18," &
" va_19 : D19," &
" va_18 : C12," &
" va_17 : B15," &
" va_16 : B14," &
" va_15 : B16," &
" va_14 : D17," &
" va_13 : A15," &
" va_12 : B13," &
" va_11 : E14," &
" va_10 : F12," &
" va_9 : A13," &
" va_8 : D15," &
" va_7 : A16," &
" va_6 : C11," &
" vdtack : B12," &
" vslave_dir : F11," &
" va_5 : D14," &
" va_4 : D11," &
" va_3 : B11," &
" va_2 : D13," &
" va_1 : E13," &
" vas : A12," &
" vlword : D09," &
" va_dir : B10," &
" tdo : E12," &
" tdi : F09," &
" vas_dir : D08," &
" trst : B09," &
" voe : C09," &
" tck : A11," &
" vds_1 : A09," &
" vds_0 : E11," &
" vds_dir : F08," &
" vxberr : B08," &
" tms : C08," &
" vam_5 : A08," &
" vam_4 : D07," &
" vam_3 : B07," &
" vam_2 : E10," &
" vam_1 : A07," &
" vam_0 : D06," &
" vrberr : B06," &
" vam_dir : E09," &
" vd_dir : F07," &
" vd_31 : C07," &
" vd_30 : A05," &
" vd_29 : D05," &
" vwrite : B05," &
" vd_28 : C02," &
" vd_27 : E08," &
" vd_26 : B03," &
" vd_25 : C05," &
" vd_24 : C04," &
" viack : E07," &
" vd_23 : B04," &
" vd_22 : C03," &
" vd_21 : A04," &
" GND_dbga: (A14, A17, B02, B18, C18, F06, F10, G04, G16, H08," &
" H09, H10, H11, H12, J06, J07, J08, J09, J10, J11, J12, K08," &
" K09, K10, K11, K12, L07, L08, L09, L10, L11, L12, L13," &
" M06, M08, M09, M10, M11, M12, M17, N08, N11, N12, N15," &
" P01, P10, P19, R17, T10, V01, V08, V19, W02, W10, W18, Y03," &
" Y06)," &
" PWR_dbga: (A03, A06, A10, C01, C06, C10, C14, C19, D04, D10," &
" D16, F01, F03, F14, F17, F19, G07, G13, H01, H03, H17, H19," &
" K01, K19, M01, M03, M14, M19, N05, N09, P03, P17, R03," &
" R05, R10, R15, T01, T07, T13, T19, V04, V10, V12, V16," &
" W03, W06, W14, Y10, Y17 )";
-- This section specifies the TAP ports.
-- For the TAP TCK port, the parameters in the brackets are:
-- First Field : Maximum TCK frequency.
-- Second Field: Allowable states TCK may be stopped in.
attribute TAP_SCAN_IN of tdi : signal is true;
attribute TAP_SCAN_MODE of tms : signal is true;
attribute TAP_SCAN_OUT of tdo : signal is true;
attribute TAP_SCAN_CLOCK of tck : signal is (10.0e6, BOTH);
attribute TAP_SCAN_RESET of trst : signal is true;
-- attribute COMPLIANCE_ENABLE of tmode_2 : signal is true;
-- attribute COMPLIANCE_ENABLE of tmode_1 : signal is true;
-- attribute COMPLIANCE_ENABLE of tmode_0 : signal is true;
-- attribute COMPLIANCE_ENABLE of bidir_ctl : signal is true;
-- attribute COMPLIANCE_PATTERNS of CA91C142D : entity is
-- "(tmode_2, tmode_1, tmode_0, bidir_ctl) (0000)";
-- Specifies the number of bits in the instruction register.
attribute INSTRUCTION_LENGTH of CA91C142D : entity is 3;
-- Specifies the boundary-scan instructions implemented in the
-- design and their opcodes.
attribute INSTRUCTION_OPCODE of CA91C142D : entity is
"BYPASS (111)," &
"SAMPLE (010)," &
"EXTEST (000)," &
"IDCODE (100)";
-- Specifies the bit pattern that is loaded into the instruction
-- register when the TAP controller passes through the Capture-IR
-- state. The standard mandates that the two LSBs must be "01".
-- The remaining bits are design specific.
attribute INSTRUCTION_CAPTURE of CA91C142D : entity is "001";
-- Specifies the bit pattern that is loaded into the DEVICE_ID
-- register during the IDCODE instruction when the TAP controller
-- passes through the Capture-DR state.
attribute IDCODE_REGISTER of CA91C142D : entity is
"0001" & -- version
"0001111000100101" & -- part number
"00010110011" & -- manufacturer's identity
"1"; -- required by 1149.1
-- This section specifies the test data register placed between TDI
-- and TDO for each implemented instruction.
attribute REGISTER_ACCESS of CA91C142D : entity is
"BYPASS (BYPASS)," &
"BOUNDARY (SAMPLE, EXTEST)," &
"IDCODE (IDCODE)";
attribute BOUNDARY_CELLS of CA91C142D : entity is
"BC_1";
-- Specifies the length of the boundary scan register.
attribute BOUNDARY_LENGTH of CA91C142D : entity is 443;
-- The following list specifies the characteristics of each cell
-- in the boundary scan register from TDI to TDO.
-- The following is a description of the label fields:
-- num : Is the cell number.
-- cell : Is the cell type as defined by the standard.
-- port : Is the design port name. Control cells do not
-- have a port name.
-- function: Is the function of the cell as defined by the
-- standard. Is one of input, output2, output3,
-- bidir, control or controlr.
-- safe : Specifies the value that the BSR cell should be
-- loaded with for safe operation when the software
-- might otherwise choose a random value.
-- ccell : The control cell number. Specifies the control
-- cell that drives the output enable for this port.
-- disval : Specifies the value that is loaded into the
-- control cell to disable the output enable for
-- the corresponding port.
-- rslt : Resulting state. Shows the state of the driver
-- when it is disabled.
attribute BOUNDARY_REGISTER of CA91C142D : entity is
--
-- num cell port function safe [ccell disval rslt]
--
"442 (BC_1, vas_dir, output3, X, 146, 0, Z)," &
"441 (BC_1, voe, output3, X, 146, 0, Z)," &
"440 (BC_1, *, controlr, 0)," &
"439 (BC_1, vds_1, input, X)," &
"438 (BC_1, vds_1, output3, X, 440, 0, Z)," &
"437 (BC_1, vds_0, input, X)," &
"436 (BC_1, vds_0, output3, X, 440, 0, Z)," &
"435 (BC_1, vds_dir, output3, X, 146, 0, Z)," &
"434 (BC_1, vxberr, output3, X, 146, 0, Z)," &
"433 (BC_1, vam_5, input, X)," &
"432 (BC_1, vam_5, output3, X, 425, 0, Z)," &
"431 (BC_1, vam_4, input, X)," &
"430 (BC_1, vam_4, output3, X, 425, 0, Z)," &
"429 (BC_1, vam_3, input, X)," &
"428 (BC_1, vam_3, output3, X, 425, 0, Z)," &
"427 (BC_1, vam_2, input, X)," &
"426 (BC_1, vam_2, output3, X, 425, 0, Z)," &
"425 (BC_1, *, controlr, 0)," &
"424 (BC_1, vam_1, input, X)," &
"423 (BC_1, vam_1, output3, X, 425, 0, Z)," &
"422 (BC_1, vam_0, input, X)," &
"421 (BC_1, vam_0, output3, X, 425, 0, Z)," &
"420 (BC_1, vrberr, input, X)," &
"419 (BC_1, vam_dir, output3, X, 146, 0, Z)," &
"418 (BC_1, vd_dir, output3, X, 146, 0, Z)," &
"417 (BC_1, vd_31, input, X)," &
"416 (BC_1, vd_31, output3, X, 379, 0, Z)," &
"415 (BC_1, vd_30, input, X)," &
"414 (BC_1, vd_30, output3, X, 379, 0, Z)," &
"413 (BC_1, vd_29, input, X)," &
"412 (BC_1, vd_29, output3, X, 379, 0, Z)," &
"411 (BC_1, vwrite, input, X)," &
"410 (BC_1, vwrite, output3, X, 409, 0, Z)," &
"409 (BC_1, *, controlr, 0)," &
"408 (BC_1, vd_28, input, X)," &
"407 (BC_1, vd_28, output3, X, 379, 0, Z)," &
"406 (BC_1, vd_27, input, X)," &
"405 (BC_1, vd_27, output3, X, 379, 0, Z)," &
"404 (BC_1, vd_26, input, X)," &
"403 (BC_1, vd_26, output3, X, 379, 0, Z)," &
"402 (BC_1, vd_25, input, X)," &
"401 (BC_1, vd_25, output3, X, 379, 0, Z)," &
"400 (BC_1, vd_24, input, X)," &
"399 (BC_1, vd_24, output3, X, 379, 0, Z)," &
"398 (BC_1, *, controlr, 0)," &
"397 (BC_1, viack, input, X)," &
"396 (BC_1, viack, output3, X, 398, 0, Z)," &
"395 (BC_1, vd_23, input, X)," &
"394 (BC_1, vd_23, output3, X, 379, 0, Z)," &
"393 (BC_1, vd_22, input, X)," &
"392 (BC_1, vd_22, output3, X, 379, 0, Z)," &
"391 (BC_1, vd_21, input, X)," &
"390 (BC_1, vd_21, output3, X, 379, 0, Z)," &
"389 (BC_1, vd_20, input, X)," &
"388 (BC_1, vd_20, output3, X, 379, 0, Z)," &
"387 (BC_1, vd_19, input, X)," &
"386 (BC_1, vd_19, output3, X, 379, 0, Z)," &
"385 (BC_1, vd_18, input, X)," &
"384 (BC_1, vd_18, output3, X, 379, 0, Z)," &
"383 (BC_1, vd_17, input, X)," &
"382 (BC_1, vd_17, output3, X, 379, 0, Z)," &
"381 (BC_1, vd_16, input, X)," &
"380 (BC_1, vd_16, output3, X, 379, 0, Z)," &
"379 (BC_1, *, controlr, 0)," &
"378 (BC_1, vd_15, input, X)," &
"377 (BC_1, vd_15, output3, X, 379, 0, Z)," &
"376 (BC_1, vd_14, input, X)," &
"375 (BC_1, vd_14, output3, X, 379, 0, Z)," &
"374 (BC_1, vd_13, input, X)," &
"373 (BC_1, vd_13, output3, X, 379, 0, Z)," &
"372 (BC_1, vd_12, input, X)," &
"371 (BC_1, vd_12, output3, X, 379, 0, Z)," &
"370 (BC_1, vd_11, input, X)," &
"369 (BC_1, vd_11, output3, X, 379, 0, Z)," &
"368 (BC_1, vd_10, input, X)," &
"367 (BC_1, vd_10, output3, X, 379, 0, Z)," &
"366 (BC_1, *, controlr, 0)," &
"365 (BC_1, vd_9, input, X)," &
"364 (BC_1, vd_9, output3, X, 379, 0, Z)," &
"363 (BC_1, vd_8, input, X)," &
"362 (BC_1, vd_8, output3, X, 379, 0, Z)," &
"361 (BC_1, vd_7, input, X)," &
"360 (BC_1, vd_7, output3, X, 379, 0, Z)," &
"359 (BC_1, vd_6, input, X)," &
"358 (BC_1, vd_6, output3, X, 379, 0, Z)," &
"357 (BC_1, vd_5, input, X)," &
"356 (BC_1, vd_5, output3, X, 379, 0, Z)," &
"355 (BC_1, vd_4, input, X)," &
"354 (BC_1, vd_4, output3, X, 379, 0, Z)," &
"353 (BC_1, vd_3, input, X)," &
"352 (BC_1, vd_3, output3, X, 379, 0, Z)," &
"351 (BC_1, vd_2, input, X)," &
"350 (BC_1, vd_2, output3, X, 379, 0, Z)," &
"349 (BC_1, vd_1, input, X)," &
"348 (BC_1, vd_1, output3, X, 379, 0, Z)," &
"347 (BC_1, vd_0, input, X)," &
"346 (BC_1, vd_0, output3, X, 379, 0, Z)," &
"345 (BC_1, *, controlr, 0)," &
"344 (BC_1, vrbr_3, input, X)," &
"343 (BC_1, int_5, input, X)," &
"342 (BC_1, int_5, output3, X, 302, 0, Z)," &
"341 (BC_1, int_4, input, X)," &
"340 (BC_1, int_4, output3, X, 294, 0, Z)," &
"339 (BC_1, int_2, input, X)," &
"338 (BC_1, int_2, output3, X, 366, 0, Z)," &
"337 (BC_1, vrbbsy, input, X)," &
"336 (BC_1, int_7, input, X)," &
"335 (BC_1, int_7, output3, X, 345, 0, Z)," &
"334 (BC_1, int_6, input, X)," &
"333 (BC_1, int_6, output3, X, 313, 0, Z)," &
"332 (BC_1, vscon_dir, output3, X, 146, 0, Z)," &
"331 (BC_1, vxsysfail, output2, X)," &
"330 (BC_1, vsysclk, input, X)," &
"329 (BC_1, vsysclk, output3, X, 327, 0, Z)," &
"328 (BC_1, vbclr, output3, X, 146, 0, Z)," &
"327 (BC_1, *, controlr, 0)," &
"326 (BC_1, ad_31, input, X)," &
"325 (BC_1, ad_31, output3, X, 310, 0, Z)," &
"324 (BC_1, ad_63, input, X)," &
"323 (BC_1, ad_63, output3, X, 307, 0, Z)," &
"322 (BC_1, vxbbsy, output3, X, 146, 0, Z)," &
"321 (BC_1, par, input, X)," &
"320 (BC_1, par, output3, X, 319, 0, Z)," &
"319 (BC_1, *, controlr, 0)," &
"318 (BC_1, lrst, output3, X, 146, 0, Z)," &
"317 (BC_1, ad_30, input, X)," &
"316 (BC_1, ad_30, output3, X, 310, 0, Z)," &
"315 (BC_1, ad_62, input, X)," &
"314 (BC_1, ad_62, output3, X, 307, 0, Z)," &
"313 (BC_1, *, controlr, 0)," &
"312 (BC_1, vrbr_2, input, X)," &
"311 (BC_1, vrbr_1, input, X)," &
"310 (BC_1, *, controlr, 0)," &
"309 (BC_1, ad_29, input, X)," &
"308 (BC_1, ad_29, output3, X, 310, 0, Z)," &
"307 (BC_1, *, controlr, 0)," &
"306 (BC_1, ad_61, input, X)," &
"305 (BC_1, ad_61, output3, X, 307, 0, Z)," &
"304 (BC_1, ad_28, input, X)," &
"303 (BC_1, ad_28, output3, X, 310, 0, Z)," &
"302 (BC_1, *, controlr, 0)," &
"301 (BC_1, pwrrst, input, X)," &
"300 (BC_1, ad_60, input, X)," &
"299 (BC_1, ad_60, output3, X, 307, 0, Z)," &
"298 (BC_1, ad_27, input, X)," &
"297 (BC_1, ad_27, output3, X, 287, 0, Z)," &
"296 (BC_1, ad_59, input, X)," &
"295 (BC_1, ad_59, output3, X, 283, 0, Z)," &
"294 (BC_1, *, controlr, 0)," &
"293 (BC_1, ad_26, input, X)," &
"292 (BC_1, ad_26, output3, X, 287, 0, Z)," &
"291 (BC_1, ad_58, input, X)," &
"290 (BC_1, ad_58, output3, X, 283, 0, Z)," &
"289 (BC_1, int_3, input, X)," &
"288 (BC_1, int_3, output3, X, 284, 0, Z)," &
"287 (BC_1, *, controlr, 0)," &
"286 (BC_1, ad_25, input, X)," &
"285 (BC_1, ad_25, output3, X, 287, 0, Z)," &
"284 (BC_1, *, controlr, 0)," &
"283 (BC_1, *, controlr, 0)," &
"282 (BC_1, ad_57, input, X)," &
"281 (BC_1, ad_57, output3, X, 283, 0, Z)," &
"280 (BC_1, ad_24, input, X)," &
"279 (BC_1, ad_24, output3, X, 287, 0, Z)," &
"278 (BC_1, vrbr_0, input, X)," &
"277 (BC_1, ad_56, input, X)," &
"276 (BC_1, ad_56, output3, X, 283, 0, Z)," &
"275 (BC_1, int_1, input, X)," &
"274 (BC_1, int_1, output3, X, 273, 0, Z)," &
"273 (BC_1, *, controlr, 0)," &
"272 (BC_1, ad_23, input, X)," &
"271 (BC_1, ad_23, output3, X, 256, 0, Z)," &
"270 (BC_1, serr, output3, X, 269, 0, Z)," &
"269 (BC_1, *, controlr, 0)," &
"268 (BC_1, perr, input, X)," &
"267 (BC_1, perr, output3, X, 266, 0, Z)," &
"266 (BC_1, *, controlr, 0)," &
"265 (BC_1, ad_55, input, X)," &
"264 (BC_1, ad_55, output3, X, 250, 0, Z)," &
"263 (BC_1, ad_22, input, X)," &
"262 (BC_1, ad_22, output3, X, 256, 0, Z)," &
"261 (BC_1, *, controlr, 0)," &
"260 (BC_1, devsel, input, X)," &
"259 (BC_1, devsel, output3, X, 261, 0, Z)," &
"258 (BC_1, ad_54, input, X)," &
"257 (BC_1, ad_54, output3, X, 250, 0, Z)," &
"256 (BC_1, *, controlr, 0)," &
"255 (BC_1, ad_21, input, X)," &
"254 (BC_1, ad_21, output3, X, 256, 0, Z)," &
"253 (BC_1, *, controlr, 0)," &
"252 (BC_1, par64, input, X)," &
"251 (BC_1, par64, output3, X, 253, 0, Z)," &
"250 (BC_1, *, controlr, 0)," &
"249 (BC_1, ad_53, input, X)," &
"248 (BC_1, ad_53, output3, X, 250, 0, Z)," &
"247 (BC_1, *, controlr, 0)," &
"246 (BC_1, trdy, input, X)," &
"245 (BC_1, trdy, output3, X, 247, 0, Z)," &
"244 (BC_1, ad_20, input, X)," &
"243 (BC_1, ad_20, output3, X, 256, 0, Z)," &
"242 (BC_1, ad_52, input, X)," &
"241 (BC_1, ad_52, output3, X, 250, 0, Z)," &
"240 (BC_1, ad_19, input, X)," &
"239 (BC_1, ad_19, output3, X, 230, 0, Z)," &
"238 (BC_1, ad_51, input, X)," &
"237 (BC_1, ad_51, output3, X, 226, 0, Z)," &
"236 (BC_1, ad_18, input, X)," &
"235 (BC_1, ad_18, output3, X, 230, 0, Z)," &
"234 (BC_1, ack64, input, X)," &
"233 (BC_1, ack64, output3, X, 227, 0, Z)," &
"232 (BC_1, ad_50, input, X)," &
"231 (BC_1, ad_50, output3, X, 226, 0, Z)," &
"230 (BC_1, *, controlr, 0)," &
"229 (BC_1, ad_17, input, X)," &
"228 (BC_1, ad_17, output3, X, 230, 0, Z)," &
"227 (BC_1, *, controlr, 0)," &
"226 (BC_1, *, controlr, 0)," &
"225 (BC_1, ad_49, input, X)," &
"224 (BC_1, ad_49, output3, X, 226, 0, Z)," &
"223 (BC_1, ad_16, input, X)," &
"222 (BC_1, ad_16, output3, X, 230, 0, Z)," &
"221 (BC_1, ad_48, input, X)," &
"220 (BC_1, ad_48, output3, X, 226, 0, Z)," &
"219 (BC_1, *, controlr, 0)," &
"218 (BC_1, cbe_7, input, X)," &
"217 (BC_1, cbe_7, output3, X, 219, 0, Z)," &
"216 (BC_1, cbe_6, input, X)," &
"215 (BC_1, cbe_6, output3, X, 219, 0, Z)," &
"214 (BC_1, cbe_3, input, X)," &
"213 (BC_1, cbe_3, output3, X, 205, 0, Z)," &
"212 (BC_1, vrsysfail, input, X)," &
"211 (BC_1, cbe_2, input, X)," &
"210 (BC_1, cbe_2, output3, X, 205, 0, Z)," &
"209 (BC_1, cbe_5, input, X)," &
"208 (BC_1, cbe_5, output3, X, 219, 0, Z)," &
"207 (BC_1, cbe_1, input, X)," &
"206 (BC_1, cbe_1, output3, X, 205, 0, Z)," &
"205 (BC_1, *, controlr, 0)," &
"204 (BC_1, cbe_4, input, X)," &
"203 (BC_1, cbe_4, output3, X, 219, 0, Z)," &
"202 (BC_1, cbe_0, input, X)," &
"201 (BC_1, cbe_0, output3, X, 205, 0, Z)," &
"200 (BC_1, ad_15, input, X)," &
"199 (BC_1, ad_15, output3, X, 180, 0, Z)," &
"198 (BC_1, *, controlr, 0)," &
"197 (BC_1, irdy, input, X)," &
"196 (BC_1, irdy, output3, X, 198, 0, Z)," &
"195 (BC_1, gnt, input, X)," &
"194 (BC_1, vrirq_5, input, X)," &
"193 (BC_1, ad_47, input, X)," &
"192 (BC_1, ad_47, output3, X, 177, 0, Z)," &
"191 (BC_1, frame, input, X)," &
"190 (BC_1, frame, output3, X, 189, 0, Z)," &
"189 (BC_1, *, controlr, 0)," &
"188 (BC_1, idsel, input, X)," &
"187 (BC_1, ad_14, input, X)," &
"186 (BC_1, ad_14, output3, X, 180, 0, Z)," &
"185 (BC_1, ad_46, input, X)," &
"184 (BC_1, ad_46, output3, X, 177, 0, Z)," &
"183 (BC_1, req64, input, X)," &
"182 (BC_1, req64, output3, X, 181, 0, Z)," &
"181 (BC_1, *, controlr, 0)," &
"180 (BC_1, *, controlr, 0)," &
"179 (BC_1, ad_13, input, X)," &
"178 (BC_1, ad_13, output3, X, 180, 0, Z)," &
"177 (BC_1, *, controlr, 0)," &
"176 (BC_1, ad_45, input, X)," &
"175 (BC_1, ad_45, output3, X, 177, 0, Z)," &
"174 (BC_1, stop, input, X)," &
"173 (BC_1, stop, output3, X, 172, 0, Z)," &
"172 (BC_1, *, controlr, 0)," &
"171 (BC_1, ad_12, input, X)," &
"170 (BC_1, ad_12, output3, X, 180, 0, Z)," &
"169 (BC_1, ad_44, input, X)," &
"168 (BC_1, ad_44, output3, X, 177, 0, Z)," &
"167 (BC_1, rst, input, X)," &
"166 (BC_1, ad_11, input, X)," &
"165 (BC_1, ad_11, output3, X, 157, 0, Z)," &
"164 (BC_1, ad_43, input, X)," &
"163 (BC_1, ad_43, output3, X, 151, 0, Z)," &
"162 (BC_1, viacki, input, X)," &
"161 (BC_1, ad_10, input, X)," &
"160 (BC_1, ad_10, output3, X, 157, 0, Z)," &
"159 (BC_1, ad_42, input, X)," &
"158 (BC_1, ad_42, output3, X, 151, 0, Z)," &
"157 (BC_1, *, controlr, 0)," &
"156 (BC_1, ad_9, input, X)," &
"155 (BC_1, ad_9, output3, X, 157, 0, Z)," &
"154 (BC_1, lock, input, X)," &
"153 (BC_1, lock, output3, X, 152, 0, Z)," &
"152 (BC_1, *, controlr, 0)," &
"151 (BC_1, *, controlr, 0)," &
"150 (BC_1, ad_41, input, X)," &
"149 (BC_1, ad_41, output3, X, 151, 0, Z)," &
"148 (BC_1, ad_8, input, X)," &
"147 (BC_1, ad_8, output3, X, 157, 0, Z)," &
"146 (BC_1, *, controlr, 0)," &
"145 (BC_1, ad_40, input, X)," &
"144 (BC_1, ad_40, output3, X, 151, 0, Z)," &
"143 (BC_1, ad_7, input, X)," &
"142 (BC_1, ad_7, output3, X, 134, 0, Z)," &
"141 (BC_1, vme_reset, input, X)," &
"140 (BC_1, ad_39, input, X)," &
"139 (BC_1, ad_39, output3, X, 131, 0, Z)," &
"138 (BC_1, ad_6, input, X)," &
"137 (BC_1, ad_6, output3, X, 134, 0, Z)," &
"136 (BC_1, ad_38, input, X)," &
"135 (BC_1, ad_38, output3, X, 131, 0, Z)," &
"134 (BC_1, *, controlr, 0)," &
"133 (BC_1, ad_5, input, X)," &
"132 (BC_1, ad_5, output3, X, 134, 0, Z)," &
"131 (BC_1, *, controlr, 0)," &
"130 (BC_1, ad_37, input, X)," &
"129 (BC_1, ad_37, output3, X, 131, 0, Z)," &
"128 (BC_1, ad_4, input, X)," &
"127 (BC_1, ad_4, output3, X, 134, 0, Z)," &
"126 (BC_1, ad_36, input, X)," &
"125 (BC_1, ad_36, output3, X, 131, 0, Z)," &
"124 (BC_1, ad_3, input, X)," &
"123 (BC_1, ad_3, output3, X, 116, 0, Z)," &
"122 (BC_1, ad_35, input, X)," &
"121 (BC_1, ad_35, output3, X, 106, 0, Z)," &
"120 (BC_1, ad_2, input, X)," &
"119 (BC_1, ad_2, output3, X, 116, 0, Z)," &
"118 (BC_1, ad_34, input, X)," &
"117 (BC_1, ad_34, output3, X, 106, 0, Z)," &
"116 (BC_1, *, controlr, 0)," &
"115 (BC_1, ad_1, input, X)," &
"114 (BC_1, ad_1, output3, X, 116, 0, Z)," &
"113 (BC_1, vrirq_7, input, X)," &
"112 (BC_1, vrirq_6, input, X)," &
"111 (BC_1, vxirq_7, output3, X, 146, 0, Z)," &
"110 (BC_1, vracfail, input, X)," &
"109 (BC_1, vxbr_2, output3, X, 146, 0, Z)," &
"108 (BC_1, ad_0, input, X)," &
"107 (BC_1, ad_0, output3, X, 116, 0, Z)," &
"106 (BC_1, *, controlr, 0)," &
"105 (BC_1, ad_33, input, X)," &
"104 (BC_1, ad_33, output3, X, 106, 0, Z)," &
"103 (BC_1, vbgi_3, input, X)," &
"102 (BC_1, vbgi_2, input, X)," &
"101 (BC_1, vbgi_1, input, X)," &
"100 (BC_1, vbgi_0, input, X)," &
"99 (BC_1, vbgo_3, output3, X, 146, 0, Z)," &
"98 (BC_1, vbgo_2, output3, X, 146, 0, Z)," &
"97 (BC_1, vbgo_1, output3, X, 146, 0, Z)," &
"96 (BC_1, vbgo_0, output3, X, 146, 0, Z)," &
"95 (BC_1, ad_32, input, X)," &
"94 (BC_1, ad_32, output3, X, 106, 0, Z)," &
"93 (BC_1, vxirq_6, output3, X, 146, 0, Z)," &
"92 (BC_1, vxirq_5, output3, X, 146, 0, Z)," &
"91 (BC_1, vxirq_4, output3, X, 146, 0, Z)," &
"90 (BC_1, vxirq_3, output3, X, 146, 0, Z)," &
"89 (BC_1, vxirq_2, output3, X, 146, 0, Z)," &
"88 (BC_1, vxirq_1, output3, X, 146, 0, Z)," &
"87 (BC_1, req, output3, X, 146, 0, Z)," &
"86 (BC_1, viacko, output3, X, 146, 0, Z)," &
"85 (BC_1, vxbr_0, output3, X, 146, 0, Z)," &
"84 (BC_1, vxbr_1, output3, X, 146, 0, Z)," &
"83 (BC_1, int_0, input, X)," &
"82 (BC_1, int_0, output3, X, 81, 0, Z)," &
"81 (BC_1, *, controlr, 0)," &
"80 (BC_1, vrirq_4, input, X)," &
"79 (BC_1, vrirq_3, input, X)," &
"78 (BC_1, vrirq_2, input, X)," &
"77 (BC_1, vrirq_1, input, X)," &
"76 (BC_1, vxbr_3, output3, X, 146, 0, Z)," &
"75 (BC_1, va_31, input, X)," &
"74 (BC_1, va_31, output3, X, 40, 0, Z)," &
"73 (BC_1, va_30, input, X)," &
"72 (BC_1, va_30, output3, X, 40, 0, Z)," &
"71 (BC_1, va_29, input, X)," &
"70 (BC_1, va_29, output3, X, 40, 0, Z)," &
"69 (BC_1, va_28, input, X)," &
"68 (BC_1, va_28, output3, X, 40, 0, Z)," &
"67 (BC_1, va_27, input, X)," &
"66 (BC_1, va_27, output3, X, 40, 0, Z)," &
"65 (BC_1, va_26, input, X)," &
"64 (BC_1, va_26, output3, X, 40, 0, Z)," &
"63 (BC_1, va_25, input, X)," &
"62 (BC_1, va_25, output3, X, 40, 0, Z)," &
"61 (BC_1, va_24, input, X)," &
"60 (BC_1, va_24, output3, X, 40, 0, Z)," &
"59 (BC_1, clk64, input, X)," &
"58 (BC_1, vrsysrst, input, X)," &
"57 (BC_1, vxsysrst, output3, X, 146, 0, Z)," &
"56 (BC_1, va_23, input, X)," &
"55 (BC_1, va_23, output3, X, 40, 0, Z)," &
"54 (BC_1, va_22, input, X)," &
"53 (BC_1, va_22, output3, X, 40, 0, Z)," &
"52 (BC_1, va_21, input, X)," &
"51 (BC_1, va_21, output3, X, 40, 0, Z)," &
"50 (BC_1, va_20, input, X)," &
"49 (BC_1, va_20, output3, X, 40, 0, Z)," &
"48 (BC_1, va_19, input, X)," &
"47 (BC_1, va_19, output3, X, 40, 0, Z)," &
"46 (BC_1, va_18, input, X)," &
"45 (BC_1, va_18, output3, X, 40, 0, Z)," &
"44 (BC_1, va_17, input, X)," &
"43 (BC_1, va_17, output3, X, 40, 0, Z)," &
"42 (BC_1, va_16, input, X)," &
"41 (BC_1, va_16, output3, X, 40, 0, Z)," &
"40 (BC_1, *, controlr, 0)," &
"39 (BC_1, va_15, input, X)," &
"38 (BC_1, va_15, output3, X, 40, 0, Z)," &
"37 (BC_1, va_14, input, X)," &
"36 (BC_1, va_14, output3, X, 40, 0, Z)," &
"35 (BC_1, va_13, input, X)," &
"34 (BC_1, va_13, output3, X, 40, 0, Z)," &
"33 (BC_1, va_12, input, X)," &
"32 (BC_1, va_12, output3, X, 40, 0, Z)," &
"31 (BC_1, va_11, input, X)," &
"30 (BC_1, va_11, output3, X, 40, 0, Z)," &
"29 (BC_1, va_10, input, X)," &
"28 (BC_1, va_10, output3, X, 40, 0, Z)," &
"27 (BC_1, va_9, input, X)," &
"26 (BC_1, va_9, output3, X, 40, 0, Z)," &
"25 (BC_1, va_8, input, X)," &
"24 (BC_1, va_8, output3, X, 40, 0, Z)," &
"23 (BC_1, va_7, input, X)," &
"22 (BC_1, va_7, output3, X, 40, 0, Z)," &
"21 (BC_1, va_6, input, X)," &
"20 (BC_1, va_6, output3, X, 40, 0, Z)," &
"19 (BC_1, *, controlr, 0)," &
"18 (BC_1, vdtack, input, X)," &
"17 (BC_1, vdtack, output3, X, 19, 0, Z)," &
"16 (BC_1, vslave_dir, output3, X, 146, 0, Z)," &
"15 (BC_1, va_5, input, X)," &
"14 (BC_1, va_5, output3, X, 40, 0, Z)," &
"13 (BC_1, va_4, input, X)," &
"12 (BC_1, va_4, output3, X, 40, 0, Z)," &
"11 (BC_1, va_3, input, X)," &
"10 (BC_1, va_3, output3, X, 40, 0, Z)," &
"9 (BC_1, va_2, input, X)," &
"8 (BC_1, va_2, output3, X, 40, 0, Z)," &
"7 (BC_1, va_1, input, X)," &
"6 (BC_1, va_1, output3, X, 40, 0, Z)," &
"5 (BC_1, *, controlr, 0)," &
"4 (BC_1, vas, input, X)," &
"3 (BC_1, vas, output3, X, 5, 0, Z)," &
"2 (BC_1, vlword, input, X)," &
"1 (BC_1, vlword, output3, X, 40, 0, Z)," &
"0 (BC_1, va_dir, output3, X, 146, 0, Z)";
end CA91C142D;