BSDL Files Library for JTAG

The only free public library that contains thousands of BSDL (Boundary Scan Description Language) models to use with BScan/JTAG tools

BSDL model: idt82P33724NLG

-- *****************************************************************************

--   BSDL file for design idt82P33724NLG

--   Created by Synopsys Version G-2012.06-SP5 (Jan 18, 2013)

--   Designer: 
--   Company:  

--   Date: Fri Oct 10 16:55:13 2014

-- *****************************************************************************


 entity idt82P33724NLG is
   
-- This section identifies the default device package selected.
   
   generic (PHYSICAL_PIN_MAP: string:= "PKG_82P33724BAG");
   
-- This section declares all the ports in the design.
   
   port ( 
          CLKE_I2C_AD1        : in       bit;
          CS_I2C_AD0          : in       bit;
          IC                  : in       bit;
          IN1_NEG             : in       bit;
          IN1_POS             : in       bit;
          IN2_NEG             : in       bit;
          IN2_POS             : in       bit;
          IN3_NEG             : in       bit;
          IN3_POS             : in       bit;
          IN4_NEG             : in       bit;
          IN4_POS             : in       bit;
          IN5                 : in       bit;
          IN6                 : in       bit;
          OSCI                : in       bit;
          RSTB                : in       bit;
          SCLK_I2C_SCL        : in       bit;
          SDI_I2C_AD2_UART_RX : in       bit;
          SONET_SDH_LOS3      : in       bit;
          TCK                 : in       bit;
          TDI                 : in       bit;
          TMS                 : in       bit;
          TRSTB               : in       bit;
          XO_FREQ0_LOS0       : in       bit;
          XO_FREQ1_LOS1       : in       bit;
          XO_FREQ2_LOS2       : in       bit;
          MPU_MODE0_I2C_SDA   : inout    bit;
          MPU_MODE1_I2C_SCL   : inout    bit;
          SDO_I2C_SDA_UART_TX : inout    bit;
          INT_REQ             : out      bit;
          OUT1                : out      bit;
          OUT10               : out      bit;
          OUT2                : out      bit;
          OUT3_NEG            : out      bit;
          OUT3_POS            : out      bit;
          OUT4_NEG            : out      bit;
          OUT4_POS            : out      bit;
          OUT5_NEG            : out      bit;
          OUT5_POS            : out      bit;
          OUT6_NEG            : out      bit;
          OUT6_POS            : out      bit;
          OUT7                : out      bit;
          OUT8                : out      bit;
          OUT9                : out      bit;
          TDO                 : out      bit;
          DPLL1_LOCK          : buffer   bit;
          DPLL2_LOCK          : buffer   bit;
          DPLL3_LOCK          : buffer   bit;
          FRSYNC_8K_1PPS      : buffer   bit;
          MFRSYNC_2K_1PPS     : buffer   bit;
          VC1                 : linkage  bit;
          VC2                 : linkage  bit;
          VDDAO_P20           : linkage  bit;
          VDDAO_P24           : linkage  bit;
          VDDAO_P69           : linkage  bit;
          VDDAO_P72           : linkage  bit;
          VDDA_P10            : linkage  bit;
          VDDA_P11            : linkage  bit;
          VDDA_P12            : linkage  bit;
          VDDA_P2             : linkage  bit;
          VDDA_P3             : linkage  bit;
          VDDA_P4             : linkage  bit;
          VDDA_P5             : linkage  bit;
          VDDDO_P27           : linkage  bit;
          VDDDO_P29           : linkage  bit;
          VDDDO_P64           : linkage  bit;
          VDDDO_P66           : linkage  bit;
          VDDD_1_8_P42        : linkage  bit;
          VDDD_1_8_P53        : linkage  bit;
          VDDD_P40            : linkage  bit;
          VDDD_P62            : linkage  bit;
          VSS                 : linkage  bit;
          VSSAO_P19           : linkage  bit;
          VSSAO_P23           : linkage  bit
   );
   
   use STD_1149_1_2001.all;
   
   attribute COMPONENT_CONFORMANCE of idt82P33724NLG: entity is 
     "STD_1149_1_2001";
   
   attribute PIN_MAP of idt82P33724NLG: entity is PHYSICAL_PIN_MAP;
   
-- This section specifies the pin map for each port. This information is 
-- extracted from the port-to-pin map file that was read in using the 
-- "read_pin_map" command.
   
     constant PKG_82P33724BAG: PIN_MAP_STRING := 
        "CLKE_I2C_AD1        : P48," &
        "CS_I2C_AD0          : P49," &
        "IC                  : P58," &
        "IN1_NEG             : P32," &
        "IN1_POS             : P31," &
        "IN2_NEG             : P34," &
        "IN2_POS             : P33," &
        "IN3_NEG             : P36," &
        "IN3_POS             : P35," &
        "IN4_NEG             : P39," &
        "IN4_POS             : P38," &
        "IN5                 : P37," &
        "IN6                 : P41," &
        "OSCI                : P6," &
        "RSTB                : P52," &
        "SCLK_I2C_SCL        : P50," &
        "SDI_I2C_AD2_UART_RX : P47," &
        "SONET_SDH_LOS3      : P59," &
        "TCK                 : P16," &
        "TDI                 : P17," &
        "TMS                 : P14," &
        "TRSTB               : P15," &
        "XO_FREQ0_LOS0       : P7," &
        "XO_FREQ1_LOS1       : P8," &
        "XO_FREQ2_LOS2       : P9," &
        "MPU_MODE0_I2C_SDA   : P45," &
        "MPU_MODE1_I2C_SCL   : P46," &
        "SDO_I2C_SDA_UART_TX : P51," &
        "INT_REQ             : P57," &
        "OUT1                : P30," &
        "OUT10               : P60," &
        "OUT2                : P28," &
        "OUT3_NEG            : P26," &
        "OUT3_POS            : P25," &
        "OUT4_NEG            : P22," &
        "OUT4_POS            : P21," &
        "OUT5_NEG            : P70," &
        "OUT5_POS            : P71," &
        "OUT6_NEG            : P67," &
        "OUT6_POS            : P68," &
        "OUT7                : P65," &
        "OUT8                : P63," &
        "OUT9                : P61," &
        "TDO                 : P18," &
        "DPLL1_LOCK          : P55," &
        "DPLL2_LOCK          : P56," &
        "DPLL3_LOCK          : P54," &
        "FRSYNC_8K_1PPS      : P43," &
        "MFRSYNC_2K_1PPS     : P44," &
        "VC1                 : P13," &
        "VC2                 : P1," &
        "VDDAO_P20           : P20," &
        "VDDAO_P24           : P24," &
        "VDDAO_P69           : P69," &
        "VDDAO_P72           : P72," &
        "VDDA_P10            : P10," &
        "VDDA_P11            : P11," &
        "VDDA_P12            : P12," &
        "VDDA_P2             : P2," &
        "VDDA_P3             : P3," &
        "VDDA_P4             : P4," &
        "VDDA_P5             : P5," &
        "VDDDO_P27           : P27," &
        "VDDDO_P29           : P29," &
        "VDDDO_P64           : P64," &
        "VDDDO_P66           : P66," &
        "VDDD_1_8_P42        : P42," &
        "VDDD_1_8_P53        : P53," &
        "VDDD_P40            : P40," &
        "VDDD_P62            : P62," &
        "VSS                 : P73," &
        "VSSAO_P19           : P19," &
        "VSSAO_P23           : P23";
   
-- This section specifies the TAP ports. For the TAP TCK port, the parameters in 
-- the brackets are:
--        First Field : Maximum  TCK frequency.
--        Second Field: Allowable states TCK may be stopped in.
   
   attribute TAP_SCAN_CLOCK of TCK  : signal is (10.0e6, BOTH);
   attribute TAP_SCAN_IN    of TDI  : signal is true;
   attribute TAP_SCAN_MODE  of TMS  : signal is true;
   attribute TAP_SCAN_OUT   of TDO  : signal is true;
   attribute TAP_SCAN_RESET of TRSTB: signal is true;
   
-- Specifies the number of bits in the instruction register.
   
   attribute INSTRUCTION_LENGTH of idt82P33724NLG: entity is 3;
   
-- Specifies the boundary-scan instructions implemented in the design and their 
-- opcodes.
   
   attribute INSTRUCTION_OPCODE of idt82P33724NLG: entity is 
     "BYPASS  (111)," &
     "EXTEST  (000)," &
     "SAMPLE  (010)," &
     "PRELOAD (010)," &
     "IDCODE  (001)";
   
-- Specifies the bit pattern that is loaded into the instruction register when 
-- the TAP controller passes through the Capture-IR state. The standard mandates 
-- that the two LSBs must be "01". The remaining bits are design specific.
   
   attribute INSTRUCTION_CAPTURE of idt82P33724NLG: entity is "001";
   
-- Specifies the bit pattern that is loaded into the DEVICE_ID register during 
-- the IDCODE instruction when the TAP controller passes through the Capture-DR 
-- state.
   
   attribute IDCODE_REGISTER of idt82P33724NLG: entity is 
     "0000" &                  
 -- 4-bit version number
     "0000011000010101" &      
 -- 16-bit part number
     "00010110011" &           
 -- 11-bit identity of the manufacturer
     "1";                      
 -- Required by IEEE Std 1149.1
   
-- This section specifies the test data register placed between TDI and TDO for 
-- each implemented instruction.
   
   attribute REGISTER_ACCESS of idt82P33724NLG: entity is 
        "BYPASS    (BYPASS)," &
        "BOUNDARY  (EXTEST, SAMPLE, PRELOAD)," &
        "DEVICE_ID (IDCODE)";
   
-- Specifies the length of the boundary scan register.
   
   attribute BOUNDARY_LENGTH of idt82P33724NLG: entity is 53;
   
-- The following list specifies the characteristics of each cell in the boundary 
-- scan register from TDI to TDO. The following is a description of the label 
-- fields:
--      num     : Is the cell number.
--      cell    : Is the cell type as defined by the standard.
--      port    : Is the design port name. Control cells do not have a port 
--                name.
--      function: Is the function of the cell as defined by the standard. Is one 
--                of input, output2, output3, bidir, control or controlr.
--      safe    : Specifies the value that the BSR cell should be loaded with 
--                for safe operation when the software might otherwise choose a 
--                random value.
--      ccell   : The control cell number. Specifies the control cell that 
--                drives the output enable for this port.
--      disval  : Specifies the value that is loaded into the control cell to 
--                disable the output enable for the corresponding port.
--      rslt    : Resulting state. Shows the state of the driver when it is 
--                disabled.
   
   attribute BOUNDARY_REGISTER of idt82P33724NLG: entity is 
--     
--    num   cell   port                 function      safe  [ccell  disval  
--    rslt]
--     
     "52   (BC_0,  *,                   internal,     " &
     "X),                        " &
     "51   (BC_0,  *,                   internal,     " &
     "X),                        " &
     "50   (BC_0,  *,                   internal,     " &
     "X),                        " &
     "49   (BC_0,  *,                   internal,     " &
     "X),                        " &
     "48   (BC_0,  *,                   internal,     " &
     "X),                        " &
     "47   (BC_0,  *,                   internal,     " &
     "X),                        " &
     "46   (BC_3,  SONET_SDH_LOS3,      input,        " &
     "X),                        " &
     "45   (BC_3,  IC,                  input,        " &
     "X),                        " &
     "44   (BC_3,  IC,                  input,        " &
     "X),                        " &
     "43   (BC_1,  INT_REQ,             output3,      X,    42,     1,      " &
     "Z),  " &
     "42   (BC_1,  *,                   control,      " &
     "1),                        " &
     "41   (BC_1,  DPLL2_LOCK,          output2,      " &
     "X),                        " &
     "40   (BC_1,  DPLL1_LOCK,          output2,      " &
     "X),                        " &
     "39   (BC_1,  DPLL3_LOCK,          output2,      " &
     "X),                        " &
     "38   (BC_3,  RSTB,                input,        " &
     "X),                        " &
     "37   (BC_1,  *,                   control,      " &
     "1),                        " &
     "36   (BC_3,  SCLK_I2C_SCL,        input,        " &
     "X),                        " &
     "35   (BC_3,  CS_I2C_AD0,          input,        " &
     "X),                        " &
     "34   (BC_3,  CLKE_I2C_AD1,        input,        " &
     "X),                        " &
     "33   (BC_3,  SDI_I2C_AD2_UART_RX, input,        " &
     "X),                        " &
     "32   (BC_7,  SDO_I2C_SDA_UART_TX, bidir,        X,    37,     1,      " &
     "PULL1)," &
     "31   (BC_7,  MPU_MODE1_I2C_SCL,   bidir,        X,    30,     1,      " &
     "PULL1)," &
     "30   (BC_1,  *,                   control,      " &
     "1),                        " &
     "29   (BC_7,  MPU_MODE0_I2C_SDA,   bidir,        X,    28,     1,      " &
     "PULL1)," &
     "28   (BC_1,  *,                   control,      " &
     "1),                        " &
     "27   (BC_1,  FRSYNC_8K_1PPS,      output2,      " &
     "X),                        " &
     "26   (BC_1,  MFRSYNC_2K_1PPS,     output2,      " &
     "X),                        " &
     "25   (BC_0,  *,                   internal,     " &
     "X),                        " &
     "24   (BC_0,  *,                   internal,     " &
     "X),                        " &
     "23   (BC_0,  *,                   internal,     " &
     "X),                        " &
     "22   (BC_0,  *,                   internal,     " &
     "X),                        " &
     "21   (BC_3,  IN6,                 input,        " &
     "X),                        " &
     "20   (BC_3,  IN5,                 input,        " &
     "X),                        " &
     "19   (BC_0,  *,                   internal,     " &
     "X),                        " &
     "18   (BC_0,  *,                   internal,     " &
     "X),                        " &
     "17   (BC_3,  IN2_POS,             input,        " &
     "X),                        " &
     "16   (BC_3,  IN1_POS,             input,        " &
     "X),                        " &
     "15   (BC_3,  IN4_POS,             input,        " &
     "X),                        " &
     "14   (BC_3,  IN3_POS,             input,        " &
     "X),                        " &
     "13   (BC_0,  *,                   internal,     " &
     "X),                        " &
     "12   (BC_0,  *,                   internal,     " &
     "X),                        " &
     "11   (BC_0,  *,                   internal,     " &
     "X),                        " &
     "10   (BC_0,  *,                   internal,     " &
     "X),                        " &
     "9    (BC_0,  *,                   internal,     " &
     "X),                        " &
     "8    (BC_0,  *,                   internal,     " &
     "X),                        " &
     "7    (BC_0,  *,                   internal,     " &
     "X),                        " &
     "6    (BC_0,  *,                   internal,     " &
     "X),                        " &
     "5    (BC_0,  *,                   internal,     " &
     "X),                        " &
     "4    (BC_0,  *,                   internal,     " &
     "X),                        " &
     "3    (BC_3,  XO_FREQ2_LOS2,       input,        " &
     "X),                        " &
     "2    (BC_3,  XO_FREQ1_LOS1,       input,        " &
     "X),                        " &
     "1    (BC_3,  XO_FREQ0_LOS0,       input,        " &
     "X),                        " &
     "0    (BC_3,  OSCI,                input,        " &
     "X)                         ";
 
 end idt82P33724NLG;