-- ***********************************************************************
-- BSDL file for design ds26518
-- Created by Synopsys Version 2000.11 (Nov 27, 2000)
-- Designer:
-- Company:
-- Date: Wed Jun 27 17:51:48 2007
-- ***********************************************************************
entity ds26518 is
-- This section identifies the default device package selected.
generic (PHYSICAL_PIN_MAP: string:= "LBGA_256");
-- This section declares all the ports in the design.
port (
HIZ_N : in bit;
JTCLK : in bit;
JTDI : in bit;
JTMS : in bit;
JTRST_N : in bit;
SCAN_MODE : in bit;
A0 : inout bit;
A1 : inout bit;
A10 : inout bit;
A11 : inout bit;
A12 : inout bit;
A2 : inout bit;
A3 : inout bit;
A4 : inout bit;
A5 : inout bit;
A6 : inout bit;
A7 : inout bit;
A8 : inout bit;
A9 : inout bit;
BPCLK : inout bit;
BTS : inout bit;
CLKO : inout bit;
CSB : inout bit;
D0 : inout bit;
D1 : inout bit;
D2 : inout bit;
D3 : inout bit;
D4 : inout bit;
D5 : inout bit;
D6 : inout bit;
D7 : inout bit;
INTB : inout bit;
MCLK : inout bit;
RCHBLK1 : inout bit;
RCHBLK2 : inout bit;
RCHBLK3 : inout bit;
RCHBLK4 : inout bit;
RCHBLK5 : inout bit;
RCHBLK6 : inout bit;
RCHBLK7 : inout bit;
RCHBLK8 : inout bit;
RCLK1 : inout bit;
RCLK2 : inout bit;
RCLK3 : inout bit;
RCLK4 : inout bit;
RCLK5 : inout bit;
RCLK6 : inout bit;
RCLK7 : inout bit;
RCLK8 : inout bit;
RDB : inout bit;
REFCLKIO : inout bit;
RESETB : inout bit;
RESREF : inout bit;
RMSYNC1 : inout bit;
RMSYNC2 : inout bit;
RMSYNC3 : inout bit;
RMSYNC4 : inout bit;
RMSYNC5 : inout bit;
RMSYNC6 : inout bit;
RMSYNC7 : inout bit;
RMSYNC8 : inout bit;
RRING1 : inout bit;
RRING2 : inout bit;
RRING3 : inout bit;
RRING4 : inout bit;
RRING5 : inout bit;
RRING6 : inout bit;
RRING7 : inout bit;
RRING8 : inout bit;
RSER1 : inout bit;
RSER2 : inout bit;
RSER3 : inout bit;
RSER4 : inout bit;
RSER5 : inout bit;
RSER6 : inout bit;
RSER7 : inout bit;
RSER8 : inout bit;
RSIG1 : inout bit;
RSIG2 : inout bit;
RSIG3 : inout bit;
RSIG4 : inout bit;
RSIG5 : inout bit;
RSIG6 : inout bit;
RSIG7 : inout bit;
RSIG8 : inout bit;
RSYNC1 : inout bit;
RSYNC2 : inout bit;
RSYNC3 : inout bit;
RSYNC4 : inout bit;
RSYNC5 : inout bit;
RSYNC6 : inout bit;
RSYNC7 : inout bit;
RSYNC8 : inout bit;
RSYSCLK1 : inout bit;
RSYSCLK2 : inout bit;
RSYSCLK3 : inout bit;
RSYSCLK4 : inout bit;
RSYSCLK5 : inout bit;
RSYSCLK6 : inout bit;
RSYSCLK7 : inout bit;
RSYSCLK8 : inout bit;
RTIP1 : inout bit;
RTIP2 : inout bit;
RTIP3 : inout bit;
RTIP4 : inout bit;
RTIP5 : inout bit;
RTIP6 : inout bit;
RTIP7 : inout bit;
RTIP8 : inout bit;
SPI_SEL : inout bit;
TCHBLK1 : inout bit;
TCHBLK2 : inout bit;
TCHBLK3 : inout bit;
TCHBLK4 : inout bit;
TCHBLK5 : inout bit;
TCHBLK6 : inout bit;
TCHBLK7 : inout bit;
TCHBLK8 : inout bit;
TCLK1 : inout bit;
TCLK2 : inout bit;
TCLK3 : inout bit;
TCLK4 : inout bit;
TCLK5 : inout bit;
TCLK6 : inout bit;
TCLK7 : inout bit;
TCLK8 : inout bit;
TSER1 : inout bit;
TSER2 : inout bit;
TSER3 : inout bit;
TSER4 : inout bit;
TSER5 : inout bit;
TSER6 : inout bit;
TSER7 : inout bit;
TSER8 : inout bit;
TSIG1 : inout bit;
TSIG2 : inout bit;
TSIG3 : inout bit;
TSIG4 : inout bit;
TSIG5 : inout bit;
TSIG6 : inout bit;
TSIG7 : inout bit;
TSIG8 : inout bit;
TSSYNC : inout bit;
TSYNC1 : inout bit;
TSYNC2 : inout bit;
TSYNC3 : inout bit;
TSYNC4 : inout bit;
TSYNC5 : inout bit;
TSYNC6 : inout bit;
TSYNC7 : inout bit;
TSYNC8 : inout bit;
TSYSCLK1 : inout bit;
TSYSCLK2 : inout bit;
TSYSCLK3 : inout bit;
TSYSCLK4 : inout bit;
TSYSCLK5 : inout bit;
TSYSCLK6 : inout bit;
TSYSCLK7 : inout bit;
TSYSCLK8 : inout bit;
TX_ENABLE : inout bit;
WRB : inout bit;
TRING1 : inout bit_vector (0 to 1);
TRING2 : inout bit_vector (0 to 1);
TRING3 : inout bit_vector (0 to 1);
TRING4 : inout bit_vector (0 to 1);
TRING5 : inout bit_vector (0 to 1);
TRING6 : inout bit_vector (0 to 1);
TRING7 : inout bit_vector (0 to 1);
TRING8 : inout bit_vector (0 to 1);
TTIP1 : inout bit_vector (0 to 1);
TTIP2 : inout bit_vector (0 to 1);
TTIP3 : inout bit_vector (0 to 1);
TTIP4 : inout bit_vector (0 to 1);
TTIP5 : inout bit_vector (0 to 1);
TTIP6 : inout bit_vector (0 to 1);
TTIP7 : inout bit_vector (0 to 1);
TTIP8 : inout bit_vector (0 to 1);
JTDO : out bit;
VDD18 : linkage bit_vector (1 to 5);
VDD33 : linkage bit_vector (1 to 26);
VSS : linkage bit_vector (1 to 31)
);
use STD_1149_1_1994.all;
attribute COMPONENT_CONFORMANCE of ds26518: entity is "STD_1149_1_1993";
attribute PIN_MAP of ds26518: entity is PHYSICAL_PIN_MAP;
-- This section specifies the pin map for each port. This information
-- is extracted from the port-to-pin map file that was read in using
-- the "read_pin_map" command.
constant LBGA_256: PIN_MAP_STRING :=
"HIZ_N : D8," &
"JTCLK : F5," &
"JTDI : H4," &
"JTMS : K4," &
"JTRST_N : L5," &
"SCAN_MODE : H13," &
"A0 : C10," &
"A1 : A10," &
"A10 : B8," &
"A11 : A8," &
"A12 : C8," &
"A2 : B10," &
"A3 : F9," &
"A4 : E9," &
"A5 : D9," &
"A6 : C9," &
"A7 : A9," &
"A8 : B9," &
"A9 : F8," &
"BPCLK : E8," &
"BTS : M13," &
"CLKO : D3," &
"CSB : T7," &
"D0 : N8," &
"D1 : L9," &
"D2 : P8," &
"D3 : T8," &
"D4 : R8," &
"D5 : M9," &
"D6 : N9," &
"D7 : T9," &
"INTB : R9," &
"MCLK : B7," &
"RCHBLK1 : E4," &
"RCHBLK2 : B5," &
"RCHBLK3 : L6," &
"RCHBLK4 : T5," &
"RCHBLK5 : T11," &
"RCHBLK6 : T13," &
"RCHBLK7 : C12," &
"RCHBLK8 : G13," &
"RCLK1 : F4," &
"RCLK2 : G4," &
"RCLK3 : L4," &
"RCLK4 : M4," &
"RCLK5 : K13," &
"RCLK6 : J13," &
"RCLK7 : F13," &
"RCLK8 : E13," &
"RDB : M8," &
"REFCLKIO : A7," &
"RESETB : J12," &
"RESREF : J5," &
"RMSYNC1 : C4," &
"RMSYNC2 : C6," &
"RMSYNC3 : P4," &
"RMSYNC4 : P6," &
"RMSYNC5 : P10," &
"RMSYNC6 : N12," &
"RMSYNC7 : D11," &
"RMSYNC8 : E12," &
"RRING1 : C2," &
"RRING2 : F2," &
"RRING3 : L2," &
"RRING4 : P2," &
"RRING5 : P15," &
"RRING6 : L15," &
"RRING7 : F15," &
"RRING8 : C15," &
"RSER1 : E5," &
"RSER2 : D6," &
"RSER3 : N4," &
"RSER4 : N6," &
"RSER5 : M11," &
"RSER6 : M12," &
"RSER7 : B12," &
"RSER8 : F11," &
"RSIG1 : D4," &
"RSIG2 : E6," &
"RSIG3 : M5," &
"RSIG4 : R5," &
"RSIG5 : R11," &
"RSIG6 : R13," &
"RSIG7 : A12," &
"RSIG8 : F12," &
"RSYNC1 : A4," &
"RSYNC2 : B6," &
"RSYNC3 : N5," &
"RSYNC4 : T6," &
"RSYNC5 : R10," &
"RSYNC6 : P12," &
"RSYNC7 : C11," &
"RSYNC8 : D13," &
"RSYSCLK1 : L12," &
"RSYSCLK2 : E3," &
"RSYSCLK3 : M3," &
"RSYSCLK4 : N3," &
"RSYSCLK5 : N14," &
"RSYSCLK6 : M14," &
"RSYSCLK7 : E14," &
"RSYSCLK8 : D14," &
"RTIP1 : C1," &
"RTIP2 : F1," &
"RTIP3 : L1," &
"RTIP4 : P1," &
"RTIP5 : P16," &
"RTIP6 : L16," &
"RTIP7 : F16," &
"RTIP8 : C16," &
"SPI_SEL : C3," &
"TCHBLK1 : A5," &
"TCHBLK2 : C7," &
"TCHBLK3 : L7," &
"TCHBLK4 : P7," &
"TCHBLK5 : P9," &
"TCHBLK6 : P11," &
"TCHBLK7 : D10," &
"TCHBLK8 : E11," &
"TCLK1 : C5," &
"TCLK2 : D7," &
"TCLK3 : P5," &
"TCLK4 : L8," &
"TCLK5 : L10," &
"TCLK6 : N11," &
"TCLK7 : E10," &
"TCLK8 : B13," &
"TSER1 : F6," &
"TSER2 : E7," &
"TSER3 : R4," &
"TSER4 : N7," &
"TSER5 : M10," &
"TSER6 : L11," &
"TSER7 : F10," &
"TSER8 : D12," &
"TSIG1 : D5," &
"TSIG2 : A6," &
"TSIG3 : T4," &
"TSIG4 : R6," &
"TSIG5 : T10," &
"TSIG6 : R12," &
"TSIG7 : A11," &
"TSIG8 : C13," &
"TSSYNC : N13," &
"TSYNC1 : B4," &
"TSYNC2 : F7," &
"TSYNC3 : M6," &
"TSYNC4 : M7," &
"TSYNC5 : N10," &
"TSYNC6 : T12," &
"TSYNC7 : B11," &
"TSYNC8 : A13," &
"TSYSCLK1 : P13," &
"TSYSCLK2 : F3," &
"TSYSCLK3 : L3," &
"TSYSCLK4 : P3," &
"TSYSCLK5 : P14," &
"TSYSCLK6 : L14," &
"TSYSCLK7 : F14," &
"TSYSCLK8 : C14," &
"TX_ENABLE : L13," &
"WRB : R7," &
"TRING1 : (B3, A3)," &
"TRING2 : (H3, G3)," &
"TRING3 : (K3, J3)," &
"TRING4 : (T3, R3)," &
"TRING5 : (T14, R14)," &
"TRING6 : (K14, J14)," &
"TRING7 : (H14, G14)," &
"TRING8 : (B14, A14)," &
"TTIP1 : (A2, A1)," &
"TTIP2 : (H2, H1)," &
"TTIP3 : (J2, J1)," &
"TTIP4 : (T2, T1)," &
"TTIP5 : (T16, T15)," &
"TTIP6 : (J16, J15)," &
"TTIP7 : (H16, H15)," &
"TTIP8 : (A16, A15)," &
"JTDO : J4," &
"VDD18 : (G7, G8, G9, G10, H7)," &
"VDD33 : (D16, E16, M16, N16, N1, M1, E1, D1, B16, G16, K16, R16" &
", R1, K1, G1, B1, H8, H9, H11, H10, H6, H5, G11, G12, G5, G6)," &
"VSS : (D15, E15, M15, N15, N2, M2, E2, D2, J7, B15, G15, K15" &
", R15, R2, K2, G2, B2, J8, J9, J11, J10, J6, K9, K10, K12, K11, K6" &
", K5, K7, K8, H12)";
-- This section specifies the TAP ports.
-- For the TAP TCK port, the parameters in the brackets are:
-- First Field : Maximum TCK frequency.
-- Second Field: Allowable states TCK may be stopped in.
attribute TAP_SCAN_CLOCK of JTCLK : signal is (10.0e6, BOTH);
attribute TAP_SCAN_IN of JTDI : signal is true;
attribute TAP_SCAN_MODE of JTMS : signal is true;
attribute TAP_SCAN_OUT of JTDO : signal is true;
attribute TAP_SCAN_RESET of JTRST_N: signal is true;
-- Specifies the number of bits in the instruction register.
attribute INSTRUCTION_LENGTH of ds26518: entity is 3;
-- Specifies the boundary-scan instructions implemented in the
-- design and their opcodes.
attribute INSTRUCTION_OPCODE of ds26518: entity is
"BYPASS (111)," &
"EXTEST (000)," &
"SAMPLE (010)," &
"USER1 (100)," &
"IDCODE (001)";
-- Specifies the bit pattern that is loaded into the instruction
-- register when the TAP controller passes through the Capture-IR
-- state. The standard mandates that the two LSBs must be "01".
-- The remaining bits are design specific.
attribute INSTRUCTION_CAPTURE of ds26518: entity is "001";
-- Specifies the bit pattern that is loaded into the DEVICE_ID
-- register during the IDCODE instruction when the TAP controller
-- passes through the Capture-DR state.
attribute IDCODE_REGISTER of ds26518: entity is
"0010" & -- 4-bit version number
"0000000010001010" & -- 16-bit part number
"00010100001" & -- 11-bit identity of the manufacturer
"1"; -- Required by IEEE Std 1149.1
-- This section specifies the test data register placed between TDI
-- and TDO for each implemented instruction.
attribute REGISTER_ACCESS of ds26518: entity is
"BYPASS (BYPASS, USER1)," &
"BOUNDARY (EXTEST, SAMPLE)," &
"DEVICE_ID (IDCODE)";
-- Specifies the length of the boundary scan register.
attribute BOUNDARY_LENGTH of ds26518: entity is 268;
-- The following list specifies the characteristics of each cell
-- in the boundary scan register from TDI to TDO.
-- The following is a description of the label fields:
-- num : Is the cell number.
-- cell : Is the cell type as defined by the standard.
-- port : Is the design port name. Control cells do not
-- have a port name.
-- function: Is the function of the cell as defined by the
-- standard. Is one of input, output2, output3,
-- bidir, control or controlr.
-- safe : Specifies the value that the BSR cell should be
-- loaded with for safe operation when the software
-- might otherwise choose a random value.
-- ccell : The control cell number. Specifies the control
-- cell that drives the output enable for this port.
-- disval : Specifies the value that is loaded into the
-- control cell to disable the output enable for
-- the corresponding port.
-- rslt : Resulting state. Shows the state of the driver
-- when it is disabled.
attribute BOUNDARY_REGISTER of ds26518: entity is
--
-- num cell port function safe [ccell disval rslt]
--
"267 (BC_1, *, controlr, 0), " &
"266 (BC_0, RCHBLK3, bidir, X, 267, 0, Z), " &
"265 (BC_1, *, controlr, 0), " &
"264 (BC_0, RSIG3, bidir, X, 265, 0, Z), " &
"263 (BC_1, *, controlr, 0), " &
"262 (BC_0, RSYSCLK3, bidir, X, 263, 0, PULL0)," &
"261 (BC_1, *, controlr, 0), " &
"260 (BC_0, TSYSCLK3, bidir, X, 261, 0, PULL0)," &
"259 (BC_1, *, controlr, 0), " &
"258 (BC_0, RSER3, bidir, X, 259, 0, Z), " &
"257 (BC_1, *, controlr, 0), " &
"256 (BC_0, RMSYNC3, bidir, X, 257, 0, Z), " &
"255 (BC_1, *, controlr, 0), " &
"254 (BC_0, RSYNC3, bidir, X, 255, 0, Z), " &
"253 (BC_1, *, controlr, 0), " &
"252 (BC_0, TSIG3, bidir, X, 253, 0, Z), " &
"251 (BC_1, *, controlr, 0), " &
"250 (BC_0, TSYNC3, bidir, X, 251, 0, Z), " &
"249 (BC_1, *, controlr, 0), " &
"248 (BC_0, TSER3, bidir, X, 249, 0, Z), " &
"247 (BC_1, *, controlr, 0), " &
"246 (BC_0, TCLK3, bidir, X, 247, 0, Z), " &
"245 (BC_1, *, controlr, 0), " &
"244 (BC_0, TCHBLK3, bidir, X, 245, 0, Z), " &
"243 (BC_1, *, controlr, 0), " &
"242 (BC_0, RCHBLK4, bidir, X, 243, 0, Z), " &
"241 (BC_1, *, controlr, 0), " &
"240 (BC_0, RSIG4, bidir, X, 241, 0, Z), " &
"239 (BC_1, *, controlr, 0), " &
"238 (BC_0, RSYSCLK4, bidir, X, 239, 0, PULL0)," &
"237 (BC_1, *, controlr, 0), " &
"236 (BC_0, TSYSCLK4, bidir, X, 237, 0, PULL0)," &
"235 (BC_1, *, controlr, 0), " &
"234 (BC_0, RSER4, bidir, X, 235, 0, Z), " &
"233 (BC_1, *, controlr, 0), " &
"232 (BC_0, RMSYNC4, bidir, X, 233, 0, Z), " &
"231 (BC_1, *, controlr, 0), " &
"230 (BC_0, RSYNC4, bidir, X, 231, 0, Z), " &
"229 (BC_1, *, controlr, 0), " &
"228 (BC_0, TSIG4, bidir, X, 229, 0, Z), " &
"227 (BC_1, *, controlr, 0), " &
"226 (BC_0, TSYNC4, bidir, X, 227, 0, Z), " &
"225 (BC_1, *, controlr, 0), " &
"224 (BC_0, TSER4, bidir, X, 225, 0, Z), " &
"223 (BC_1, *, controlr, 0), " &
"222 (BC_0, TCLK4, bidir, X, 223, 0, Z), " &
"221 (BC_1, *, controlr, 0), " &
"220 (BC_0, TCHBLK4, bidir, X, 221, 0, Z), " &
"219 (BC_1, *, controlr, 0), " &
"218 (BC_0, CSB, bidir, X, 219, 0, Z), " &
"217 (BC_1, *, controlr, 0), " &
"216 (BC_0, WRB, bidir, X, 217, 0, Z), " &
"215 (BC_1, *, controlr, 0), " &
"214 (BC_0, RDB, bidir, X, 215, 0, Z), " &
"213 (BC_1, *, controlr, 0), " &
"212 (BC_0, D0, bidir, X, 213, 0, Z), " &
"211 (BC_1, *, controlr, 0), " &
"210 (BC_0, D1, bidir, X, 211, 0, Z), " &
"209 (BC_1, *, controlr, 0), " &
"208 (BC_0, D2, bidir, X, 209, 0, Z), " &
"207 (BC_1, *, controlr, 0), " &
"206 (BC_0, D3, bidir, X, 207, 0, Z), " &
"205 (BC_1, *, controlr, 0), " &
"204 (BC_0, D4, bidir, X, 205, 0, Z), " &
"203 (BC_1, *, controlr, 0), " &
"202 (BC_0, D5, bidir, X, 203, 0, Z), " &
"201 (BC_1, *, controlr, 0), " &
"200 (BC_0, D6, bidir, X, 201, 0, Z), " &
"199 (BC_1, *, controlr, 0), " &
"198 (BC_0, D7, bidir, X, 199, 0, Z), " &
"197 (BC_1, *, controlr, 0), " &
"196 (BC_0, INTB, bidir, X, 197, 0, Z), " &
"195 (BC_1, *, controlr, 0), " &
"194 (BC_0, TCHBLK5, bidir, X, 195, 0, Z), " &
"193 (BC_1, *, controlr, 0), " &
"192 (BC_0, TCLK5, bidir, X, 193, 0, Z), " &
"191 (BC_1, *, controlr, 0), " &
"190 (BC_0, TSER5, bidir, X, 191, 0, Z), " &
"189 (BC_1, *, controlr, 0), " &
"188 (BC_0, TSYNC5, bidir, X, 189, 0, Z), " &
"187 (BC_1, *, controlr, 0), " &
"186 (BC_0, TSIG5, bidir, X, 187, 0, Z), " &
"185 (BC_1, *, controlr, 0), " &
"184 (BC_0, RSYNC5, bidir, X, 185, 0, Z), " &
"183 (BC_1, *, controlr, 0), " &
"182 (BC_0, RMSYNC5, bidir, X, 183, 0, Z), " &
"181 (BC_1, *, controlr, 0), " &
"180 (BC_0, RSER5, bidir, X, 181, 0, Z), " &
"179 (BC_1, *, controlr, 0), " &
"178 (BC_0, TSYSCLK5, bidir, X, 179, 0, PULL0)," &
"177 (BC_1, *, controlr, 0), " &
"176 (BC_0, RSYSCLK5, bidir, X, 177, 0, PULL0)," &
"175 (BC_1, *, controlr, 0), " &
"174 (BC_0, RSIG5, bidir, X, 175, 0, Z), " &
"173 (BC_1, *, controlr, 0), " &
"172 (BC_0, RCHBLK5, bidir, X, 173, 0, Z), " &
"171 (BC_1, *, controlr, 0), " &
"170 (BC_0, TCHBLK6, bidir, X, 171, 0, Z), " &
"169 (BC_1, *, controlr, 0), " &
"168 (BC_0, TCLK6, bidir, X, 169, 0, Z), " &
"167 (BC_1, *, controlr, 0), " &
"166 (BC_0, TSER6, bidir, X, 167, 0, Z), " &
"165 (BC_1, *, controlr, 0), " &
"164 (BC_0, TSYNC6, bidir, X, 165, 0, Z), " &
"163 (BC_1, *, controlr, 0), " &
"162 (BC_0, TSIG6, bidir, X, 163, 0, Z), " &
"161 (BC_1, *, controlr, 0), " &
"160 (BC_0, RSYNC6, bidir, X, 161, 0, Z), " &
"159 (BC_1, *, controlr, 0), " &
"158 (BC_0, RMSYNC6, bidir, X, 159, 0, Z), " &
"157 (BC_1, *, controlr, 0), " &
"156 (BC_0, RSER6, bidir, X, 157, 0, Z), " &
"155 (BC_1, *, controlr, 0), " &
"154 (BC_0, TSYSCLK6, bidir, X, 155, 0, PULL0)," &
"153 (BC_1, *, controlr, 0), " &
"152 (BC_0, RSYSCLK6, bidir, X, 153, 0, PULL0)," &
"151 (BC_1, *, controlr, 0), " &
"150 (BC_0, RSIG6, bidir, X, 151, 0, Z), " &
"149 (BC_1, *, controlr, 0), " &
"148 (BC_0, RCHBLK6, bidir, X, 149, 0, Z), " &
"147 (BC_1, *, controlr, 0), " &
"146 (BC_0, TSYSCLK1, bidir, X, 147, 0, Z), " &
"145 (BC_1, *, controlr, 0), " &
"144 (BC_0, TSSYNC, bidir, X, 145, 0, Z), " &
"143 (BC_1, *, controlr, 0), " &
"142 (BC_0, RSYSCLK1, bidir, X, 143, 0, Z), " &
"141 (BC_1, *, controlr, 0), " &
"140 (BC_0, BTS, bidir, X, 141, 0, Z), " &
"139 (BC_1, *, controlr, 0), " &
"138 (BC_0, TX_ENABLE, bidir, X, 139, 0, Z), " &
"137 (BC_1, *, controlr, 0), " &
"136 (BC_0, RESETB, bidir, X, 137, 0, Z), " &
"135 (BC_1, *, controlr, 0), " &
"134 (BC_0, RCLK5, bidir, X, 135, 0, Z), " &
"133 (BC_1, *, controlr, 0), " &
"132 (BC_0, RCLK6, bidir, X, 133, 0, Z), " &
"131 (BC_1, *, controlr, 0), " &
"130 (BC_0, RCHBLK8, bidir, X, 131, 0, Z), " &
"129 (BC_1, *, controlr, 0), " &
"128 (BC_0, RSIG8, bidir, X, 129, 0, Z), " &
"127 (BC_1, *, controlr, 0), " &
"126 (BC_0, RCLK7, bidir, X, 127, 0, Z), " &
"125 (BC_1, *, controlr, 0), " &
"124 (BC_0, RCLK8, bidir, X, 125, 0, Z), " &
"123 (BC_1, *, controlr, 0), " &
"122 (BC_0, RSYSCLK8, bidir, X, 123, 0, PULL0)," &
"121 (BC_1, *, controlr, 0), " &
"120 (BC_0, TSYSCLK8, bidir, X, 121, 0, PULL0)," &
"119 (BC_1, *, controlr, 0), " &
"118 (BC_0, RSER8, bidir, X, 119, 0, Z), " &
"117 (BC_1, *, controlr, 0), " &
"116 (BC_0, RMSYNC8, bidir, X, 117, 0, Z), " &
"115 (BC_1, *, controlr, 0), " &
"114 (BC_0, RSYNC8, bidir, X, 115, 0, Z), " &
"113 (BC_1, *, controlr, 0), " &
"112 (BC_0, TSIG8, bidir, X, 113, 0, Z), " &
"111 (BC_1, *, controlr, 0), " &
"110 (BC_0, TSYNC8, bidir, X, 111, 0, Z), " &
"109 (BC_1, *, controlr, 0), " &
"108 (BC_0, TSER8, bidir, X, 109, 0, Z), " &
"107 (BC_1, *, controlr, 0), " &
"106 (BC_0, TCLK8, bidir, X, 107, 0, Z), " &
"105 (BC_1, *, controlr, 0), " &
"104 (BC_0, TCHBLK8, bidir, X, 105, 0, Z), " &
"103 (BC_1, *, controlr, 0), " &
"102 (BC_0, RCHBLK7, bidir, X, 103, 0, Z), " &
"101 (BC_1, *, controlr, 0), " &
"100 (BC_0, RSIG7, bidir, X, 101, 0, Z), " &
"99 (BC_1, *, controlr, 0), " &
"98 (BC_0, RSYSCLK7, bidir, X, 99, 0, PULL0)," &
"97 (BC_1, *, controlr, 0), " &
"96 (BC_0, TSYSCLK7, bidir, X, 97, 0, PULL0)," &
"95 (BC_1, *, controlr, 0), " &
"94 (BC_0, RSER7, bidir, X, 95, 0, Z), " &
"93 (BC_1, *, controlr, 0), " &
"92 (BC_0, RMSYNC7, bidir, X, 93, 0, Z), " &
"91 (BC_1, *, controlr, 0), " &
"90 (BC_0, RSYNC7, bidir, X, 91, 0, Z), " &
"89 (BC_1, *, controlr, 0), " &
"88 (BC_0, TSIG7, bidir, X, 89, 0, Z), " &
"87 (BC_1, *, controlr, 0), " &
"86 (BC_0, TSYNC7, bidir, X, 87, 0, Z), " &
"85 (BC_1, *, controlr, 0), " &
"84 (BC_0, TSER7, bidir, X, 85, 0, Z), " &
"83 (BC_1, *, controlr, 0), " &
"82 (BC_0, TCLK7, bidir, X, 83, 0, Z), " &
"81 (BC_1, *, controlr, 0), " &
"80 (BC_0, TCHBLK7, bidir, X, 81, 0, Z), " &
"79 (BC_1, *, controlr, 0), " &
"78 (BC_0, A0, bidir, X, 79, 0, Z), " &
"77 (BC_1, *, controlr, 0), " &
"76 (BC_0, A1, bidir, X, 77, 0, Z), " &
"75 (BC_1, *, controlr, 0), " &
"74 (BC_0, A2, bidir, X, 75, 0, Z), " &
"73 (BC_1, *, controlr, 0), " &
"72 (BC_0, A3, bidir, X, 73, 0, Z), " &
"71 (BC_1, *, controlr, 0), " &
"70 (BC_0, A4, bidir, X, 71, 0, Z), " &
"69 (BC_1, *, controlr, 0), " &
"68 (BC_0, A5, bidir, X, 69, 0, Z), " &
"67 (BC_1, *, controlr, 0), " &
"66 (BC_0, A6, bidir, X, 67, 0, Z), " &
"65 (BC_1, *, controlr, 0), " &
"64 (BC_0, A7, bidir, X, 65, 0, Z), " &
"63 (BC_1, *, controlr, 0), " &
"62 (BC_0, A8, bidir, X, 63, 0, Z), " &
"61 (BC_1, *, controlr, 0), " &
"60 (BC_0, A9, bidir, X, 61, 0, Z), " &
"59 (BC_1, *, controlr, 0), " &
"58 (BC_0, A10, bidir, X, 59, 0, Z), " &
"57 (BC_1, *, controlr, 0), " &
"56 (BC_0, A11, bidir, X, 57, 0, Z), " &
"55 (BC_1, *, controlr, 0), " &
"54 (BC_0, TCHBLK2, bidir, X, 55, 0, Z), " &
"53 (BC_1, *, controlr, 0), " &
"52 (BC_0, MCLK, bidir, X, 53, 0, Z), " &
"51 (BC_1, *, controlr, 0), " &
"50 (BC_0, REFCLKIO, bidir, X, 51, 0, Z), " &
"49 (BC_1, *, controlr, 0), " &
"48 (BC_0, BPCLK, bidir, X, 49, 0, Z), " &
"47 (BC_1, *, controlr, 0), " &
"46 (BC_0, A12, bidir, X, 47, 0, Z), " &
"45 (BC_1, *, controlr, 0), " &
"44 (BC_0, RMSYNC2, bidir, X, 45, 0, Z), " &
"43 (BC_1, *, controlr, 0), " &
"42 (BC_0, RSYNC2, bidir, X, 43, 0, Z), " &
"41 (BC_1, *, controlr, 0), " &
"40 (BC_0, TSIG2, bidir, X, 41, 0, Z), " &
"39 (BC_1, *, controlr, 0), " &
"38 (BC_0, TSYNC2, bidir, X, 39, 0, Z), " &
"37 (BC_1, *, controlr, 0), " &
"36 (BC_0, TSER2, bidir, X, 37, 0, Z), " &
"35 (BC_1, *, controlr, 0), " &
"34 (BC_0, TCLK2, bidir, X, 35, 0, Z), " &
"33 (BC_1, *, controlr, 0), " &
"32 (BC_0, RSER2, bidir, X, 33, 0, Z), " &
"31 (BC_1, *, controlr, 0), " &
"30 (BC_0, TSYSCLK2, bidir, X, 31, 0, PULL0)," &
"29 (BC_1, *, controlr, 0), " &
"28 (BC_0, RSYSCLK2, bidir, X, 29, 0, PULL0)," &
"27 (BC_1, *, controlr, 0), " &
"26 (BC_0, TCLK1, bidir, X, 27, 0, Z), " &
"25 (BC_1, *, controlr, 0), " &
"24 (BC_0, TSER1, bidir, X, 25, 0, Z), " &
"23 (BC_1, *, controlr, 0), " &
"22 (BC_0, TSIG1, bidir, X, 23, 0, Z), " &
"21 (BC_1, *, controlr, 0), " &
"20 (BC_0, RSYNC1, bidir, X, 21, 0, Z), " &
"19 (BC_1, *, controlr, 0), " &
"18 (BC_0, RMSYNC1, bidir, X, 19, 0, Z), " &
"17 (BC_1, *, controlr, 0), " &
"16 (BC_0, RSER1, bidir, X, 17, 0, Z), " &
"15 (BC_1, *, controlr, 0), " &
"14 (BC_0, SPI_SEL, bidir, X, 15, 0, PULL0)," &
"13 (BC_1, *, controlr, 0), " &
"12 (BC_0, CLKO, bidir, X, 13, 0, Z), " &
"11 (BC_1, *, controlr, 0), " &
"10 (BC_0, RSIG1, bidir, X, 11, 0, Z), " &
"9 (BC_1, *, controlr, 0), " &
"8 (BC_0, RCHBLK1, bidir, X, 9, 0, Z), " &
"7 (BC_1, *, controlr, 0), " &
"6 (BC_0, RCLK4, bidir, X, 7, 0, Z), " &
"5 (BC_1, *, controlr, 0), " &
"4 (BC_0, RCLK1, bidir, X, 5, 0, Z), " &
"3 (BC_1, *, controlr, 0), " &
"2 (BC_0, RCLK3, bidir, X, 3, 0, Z), " &
"1 (BC_1, *, controlr, 0), " &
"0 (BC_0, RCLK2, bidir, X, 1, 0, Z) ";
end ds26518;
