-- ***********************************************************************
--
-- File Name : DS26504_BSDL
-- Created by Synopsys Version 2000.11 (Nov 27, 2000)
--
-- Company : Dallas Semiconductor/Maxim
-- Documentation : DS26504 datasheet
-- BSDL Revision : 1.0
-- Date : 9/8/2005
--
-- Device : DS26504
-- Package : 64-pin LQFP
--
-- IMPORTANT NOTICE
-- Dallas Semiconductor customers are advised to obtain the latest version of
-- device specifications before relying on any published information contained
-- herein. Dallas Semiconductor assumes no responsibility or liability arising
-- out of the application of any information described herein.
--
-- IMPORTANT NOTICE ABOUT THE REVISION
--
-- Dallas Semiconductor customers are advised to check the revision of the
-- device they will be using. All the codes for the device revisions are
-- herein this BSDL file.
--
-- The characters "/", "(", ")" and "*" have been removed from signal names for
-- compatibility with BSDL file format.
--
-- ***********************************************************************
entity DS26504 is
-- This section identifies the default device package selected.
generic (PHYSICAL_PIN_MAP: string:= "LQFP_64");
-- This section declares all the ports in the design.
port (
TTIP :linkage bit;
TRING :linkage bit;
AD7 :inout bit;
AD6 :inout bit;
AD5 :inout bit;
AD4 :inout bit;
AD3 :inout bit;
AD2 :inout bit;
AD1 :inout bit;
AD0 :inout bit;
TSYNC :inout bit;
TSER :in bit;
TCSS1 :in bit;
TCLK :in bit;
TCLKO :out bit;
TPOSO :out bit;
TNEGO :out bit;
CS :in bit;
RDDS :in bit;
WRRW :in bit;
RTIP :linkage bit;
RRING :linkage bit;
RAIS :out bit;
RCLK :out bit;
RSYNC :out bit;
RSER :out bit;
RLOF :out bit;
RLOS :out bit;
OUT400 :out bit;
PLL_CLK :out bit;
TMODE1 :in bit;
TMODE2 :in bit;
THZE :in bit;
INT :inout bit;
TSTRST :in bit;
BIS0 :in bit;
BIS1 :in bit;
BTS :in bit;
MCLK :in bit;
JTRST :in bit;
JTCLK :in bit;
JTDI :in bit;
JTDO :out bit;
JTMS :in bit;
ALE_A7 :in bit;
A6 :in bit;
A5 :in bit;
A4 :in bit;
A3 :in bit;
A2 :in bit;
A1 :in bit;
A0 :in bit;
TVDD :linkage bit;
TVSS :linkage bit;
DVDD :linkage bit_vector(1 to 3);
DVSS :linkage bit_vector(1 to 3);
RVDD :linkage bit;
RVSS :linkage bit_vector(1 to 3)
);
use STD_1149_1_1994.all;
attribute COMPONENT_CONFORMANCE of DS26504: entity is "STD_1149_1_1993";
attribute PIN_MAP of DS26504: entity is PHYSICAL_PIN_MAP;
-- This section specifies the pin map for each port. This information
-- is extracted from the port-to-pin map file that was read in using
-- the "read_pin_map" command.
constant LQFP_64: PIN_MAP_STRING :=
"TTIP :51 ,"&
"TRING :54 ,"&
"AD7 :6 ,"&
"AD6 :5 ,"&
"AD5 :4 ,"&
"AD4 :3 ,"&
"AD3 :2 ,"&
"AD2 :1 ,"&
"AD1 :64 ,"&
"AD0 :63 ,"&
"TSYNC :23 ,"&
"TSER :21 ,"&
"TCSS1 :31 ,"&
"TCLK :17 ,"&
"TCLKO :18 ,"&
"TNEGO :19 ,"&
"TPOSO :20 ,"&
"CS :60 ,"&
"RDDS :61 ,"&
"WRRW :62 ,"&
"RTIP :41 ,"&
"RRING :42 ,"&
"RAIS :29 ,"&
"RCLK :25 ,"&
"RSYNC :26 ,"&
"RSER :28 ,"&
"RLOF :30 ,"&
"RLOS :32 ,"&
"OUT400 :27 ,"&
"PLL_CLK :47 ,"&
"TMODE1 :49 ,"&
"TMODE2 :48 ,"&
"THZE :50 ,"&
"INT :46 ,"&
"TSTRST :39 ,"&
"BIS0 :59 ,"&
"BIS1 :57 ,"&
"BTS :55 ,"&
"MCLK :44 ,"&
"JTRST :35 ,"&
"JTCLK :34 ,"&
"JTDI :36 ,"&
"JTDO :37 ,"&
"JTMS :33 ,"&
"ALE_A7 :16 ,"&
"A6 :15 ,"&
"A5 :14 ,"&
"A4 :13 ,"&
"A3 :12 ,"&
"A2 :11 ,"&
"A1 :10 ,"&
"A0 :9 ,"&
"TVDD :53 ,"&
"TVSS :52 ,"&
"DVDD :(58, 7, 24) ,"&
"DVSS :(56, 8, 22) ,"&
"RVDD :38 ,"&
"RVSS :(40, 43, 45)";
-- This section specifies the TAP ports.
-- For the TAP TCK port, the parameters in the brackets are:
-- First Field : Maximum TCK frequency.
-- Second Field: Allowable states TCK may be stopped in.
attribute TAP_SCAN_CLOCK of JTCLK : signal is (10.0e6, BOTH);
attribute TAP_SCAN_IN of JTDI : signal is true;
attribute TAP_SCAN_MODE of JTMS : signal is true;
attribute TAP_SCAN_OUT of JTDO : signal is true;
attribute TAP_SCAN_RESET of JTRST : signal is true;
-- Specifies the number of bits in the instruction register.
attribute INSTRUCTION_LENGTH of DS26504: entity is 3;
-- Specifies the boundary-scan instructions implemented in the
-- design and their opcodes.
attribute INSTRUCTION_OPCODE of DS26504: entity is
"BYPASS (111)," &
"EXTEST (000)," &
"SAMPLE (010)," &
"CLAMP (011)," &
"HIGHZ (100)," &
"IDCODE (001)";
-- Specifies the bit pattern that is loaded into the instruction
-- register when the TAP controller passes through the Capture-IR
-- state. The standard mandates that the two LSBs must be "01".
-- The remaining bits are design specific.
attribute INSTRUCTION_CAPTURE of DS26504: entity is "001";
-- Specifies the bit pattern that is loaded into the DEVICE_ID
-- register during the IDCODE instruction when the TAP controller
-- passes through the Capture-DR state.
-- 00035143 (HEX)
attribute IDCODE_REGISTER of DS26504: entity is
"0000" & -- 4-bit version number [31-28]
"0000000000110100" & -- 16-bit part number [27-12]
"00010100001" & -- 11-bit identity of the manufacturer [11- 1]
"1"; -- Required by IEEE Std 1149.1 [0]
-- This section specifies the test data register placed between TDI
-- and TDO for each implemented instruction.
-- attribute REGISTER_ACCESS of DS26504: entity is
"BYPASS (BYPASS, CLAMP, HIGHZ)," &
"BOUNDARY (EXTEST, SAMPLE)," &
"DEVICE_ID (IDCODE)";
-- Specifies the length of the boundary scan register.
attribute BOUNDARY_LENGTH of DS26504: entity is 46;
attribute BOUNDARY_REGISTER of DS26504: entity is
--
-- num cell port function safe [ccell disval rslt]
--
" 0 (BC_7, AD1 , bidir, 0, 1, 0, Z) ,"&
" 1 (BC_2, * , control, 0) ,"&
" 2 (BC_7, AD0 , bidir, 0, 3, 0, Z) ,"&
" 3 (BC_2, * , control, 0) ,"&
" 4 (BC_1, WRRW , input, X) ,"&
" 5 (BC_1, RDDS , input, X) ,"&
" 6 (BC_1, CS , input, X) ,"&
" 7 (BC_1, BIS1 , input, X) ,"&
" 8 (BC_1, BIS0 , input, X) ,"&
" 9 (BC_1, BTS , input, X) ,"&
" 10 (BC_1, THZE , input, X) ,"&
" 11 (BC_1, TMODE1 , input, X) ,"&
" 12 (BC_1, TMODE2 , input, X) ,"&
" 13 (BC_1, PLL_CLK , output2, X) ,"&
" 14 (BC_7, INT , bidir, 0, 15, 0, Z) ,"&
" 15 (BC_2, * , control, 0) ,"&
" 16 (BC_1, TSTRST , input, X) ,"&
" 17 (BC_1, RLOS , output2, X) ,"&
" 18 (BC_1, TCSS1 , input, X) ,"&
" 19 (BC_1, RLOF , output2, X) ,"&
" 20 (BC_1, RAIS , output2, X) ,"&
" 21 (BC_1, RSER , output2, X) ,"&
" 22 (BC_1, OUT400 , output2, X) ,"&
" 23 (BC_1, RSYNC , output2, X) ,"&
" 24 (BC_1, RCLK , output2, X) ,"&
" 25 (BC_7, TSYNC , bidir, 0, 26, 0, Z) ,"&
" 26 (BC_2, * , control, 0) ,"&
" 27 (BC_1, TSER , input, X) ,"&
" 28 (BC_1, TPOSO , output2, X) ,"&
" 29 (BC_1, TNEGO , output2, X) ,"&
" 30 (BC_1, TCLKO , output2, X) ,"&
" 31 (BC_1, TCLK , input, X) ,"&
" 32 (BC_1, ALE_A7 , input, X) ,"&
" 33 (BC_1, A6 , input, X) ,"&
" 34 (BC_1, A5 , input, X) ,"&
" 35 (BC_1, A4 , input, X) ,"&
" 36 (BC_1, A3 , input, X) ,"&
" 37 (BC_1, A2 , input, X) ,"&
" 38 (BC_1, A1 , input, X) ,"&
" 39 (BC_1, A0 , input, X) ,"&
" 40 (BC_7, AD7 , bidir, 0, 1 , 0, Z) ,"&
" 41 (BC_7, AD6 , bidir, 0, 1 , 0, Z) ,"&
" 42 (BC_7, AD5 , bidir, 0, 1 , 0, Z) ,"&
" 43 (BC_7, AD4 , bidir, 0, 1 , 0, Z) ,"&
" 44 (BC_7, AD3 , bidir, 0, 1 , 0, Z) ,"&
" 45 (BC_7, AD2 , bidir, 0, 1 , 0, Z) ";
end DS26504;