-- *****************************************************************************
-- BSDL file for design top
-- Created by Synopsys Version 2002.05-SP2 (Nov 15, 2002)
-- Company: IDT
-- Date: Fri Aug 29 17:34:24 2003
-- *****************************************************************************
entity top is
-- This section identifies the default device package selected.
generic (PHYSICAL_PIN_MAP: string:= "IDT82V2042EPF");
-- This section declares all the ports in the design.
port (
CSB_LP11 : in bit;
DSB_RDB_SCKES_LP21 : in bit;
JA0 : in bit;
JA1 : in bit;
MCLK : in bit;
MODE0 : in bit;
MODE1 : in bit;
MONT1 : in bit;
MONT2 : in bit;
MUX_CLKE : in bit;
RST : in bit;
RXTXM0 : in bit;
RXTXM1 : in bit;
R_nW_WRB_SDI_PATT10 : in bit;
SCLK_PATT11 : in bit;
TCK : in bit;
TCLK1 : in bit;
TCLK2 : in bit;
TDI : in bit;
TDN1 : in bit;
TDN2 : in bit;
TDP1 : in bit;
TDP2 : in bit;
TERM1 : in bit;
TERM2 : in bit;
TMS : in bit;
TRST : in bit;
TXZ : in bit;
A : in bit_vector (0 to 5);
INT_LP10 : inout bit;
SDO_LP20 : inout bit;
D : inout bit_vector (0 to 7);
TDO : out bit;
LOS1 : buffer bit;
LOS2 : buffer bit;
RCLK1 : buffer bit;
RCLK2 : buffer bit;
RDN1 : buffer bit;
RDN2 : buffer bit;
RDP1 : buffer bit;
RDP2 : buffer bit;
GNDA : linkage bit;
GNDD : linkage bit;
GNDR1 : linkage bit;
GNDR2 : linkage bit;
GNDT1 : linkage bit;
GNDT2 : linkage bit;
VDDA : linkage bit;
VDDD : linkage bit;
VDDR1 : linkage bit;
VDDR2 : linkage bit;
VDDT1 : linkage bit;
VDDT2 : linkage bit;
GNDIO : linkage bit_vector (1 to 2);
VDDIO : linkage bit_vector (1 to 2)
);
use STD_1149_1_1994.all;
attribute COMPONENT_CONFORMANCE of top: entity is "STD_1149_1_1993";
attribute PIN_MAP of top: entity is PHYSICAL_PIN_MAP;
-- This section specifies the pin map for each port. This information is
-- extracted from the port-to-pin map file that was read in using the
-- "read_pin_map" command.
constant IDT82V2042EPF: PIN_MAP_STRING :=
"CSB_LP11 : 42," &
"DSB_RDB_SCKES_LP21 : 45," &
"JA0 : 17," &
"JA1 : 16," &
"MCLK : 30," &
"MODE0 : 10," &
"MODE1 : 9," &
"MONT1 : 19," &
"MONT2 : 18," &
"MUX_CLKE : 11," &
"RST : 21," &
"RXTXM0 : 15," &
"RXTXM1 : 14," &
"R_nW_WRB_SDI_PATT10 : 44," &
"SCLK_PATT11 : 46," &
"TCK : 3," &
"TCLK1 : 38," &
"TCLK2 : 22," &
"TDI : 5," &
"TDN1 : 36," &
"TDN2 : 24," &
"TDP1 : 37," &
"TDP2 : 23," &
"TERM1 : 13," &
"TERM2 : 12," &
"TMS : 2," &
"TRST : 1," &
"TXZ : 20," &
"A : (55, 56, 57, 58, 59, 60)," &
"INT_LP10 : 41," &
"SDO_LP20 : 43," &
"D : (47, 48, 49, 50, 51, 52, 53, 54)," &
"TDO : 4," &
"LOS1 : 32," &
"LOS2 : 28," &
"RCLK1 : 35," &
"RCLK2 : 25," &
"RDN1 : 33," &
"RDN2 : 27," &
"RDP1 : 34," &
"RDP2 : 26," &
"GNDA : 72," &
"GNDD : 29," &
"GNDR1 : 65," &
"GNDR2 : 76," &
"GNDT1 : 64," &
"GNDT2 : 77," &
"VDDA : 69," &
"VDDD : 31," &
"VDDR1 : 68," &
"VDDR2 : 73," &
"VDDT1 : 61," &
"VDDT2 : 80," &
"GNDIO : (8, 39)," &
"VDDIO : (7, 40)";
-- This section specifies the TAP ports. For the TAP TCK port, the parameters in
-- the brackets are:
-- First Field : Maximum TCK frequency.
-- Second Field: Allowable states TCK may be stopped in.
attribute TAP_SCAN_CLOCK of TCK : signal is (10.0e6, BOTH);
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_RESET of TRST: signal is true;
-- Specifies the number of bits in the instruction register.
attribute INSTRUCTION_LENGTH of top: entity is 3;
-- Specifies the boundary-scan instructions implemented in the design and their
-- opcodes.
attribute INSTRUCTION_OPCODE of top: entity is
"BYPASS (111)," &
"EXTEST (000)," &
"SAMPLE (010)," &
"USER1 (011)," &
"USER2 (101)," &
"USER3 (110)," &
"IDCODE (001)," &
"USER4 (100)";
-- Specifies the bit pattern that is loaded into the instruction register when
-- the TAP controller passes through the Capture-IR state. The standard mandates
-- that the two LSBs must be "01". The remaining bits are design specific.
attribute INSTRUCTION_CAPTURE of top: entity is "001";
-- Specifies the bit pattern that is loaded into the DEVICE_ID register during
-- the IDCODE instruction when the TAP controller passes through the Capture-DR
-- state.
attribute IDCODE_REGISTER of top: entity is
"0000" &
-- 4-bit version number
"0000010011010110" &
-- 16-bit part number
"00010110011" &
-- 11-bit identity of the manufacturer
"1";
-- Required by IEEE Std 1149.1
-- This section specifies the test data register placed between TDI and TDO for
-- each implemented instruction.
attribute REGISTER_ACCESS of top: entity is
"BYPASS (BYPASS)," &
"BOUNDARY (EXTEST, SAMPLE, USER1, USER2, USER3)," &
"DEVICE_ID (IDCODE)," &
"UTDR1[2] (USER4)";
-- Specifies the length of the boundary scan register.
attribute BOUNDARY_LENGTH of top: entity is 51;
-- The following list specifies the characteristics of each cell in the boundary
-- scan register from TDI to TDO. The following is a description of the label
-- fields:
-- num : Is the cell number.
-- cell : Is the cell type as defined by the standard.
-- port : Is the design port name. Control cells do not have a port
-- name.
-- function: Is the function of the cell as defined by the standard. Is one
-- of input, output2, output3, bidir, control or controlr.
-- safe : Specifies the value that the BSR cell should be loaded with
-- for safe operation when the software might otherwise choose a
-- random value.
-- ccell : The control cell number. Specifies the control cell that
-- drives the output enable for this port.
-- disval : Specifies the value that is loaded into the control cell to
-- disable the output enable for the corresponding port.
-- rslt : Resulting state. Shows the state of the driver when it is
-- disabled.
attribute BOUNDARY_REGISTER of top: entity is
--
-- num cell port function safe [ccell disval
-- rslt]
--
"50 (BC_3, MODE1, input, " &
"X), " &
"49 (BC_3, MODE0, input, " &
"X), " &
"48 (BC_3, MUX_CLKE, input, " &
"X), " &
"47 (BC_3, TERM2, input, " &
"X), " &
"46 (BC_3, TERM1, input, " &
"X), " &
"45 (BC_3, RXTXM1, input, " &
"X), " &
"44 (BC_3, RXTXM0, input, " &
"X), " &
"43 (BC_3, JA1, input, " &
"X), " &
"42 (BC_3, JA0, input, " &
"X), " &
"41 (BC_3, MONT2, input, " &
"X), " &
"40 (BC_3, MONT1, input, " &
"X), " &
"39 (BC_3, TXZ, input, " &
"X), " &
"38 (BC_3, RST, input, " &
"X), " &
"37 (BC_3, TCLK2, input, " &
"X), " &
"36 (BC_3, TDP2, input, " &
"X), " &
"35 (BC_3, TDN2, input, " &
"X), " &
"34 (BC_1, RCLK2, output2, " &
"X), " &
"33 (BC_1, RDP2, output2, " &
"X), " &
"32 (BC_1, RDN2, output2, " &
"X), " &
"31 (BC_1, LOS2, output2, " &
"X), " &
"30 (BC_3, MCLK, input, " &
"X), " &
"29 (BC_1, LOS1, output2, " &
"X), " &
"28 (BC_1, RDN1, output2, " &
"X), " &
"27 (BC_1, RDP1, output2, " &
"X), " &
"26 (BC_1, RCLK1, output2, " &
"X), " &
"25 (BC_3, TDN1, input, " &
"X), " &
"24 (BC_3, TDP1, input, " &
"X), " &
"23 (BC_3, TCLK1, input, " &
"X), " &
"22 (BC_1, *, control, " &
"1), " &
"21 (BC_7, INT_LP10, bidir, X, 22, 1, " &
"Z), " &
"20 (BC_3, CSB_LP11, input, " &
"X), " &
"19 (BC_1, *, control, " &
"1), " &
"18 (BC_7, SDO_LP20, bidir, X, 19, 1, " &
"Z), " &
"17 (BC_3, R_nW_WRB_SDI_PATT10, input, " &
"X), " &
"16 (BC_3, DSB_RDB_SCKES_LP21, input, " &
"X), " &
"15 (BC_3, SCLK_PATT11, input, " &
"X), " &
"14 (BC_7, D(0), bidir, X, 6, 1, " &
"Z), " &
"13 (BC_7, D(1), bidir, X, 6, 1, " &
"Z), " &
"12 (BC_7, D(2), bidir, X, 6, 1, " &
"Z), " &
"11 (BC_7, D(3), bidir, X, 6, 1, " &
"Z), " &
"10 (BC_7, D(4), bidir, X, 6, 1, " &
"Z), " &
"9 (BC_7, D(5), bidir, X, 6, 1, " &
"Z), " &
"8 (BC_7, D(6), bidir, X, 6, 1, " &
"Z), " &
"7 (BC_7, D(7), bidir, X, 6, 1, " &
"Z), " &
"6 (BC_1, *, control, " &
"1), " &
"5 (BC_3, A(0), input, " &
"X), " &
"4 (BC_3, A(1), input, " &
"X), " &
"3 (BC_3, A(2), input, " &
"X), " &
"2 (BC_3, A(3), input, " &
"X), " &
"1 (BC_3, A(4), input, " &
"X), " &
"0 (BC_3, A(5), input, " &
"X) ";
end top;