BSDL Files Library for JTAG

The only free public library that contains thousands of BSDL (Boundary Scan Description Language) models to use with BScan/JTAG tools

BSDL model: Tsi578

-- ***************************************************************
--      Company:  Integrated Device Technology, Inc.
--
--      Document number: 35B8030_BS001_06
--
--      Title: BSDL file of Tsi578
--      Generated by : Andi Sugandi
-- 	Modified by:   Bruno Latulippe
--
--      Release status: formal issue
--      Security level: client use
--      BSDL Version 2001
--      Group ownership: DFT         Revision Date: 
--      Released by  : 
--      Revision History:
--              Dec 17, 2005:   initial release
--              Sep 15, 2006:   update rev ID for version A1
--              Oct 18, 2006:   update rev ID for version B0
--		Jan 25, 2007:	Rename TRI_b signal to VDD_IO
--		Jul 23, 2009:	Update with IDT formatting
--		Oct 19, 2009:	Add more VSS pins, rename TCK2_P/N, DI as VSS
--     
--              
--      BSDL Syntax Checker ->  passed Oct 20, 2009
--     
--              
--           
-- ***************************************************************
--
-- Generated by boundaryScanGenerate 4.2a-Build20050202.003 on 10/18/05 10:56:27
-- BSDL Version 2001
-- The default acjt_lvl[4:0] which is controled by IRbits[29:25] is set to 2'h03, 
-- tx_lvl which is controlled by IRbits[38:34] is set to 4'h1F
-- To program acjt_lvl and tx_lvl IRbits[33] has to be set to 0
-- 

entity Tsi578 is 
    generic (PHYSICAL_PIN_MAP : string := "FCBGA_675_27");

    port (
        -- Port List
        SP0_TD_P             : out      bit;
        SP0_TD_N             : out      bit;
        SP0_RD_P             : in       bit;
        SP0_RD_N             : in       bit;
        SP0_TC_P             : out      bit;
        SP0_TC_N             : out      bit;
        SP0_RC_P             : in       bit;
        SP0_RC_N             : in       bit;
        SP0_TB_P             : out      bit;
        SP0_TB_N             : out      bit;
        SP0_RB_P             : in       bit;
        SP0_RB_N             : in       bit;
        SP0_TA_P             : out      bit;
        SP0_TA_N             : out      bit;
        SP0_RA_P             : in       bit;
        SP0_RA_N             : in       bit;
        SP0_REXT             : linkage  bit;
        SP2_TD_P             : out      bit;
        SP2_TD_N             : out      bit;
        SP2_RD_P             : in       bit;
        SP2_RD_N             : in       bit;
        SP2_TC_P             : out      bit;
        SP2_TC_N             : out      bit;
        SP2_RC_P             : in       bit;
        SP2_RC_N             : in       bit;
        SP2_TB_P             : out      bit;
        SP2_TB_N             : out      bit;
        SP2_RB_P             : in       bit;
        SP2_RB_N             : in       bit;
        SP2_TA_P             : out      bit;
        SP2_TA_N             : out      bit;
        SP2_RA_P             : in       bit;
        SP2_RA_N             : in       bit;
        SP2_REXT             : linkage  bit;
        SP4_TD_P             : out      bit;
        SP4_TD_N             : out      bit;
        SP4_RD_P             : in       bit;
        SP4_RD_N             : in       bit;
        SP4_TC_P             : out      bit;
        SP4_TC_N             : out      bit;
        SP4_RC_P             : in       bit;
        SP4_RC_N             : in       bit;
        SP4_TB_P             : out      bit;
        SP4_TB_N             : out      bit;
        SP4_RB_P             : in       bit;
        SP4_RB_N             : in       bit;
        SP4_TA_P             : out      bit;
        SP4_TA_N             : out      bit;
        SP4_RA_P             : in       bit;
        SP4_RA_N             : in       bit;
        SP4_REXT             : linkage  bit;
        SP6_TD_P             : out      bit;
        SP6_TD_N             : out      bit;
        SP6_RD_P             : in       bit;
        SP6_RD_N             : in       bit;
        SP6_TC_P             : out      bit;
        SP6_TC_N             : out      bit;
        SP6_RC_P             : in       bit;
        SP6_RC_N             : in       bit;
        SP6_TB_P             : out      bit;
        SP6_TB_N             : out      bit;
        SP6_RB_P             : in       bit;
        SP6_RB_N             : in       bit;
        SP6_TA_P             : out      bit;
        SP6_TA_N             : out      bit;
        SP6_RA_P             : in       bit;
        SP6_RA_N             : in       bit;
        SP6_REXT             : linkage  bit;
        SP8_TD_P             : out      bit;
        SP8_TD_N             : out      bit;
        SP8_RD_P             : in       bit;
        SP8_RD_N             : in       bit;
        SP8_TC_P             : out      bit;
        SP8_TC_N             : out      bit;
        SP8_RC_P             : in       bit;
        SP8_RC_N             : in       bit;
        SP8_TB_P             : out      bit;
        SP8_TB_N             : out      bit;
        SP8_RB_P             : in       bit;
        SP8_RB_N             : in       bit;
        SP8_TA_P             : out      bit;
        SP8_TA_N             : out      bit;
        SP8_RA_P             : in       bit;
        SP8_RA_N             : in       bit;
        SP8_REXT             : linkage  bit;
        SP10_TD_P            : out      bit;
        SP10_TD_N            : out      bit;
        SP10_RD_P            : in       bit;
        SP10_RD_N            : in       bit;
        SP10_TC_P            : out      bit;
        SP10_TC_N            : out      bit;
        SP10_RC_P            : in       bit;
        SP10_RC_N            : in       bit;
        SP10_TB_P            : out      bit;
        SP10_TB_N            : out      bit;
        SP10_RB_P            : in       bit;
        SP10_RB_N            : in       bit;
        SP10_TA_P            : out      bit;
        SP10_TA_N            : out      bit;
        SP10_RA_P            : in       bit;
        SP10_RA_N            : in       bit;
        SP10_REXT            : linkage  bit;
        SP12_TD_P            : out      bit;
        SP12_TD_N            : out      bit;
        SP12_RD_P            : in       bit;
        SP12_RD_N            : in       bit;
        SP12_TC_P            : out      bit;
        SP12_TC_N            : out      bit;
        SP12_RC_P            : in       bit;
        SP12_RC_N            : in       bit;
        SP12_TB_P            : out      bit;
        SP12_TB_N            : out      bit;
        SP12_RB_P            : in       bit;
        SP12_RB_N            : in       bit;
        SP12_TA_P            : out      bit;
        SP12_TA_N            : out      bit;
        SP12_RA_P            : in       bit;
        SP12_RA_N            : in       bit;
        SP12_REXT            : linkage  bit;
        SP14_TD_P            : out      bit;
        SP14_TD_N            : out      bit;
        SP14_RD_P            : in       bit;
        SP14_RD_N            : in       bit;
        SP14_TC_P            : out      bit;
        SP14_TC_N            : out      bit;
        SP14_RC_P            : in       bit;
        SP14_RC_N            : in       bit;
        SP14_TB_P            : out      bit;
        SP14_TB_N            : out      bit;
        SP14_RB_P            : in       bit;
        SP14_RB_N            : in       bit;
        SP14_TA_P            : out      bit;
        SP14_TA_N            : out      bit;
        SP14_RA_P            : in       bit;
        SP14_RA_N            : in       bit;
        SP14_REXT            : linkage  bit;
        P_CLK                : in       bit;
        S_CLK_P              : linkage  bit;
        S_CLK_N              : linkage  bit;
        I2C_SCLK             : inout    bit;
        I2C_SD               : inout    bit;
        I2C_DISABLE          : inout    bit;
        I2C_MA               : inout    bit;
        I2C_SA               : inout    bit_vector( 1 downto 0 );
        I2C_SEL              : inout    bit;
        HARD_RST_B           : linkage  bit;
        INT_B                : inout    bit;
        SW_RST_B             : inout    bit;
        SPY_CLK_0            : linkage  bit;
        SPY_CLK_1            : linkage  bit;
        TCK                  : in       bit;
        TMS                  : in       bit;
        TDI                  : in       bit;
        TDO                  : out      bit;
        TRST_B               : in       bit;
        BCE                  : in  bit;
        DO                   : out      bit;
        SP_RX_SWAP           : inout    bit;
        SP_TX_SWAP           : inout    bit;
        SP_IO_SPEED          : inout    bit_vector( 1 downto 0 );
        SP1_PWRDN            : inout    bit;
        SP2_PWRDN            : inout    bit;
        SP3_PWRDN            : inout    bit;
        SP4_PWRDN            : inout    bit;
        SP5_PWRDN            : inout    bit;
        SP6_PWRDN            : inout    bit;
        SP7_PWRDN            : inout    bit;
        SP8_PWRDN            : inout    bit;
        SP9_PWRDN            : inout    bit;
        SP10_PWRDN           : inout    bit;
        SP11_PWRDN           : inout    bit;
        SP12_PWRDN           : inout    bit;
        SP13_PWRDN           : inout    bit;
        SP14_PWRDN           : inout    bit;
        SP15_PWRDN           : inout    bit;
        SP0_MODESEL          : inout    bit;
        SP2_MODESEL          : inout    bit;
        SP4_MODESEL          : inout    bit;
        SP6_MODESEL          : inout    bit;
        SP8_MODESEL          : inout    bit;
        SP10_MODESEL         : inout    bit;
        SP12_MODESEL         : inout    bit;
        SP14_MODESEL         : inout    bit;
        MCES                 : inout    bit;
        VDD_IO               : linkage  bit_vector( 11 downto 0 );
        VSS_IO               : linkage  bit_vector( 14 downto 0 );
        VSS                  : linkage  bit_vector( 281 downto 0 );
        VDD                  : linkage  bit_vector( 49 downto 0 );
        SP_VDD               : linkage  bit_vector( 111 downto 0 );
        SP_AVDD              : linkage  bit_vector( 15 downto 0 );
        REF_AVDD             : linkage  bit_vector( 1 downto 0 ));
--        DEV_ID_SEL           : linkage  bit_vector( 1 downto 0 ));

    use STD_1149_1_2001.all;
    use STD_1149_6_2003.all;
    use LVS_BSCAN_CELLS.all;

    attribute COMPONENT_CONFORMANCE of Tsi578: entity is "STD_1149_1_2001";

    --Pin mappings

    attribute PIN_MAP of Tsi578: entity is PHYSICAL_PIN_MAP;

    constant DEFAULT_PACKAGE_NAME: PIN_MAP_STRING := 
    "SP0_TD_P             : j1   , " &
    "SP0_TD_N             : j2   , " &
    "SP0_RD_P             : j5   , " &
    "SP0_RD_N             : j4   , " &
    "SP0_TC_P             : g2   , " &
    "SP0_TC_N             : g1   , " &
    "SP0_RC_P             : g4   , " &
    "SP0_RC_N             : g5   , " &
    "SP0_TB_P             : e1   , " &
    "SP0_TB_N             : e2   , " &
    "SP0_RB_P             : e5   , " &
    "SP0_RB_N             : e4   , " &
    "SP0_TA_P             : c2   , " &
    "SP0_TA_N             : c1   , " &
    "SP0_RA_P             : c4   , " &
    "SP0_RA_N             : c5   , " &
    "SP0_REXT             : f4   , " &
    "SP2_TD_P             : af12   , " &
    "SP2_TD_N             : ae12   , " &
    "SP2_RD_P             : ab12   , " &
    "SP2_RD_N             : ac12   , " &
    "SP2_TC_P             : ae10   , " &
    "SP2_TC_N             : af10   , " &
    "SP2_RC_P             : ac10   , " &
    "SP2_RC_N             : ab10   , " &
    "SP2_TB_P             : af8   , " &
    "SP2_TB_N             : ae8   , " &
    "SP2_RB_P             : ab8   , " &
    "SP2_RB_N             : ac8   , " &
    "SP2_TA_P             : ae6   , " &
    "SP2_TA_N             : af6   , " &
    "SP2_RA_P             : ac6   , " &
    "SP2_RA_N             : ab6   , " &
    "SP2_REXT             : ac9   , " &
    "SP4_TD_P             : r26   , " &
    "SP4_TD_N             : r25   , " &
    "SP4_RD_P             : r22   , " &
    "SP4_RD_N             : r23   , " &
    "SP4_TC_P             : u25   , " &
    "SP4_TC_N             : u26   , " &
    "SP4_RC_P             : u23   , " &
    "SP4_RC_N             : u22   , " &
    "SP4_TB_P             : w26   , " &
    "SP4_TB_N             : w25   , " &
    "SP4_RB_P             : w22   , " &
    "SP4_RB_N             : w23   , " &
    "SP4_TA_P             : aa25   , " &
    "SP4_TA_N             : aa26   , " &
    "SP4_RA_P             : aa23   , " &
    "SP4_RA_N             : aa22   , " &
    "SP4_REXT             : v23   , " &
    "SP6_TD_P             : a15   , " &
    "SP6_TD_N             : b15   , " &
    "SP6_RD_P             : e15   , " &
    "SP6_RD_N             : d15   , " &
    "SP6_TC_P             : b17   , " &
    "SP6_TC_N             : a17   , " &
    "SP6_RC_P             : d17   , " &
    "SP6_RC_N             : e17   , " &
    "SP6_TB_P             : a19   , " &
    "SP6_TB_N             : b19   , " &
    "SP6_RB_P             : e19   , " &
    "SP6_RB_N             : d19   , " &
    "SP6_TA_P             : b21   , " &
    "SP6_TA_N             : a21   , " &
    "SP6_RA_P             : d21   , " &
    "SP6_RA_N             : e21   , " &
    "SP6_REXT             : d18   , " &
    "SP8_TD_P             : u1   , " &
    "SP8_TD_N             : u2   , " &
    "SP8_RD_P             : u5   , " &
    "SP8_RD_N             : u4   , " &
    "SP8_TC_P             : r2   , " &
    "SP8_TC_N             : r1   , " &
    "SP8_RC_P             : r4   , " &
    "SP8_RC_N             : r5   , " &
    "SP8_TB_P             : n1   , " &
    "SP8_TB_N             : n2   , " &
    "SP8_RB_P             : n5   , " &
    "SP8_RB_N             : n4   , " &
    "SP8_TA_P             : l2   , " &
    "SP8_TA_N             : l1   , " &
    "SP8_RA_P             : l4   , " &
    "SP8_RA_N             : l5   , " &
    "SP8_REXT             : p4   , " &
    "SP10_TD_P            : af20   , " &
    "SP10_TD_N            : ae20   , " &
    "SP10_RD_P            : ab20  , " &
    "SP10_RD_N            : ac20  , " &
    "SP10_TC_P            : ae18   , " &
    "SP10_TC_N            : af18   , " &
    "SP10_RC_P            : ac18   , " &
    "SP10_RC_N            : ab18   , " &
    "SP10_TB_P            : af16   , " &
    "SP10_TB_N            : ae16   , " &
    "SP10_RB_P            : ab16   , " &
    "SP10_RB_N            : ac16   , " &
    "SP10_TA_P            : ae14   , " &
    "SP10_TA_N            : af14   , " &
    "SP10_RA_P            : ac14   , " &
    "SP10_RA_N            : ab14   , " &
    "SP10_REXT            : ac17  , " &
    "SP12_TD_P            : g26  , " &
    "SP12_TD_N            : g25  , " &
    "SP12_RD_P            : g22  , " &
    "SP12_RD_N            : g23  , " &
    "SP12_TC_P            : j25  , " &
    "SP12_TC_N            : j26  , " &
    "SP12_RC_P            : j23  , " &
    "SP12_RC_N            : j22  , " &
    "SP12_TB_P            : l26  , " &
    "SP12_TB_N            : l25  , " &
    "SP12_RB_P            : l22  , " &
    "SP12_RB_N            : l23  , " &
    "SP12_TA_P            : n25  , " &
    "SP12_TA_N            : n26  , " &
    "SP12_RA_P            : n23  , " &
    "SP12_RA_N            : n22  , " &
    "SP12_REXT            : k23  , " &
    "SP14_TD_P            : a7  , " &
    "SP14_TD_N            : b7  , " &
    "SP14_RD_P            : e7  , " &
    "SP14_RD_N            : d7  , " &
    "SP14_TC_P            : b9  , " &
    "SP14_TC_N            : a9  , " &
    "SP14_RC_P            : d9  , " &
    "SP14_RC_N            : e9  , " &
    "SP14_TB_P            : a11  , " &
    "SP14_TB_N            : b11  , " &
    "SP14_RB_P            : e11  , " &
    "SP14_RB_N            : d11  , " &
    "SP14_TA_P            : b13  , " &
    "SP14_TA_N            : a13  , " &
    "SP14_RA_P            : d13  , " &
    "SP14_RA_N            : e13  , " &
    "SP14_REXT            : d10  , " &
    "P_CLK                : af1  , " &
    "S_CLK_P              : b24  , " &
    "S_CLK_N              : b25  , " &
    "I2C_SCLK             : af25  , " &
    "I2C_SD               : ae24  , " &
    "I2C_DISABLE          : ac24  , " &
    "I2C_MA               : ae22  , " &
    "I2C_SA               :(u19  , " &  -- I2C_SA[1]
                           "t19 ), " &  -- I2C_SA[0]
    "I2C_SEL              : w20  , " &
    "HARD_RST_B           : af2  , " &
    "INT_B                : ac2  , " &
    "SW_RST_B             : ad3  , " &
    "SPY_CLK_0            : ad1  , " &
    "SPY_CLK_1            : ad4  , " &
    "TCK                  : af26  , " &
    "TMS                  : ac26  , " &
    "TDI                  : ad26  , " &
    "TDO                  : ad25  , " &
    "TRST_B               : ae26  , " &
    "BCE                  : v19  , " &
    "DO                   : ae2  , " &
    "SP_RX_SWAP           : y19  , " &
    "SP_TX_SWAP           : y20  , " &
    "SP_IO_SPEED          :(ac23  , " &  -- SP_IO_SPEED[1]
                           "ac22 ), " &  -- SP_IO_SPEED[0]
    "SP1_PWRDN            : af22  , " &
    "SP2_PWRDN            : ae23  , " &
    "SP3_PWRDN            : af23  , " &
    "SP4_PWRDN            : w2  , " &
    "SP5_PWRDN            : w3  , " &
    "SP6_PWRDN            : w5  , " &
    "SP7_PWRDN            : w6  , " &
    "SP8_PWRDN            : y1  , " &
    "SP9_PWRDN            : y3  , " &
    "SP10_PWRDN           : y4  , " &
    "SP11_PWRDN           : y6  , " &
    "SP12_PWRDN           : aa2  , " &
    "SP13_PWRDN           : aa3  , " &
    "SP14_PWRDN           : w7  , " &
    "SP15_PWRDN           : y8  , " &
    "SP0_MODESEL          : ad22  , " &
    "SP2_MODESEL          : ad23  , " &
    "SP4_MODESEL          : ab1  , " &
    "SP6_MODESEL          : ab3  , " &
    "SP8_MODESEL          : ab4  , " &
    "SP10_MODESEL         : ac3  , " &
    "SP12_MODESEL         : af3  , " &
    "SP14_MODESEL         : af4  , " &
    "MCES                 : ad24  , " &
    "VDD_IO               :(aa4  , " &  -- VDD_IO[11]
                           "v2  , " &  -- VDD_IO[10]
                           "v6  , " &  -- VDD_IO[9]
                           "w4  , " &  -- VDD_IO[8]
                           "y2  , " &  -- VDD_IO[7]
                           "y7  , " &  -- VDD_IO[6]
                           "ab2  , " &  -- VDD_IO[5]
                           "ac4  , " &  -- VDD_IO[4]
                           "ad2  , " &  -- VDD_IO[3]
                           "ae4  , " &  -- VDD_IO[2]
                           "ac25  , " &  -- VDD_IO[1]
                           "ae25 ), " &  -- VDD_IO[0]
    "VSS_IO               :(v3  , " &  -- VSS_IO[14]
                           "v5  , " &  -- VSS_IO[13]
                           "w1  , " &  -- VSS_IO[12]
                           "w8  , " &  -- VSS_IO[11]
                           "w19  , " &  -- VSS_IO[10]
                           "Y5  , " &  -- VSS_IO[9]
                           "ae1  , " &  -- VSS_IO[8]
                           "y18  , " &  -- VSS_IO[7]
                           "aa1  , " &  -- VSS_IO[6]
                           "ab5  , " &  -- VSS_IO[5]
                           "ac1  , " &  -- VSS_IO[4]
                           "ad5  , " &  -- VSS_IO[3]
                           "ad21  , " &  -- VSS_IO[2]
                           "af21  , " &  -- VSS_IO[1]
                           "af24 ), " &  -- VSS_IO[0]
    "VSS               :(d26  , " &  -- VSS[281]
                           "af5  , " &  -- VSS[280]
                           "ae21  , " &  -- VSS[279]
                           "ae3  , " &  -- VSS[278] -- DI
                           "ac21  , " &  -- VSS[277] 
                           "ab26  , " &  -- VSS[276] 
                           "y16  , " &  -- VSS[275] 
                           "y14  , " &  -- VSS[274] 
                           "y12  , " &  -- VSS[273] 
                           "y10  , " &  -- VSS[272] 
                           "w18  , " &  -- VSS[271] 
                           "w17  , " &  -- VSS[270] 
                           "w16  , " &  -- VSS[269] 
                           "w15  , " &  -- VSS[268] 
                           "w14  , " &  -- VSS[267] 
                           "w13  , " &  -- VSS[266] 
                           "w12  , " &  -- VSS[265] 
                           "w11  , " &  -- VSS[264] 
                           "w10  , " &  -- VSS[263] 
                           "w9  , " &  -- VSS[262] 
                           "v18  , " &  -- VSS[261] 
                           "v16  , " &  -- VSS[260] 
                           "v14  , " &  -- VSS[259] 
                           "v12  , " &  -- VSS[258] 
                           "v10  , " &  -- VSS[257] 
                           "v8  , " &  -- VSS[256] 
                           "v4  , " &  -- VSS[255] 
                           "v1  , " &  -- VSS[254] 
                           "u20  , " &  -- VSS[253] 
                           "u17  , " &  -- VSS[252] 
                           "u15  , " &  -- VSS[251] 
                           "u13  , " &  -- VSS[250] 
                           "u11  , " &  -- VSS[249] 
                           "u9  , " &  -- VSS[248] 
                           "u8  , " &  -- VSS[247] 
                           "u7  , " &  -- VSS[246] 
                           "t18  , " &  -- VSS[245] 
                           "t16  , " &  -- VSS[244] 
                           "t14  , " &  -- VSS[243] 
                           "t12  , " &  -- VSS[242] 
                           "t10  , " &  -- VSS[241] 
                           "t8  , " &  -- VSS[240] 
                           "r20  , " &  -- VSS[239] 
                           "r19  , " &  -- VSS[238] 
                           "r17  , " &  -- VSS[237] 
                           "r15  , " &  -- VSS[236] 
                           "r13  , " &  -- VSS[235] 
                           "r11  , " &  -- VSS[234] 
                           "r9  , " &  -- VSS[233] 
                           "r8  , " &  -- VSS[232] 
                           "r7  , " &  -- VSS[231] 
                           "p19  , " &  -- VSS[230] 
                           "p18  , " &  -- VSS[229] 
                           "p16  , " &  -- VSS[228] 
                           "p14  , " &  -- VSS[227] 
                           "p12  , " &  -- VSS[226] 
                           "p10  , " &  -- VSS[225] 
                           "p8  , " &  -- VSS[224] 
                           "n20  , " &  -- VSS[223] 
                           "n19  , " &  -- VSS[222] 
                           "n17  , " &  -- VSS[221] 
                           "n15  , " &  -- VSS[220] 
                           "n13  , " &  -- VSS[219] 
                           "n11  , " &  -- VSS[218] 
                           "n9  , " &  -- VSS[217] 
                           "n8  , " &  -- VSS[216] 
                           "n7  , " &  -- VSS[215] 
                           "m19  , " &  -- VSS[214] 
                           "m18  , " &  -- VSS[213] 
                           "m16  , " &  -- VSS[212] 
                           "m14  , " &  -- VSS[211] 
                           "m12  , " &  -- VSS[210] 
                           "m10  , " &  -- VSS[209] 
                           "m8  , " &  -- VSS[208] 
                           "l20  , " &  -- VSS[207] 
                           "l19  , " &  -- VSS[206] 
                           "l17  , " &  -- VSS[205] 
                           "l15  , " &  -- VSS[204] 
                           "l13  , " &  -- VSS[203] 
                           "l11  , " &  -- VSS[202] 
                           "l9  , " &  -- VSS[201] 
                           "l8  , " &  -- VSS[200] 
                           "l7  , " &  -- VSS[199] 
                           "k19  , " &  -- VSS[198] 
                           "k18  , " &  -- VSS[197] 
                           "k16  , " &  -- VSS[196] 
                           "k14  , " &  -- VSS[195] 
                           "k12  , " &  -- VSS[194] 
                           "k10  , " &  -- VSS[193] 
                           "k8  , " &  -- VSS[192] 
                           "j20  , " &  -- VSS[191] 
                           "j19  , " &  -- VSS[190] 
                           "j17  , " &  -- VSS[189] 
                           "j15  , " &  -- VSS[188] 
                           "j13  , " &  -- VSS[187] 
                           "j11  , " &  -- VSS[186] 
                           "j9  , " &  -- VSS[185] 
                           "j8  , " &  -- VSS[184] 
                           "j7  , " &  -- VSS[183] 
                           "h19  , " &  -- VSS[182] 
                           "h18  , " &  -- VSS[181] 
                           "h17  , " &  -- VSS[180] 
                           "h16  , " &  -- VSS[179] 
                           "h15  , " &  -- VSS[178] 
                           "h14  , " &  -- VSS[177] 
                           "h13  , " &  -- VSS[176] 
                           "h12  , " &  -- VSS[175] 
                           "h11  , " &  -- VSS[174] 
                           "h10  , " &  -- VSS[173] 
                           "h9  , " &  -- VSS[172] 
                           "h8  , " &  -- VSS[171] 
                           "g19  , " &  -- VSS[170] 
                           "g17  , " &  -- VSS[169] 
                           "g15  , " &  -- VSS[168] 
                           "g13  , " &  -- VSS[167] 
                           "g11  , " &  -- VSS[166] 
                           "g9  , " &  -- VSS[165] 
                           "g7  , " &  -- VSS[164] 
                           "f26  , " &  -- VSS[163] 
                           "f25  , " &  -- VSS[162] 
                           "f24  , " &  -- VSS[161] 
                           "f23  , " &  -- VSS[160] 
                           "a4  , " &  -- VSS[159] 
                           "e26  , " &  -- VSS[158] 
                           "e25  , " &  -- VSS[157] 
                           "e24  , " &  -- VSS[156] 
                           "e23  , " &  -- VSS[155] 
                           "d25  , " &  -- VSS[154] -- TCK2_N
                           "d24  , " &  -- VSS[153] -- TCK2_P
                           "c25  , " &  -- VSS[152]
                           "c23  , " &  -- VSS[151]
                           "b26  , " &  -- VSS[150]
                           "b23  , " &  -- VSS[149]
                           "a26  , " &  -- VSS[148]
                           "a25  , " &  -- VSS[147]
                           "a24  , " &  -- VSS[146]
                           "a23  , " &  -- VSS[145]
                           "a6  , " &  -- VSS[144]
                           "a5  , " &  -- VSS[143]
                           "d23  , " &  -- VSS[142]
                           "f8  , " &  -- VSS[141]
                           "f10  , " &  -- VSS[140]
                           "f12  , " &  -- VSS[139]
                           "f14  , " &  -- VSS[138]
                           "d8  , " &  -- VSS[137]
                           "d12  , " &  -- VSS[136]
                           "b12  , " &  -- VSS[135]
                           "e14  , " &  -- VSS[134]
                           "d14  , " &  -- VSS[133]
                           "c14  , " &  -- VSS[132]
                           "a8  , " &  -- VSS[131]
                           "c8  , " &  -- VSS[130]
                           "b8  , " &  -- VSS[129]
                           "c10  , " &  -- VSS[128]
                           "a10  , " &  -- VSS[127]
                           "c12  , " &  -- VSS[126]
                           "a12  , " &  -- VSS[125]
                           "a14  , " &  -- VSS[124]
                           "h21  , " &  -- VSS[123]
                           "k21  , " &  -- VSS[122]
                           "m21  , " &  -- VSS[121]
                           "p21  , " &  -- VSS[120]
                           "h23  , " &  -- VSS[119]
                           "m23  , " &  -- VSS[118]
                           "m25  , " &  -- VSS[117]
                           "p22  , " &  -- VSS[116]
                           "p23  , " &  -- VSS[115]
                           "p24  , " &  -- VSS[114]
                           "h26  , " &  -- VSS[113]
                           "h24  , " &  -- VSS[112]
                           "h25  , " &  -- VSS[111]
                           "k24  , " &  -- VSS[110]
                           "k26  , " &  -- VSS[109]
                           "m24  , " &  -- VSS[108]
                           "m26  , " &  -- VSS[107]
                           "p26  , " &  -- VSS[106]
                           "aa19  , " &  -- VSS[105]
                           "aa17  , " &  -- VSS[104]
                           "aa15  , " &  -- VSS[103]
                           "aa13  , " &  -- VSS[102]
                           "ac19  , " &  -- VSS[101]
                           "ac15  , " &  -- VSS[100]
                           "ae15  , " &  -- VSS[99]
                           "ab13  , " &  -- VSS[98]
                           "ac13  , " &  -- VSS[97]
                           "ad13  , " &  -- VSS[96]
                           "af19  , " &  -- VSS[95]
                           "ad19  , " &  -- VSS[94]
                           "ae19  , " &  -- VSS[93]
                           "ad17  , " &  -- VSS[92]
                           "af17  , " &  -- VSS[91]
                           "ad15  , " &  -- VSS[90]
                           "af15  , " &  -- VSS[89]
                           "af13  , " &  -- VSS[88]
                           "t6  , " &  -- VSS[87]
                           "p6  , " &  -- VSS[86]
                           "m6  , " &  -- VSS[85]
                           "k6  , " &  -- VSS[84]
                           "t4  , " &  -- VSS[83]
                           "m4  , " &  -- VSS[82]
                           "m2  , " &  -- VSS[81]
                           "k5  , " &  -- VSS[80]
                           "k4  , " &  -- VSS[79]
                           "k3  , " &  -- VSS[78]
                           "t1  , " &  -- VSS[77]
                           "t3  , " &  -- VSS[76]
                           "t2  , " &  -- VSS[75]
                           "p3  , " &  -- VSS[74]
                           "p1  , " &  -- VSS[73]
                           "m3  , " &  -- VSS[72]
                           "m1  , " &  -- VSS[71]
                           "k1  , " &  -- VSS[70]
                           "f16  , " &  -- VSS[69]
                           "f18  , " &  -- VSS[68]
                           "f20  , " &  -- VSS[67]
                           "f22  , " &  -- VSS[66]
                           "d16  , " &  -- VSS[65]
                           "d20  , " &  -- VSS[64]
                           "b20  , " &  -- VSS[63]
                           "e22  , " &  -- VSS[62]
                           "d22  , " &  -- VSS[61]
                           "c22  , " &  -- VSS[60]
                           "a16  , " &  -- VSS[59]
                           "c16  , " &  -- VSS[58]
                           "b16  , " &  -- VSS[57]
                           "c18  , " &  -- VSS[56]
                           "a18  , " &  -- VSS[55]
                           "c20  , " &  -- VSS[54]
                           "a20  , " &  -- VSS[53]
                           "a22  , " &  -- VSS[52]
                           "t21 , " &  -- VSS[51]
                           "v21 , " &  -- VSS[50]
                           "y21 , " &  -- VSS[49]
                           "ab21 , " &  -- VSS[48]
                           "t23 , " &  -- VSS[47]
                           "y23 , " &  -- VSS[46]
                           "y25 , " &  -- VSS[45]
                           "ab22 , " &  -- VSS[44]
                           "ab23 , " &  -- VSS[43]
                           "ab24 , " &  -- VSS[42]
                           "t26 , " &  -- VSS[41]
                           "t24 , " &  -- VSS[40]
                           "t25 , " &  -- VSS[39]
                           "v24 , " &  -- VSS[38]
                           "v26 , " &  -- VSS[37]
                           "y24 , " &  -- VSS[36]
                           "y26 , " &  -- VSS[35]
                           "aa11 , " &  -- VSS[34]
                           "aa9 , " &  -- VSS[33]
                           "aa7 , " &  -- VSS[32]
                           "aa5 , " &  -- VSS[31]
                           "ac11 , " &  -- VSS[30]
                           "ac7 , " &  -- VSS[29]
                           "ae7 , " &  -- VSS[28]
                           "a2 , " &  -- VSS[27]
                           "ac5 , " &  -- VSS[26]
                           "a3 , " &  -- VSS[25]
                           "af11 , " &  -- VSS[24]
                           "ad11 , " &  -- VSS[23]
                           "ae11 , " &  -- VSS[22]
                           "ad9 , " &  -- VSS[21]
                           "af9 , " &  -- VSS[20]
                           "ad7 , " &  -- VSS[19]
                           "af7 , " &  -- VSS[18]
                           "h6 , " &  -- VSS[17]
                           "f6 , " &  -- VSS[16]
                           "d6 , " &  -- VSS[15]
                           "b6 , " &  -- VSS[14]
                           "h4 , " &  -- VSS[13]
                           "d4 , " &  -- VSS[12]
                           "d2 , " &  -- VSS[11]
                           "b5 , " &  -- VSS[10]
                           "b4 , " &  -- VSS[9]
                           "b3 , " &  -- VSS[8]
                           "h1 , " &  -- VSS[7]
                           "h3 , " &  -- VSS[6]
                           "h2 , " &  -- VSS[5]
                           "f3 , " &  -- VSS[4]
                           "f1 , " &  -- VSS[3]
                           "d3 , " &  -- VSS[2]
                           "d1 , " &  -- VSS[1]
                           "b1 ), " &  -- VSS[0]
    "VDD               	:(v9  , " &  -- VDD[49]
                           "v17  , " &  -- VDD[48]
                           "v15  , " &  -- VDD[47]
                           "v13  , " &  -- VDD[46]
                           "v11  , " &  -- VDD[45]
                           "u18  , " &  -- VDD[44]
                           "u16  , " &  -- VDD[43]
                           "u14  , " &  -- VDD[42]
                           "u12  , " &  -- VDD[41]
                           "u10  , " &  -- VDD[40]
                           "t9  , " &  -- VDD[39]
                           "t17  , " &  -- VDD[38]
                           "t15  , " &  -- VDD[37]
                           "t13  , " &  -- VDD[36]
                           "t11  , " &  -- VDD[35]
                           "r18  , " &  -- VDD[34]
                           "r16  , " &  -- VDD[33]
                           "r14  , " &  -- VDD[32]
                           "r12  , " &  -- VDD[31]
                           "r10  , " &  -- VDD[30]
                           "p9  , " &  -- VDD[29]
                           "p17  , " &  -- VDD[28]
                           "p15  , " &  -- VDD[27]
                           "p13  , " &  -- VDD[26]
                           "p11  , " &  -- VDD[25]
                           "n18  , " &  -- VDD[24]
                           "n16  , " &  -- VDD[23]
                           "n14  , " &  -- VDD[22]
                           "n12  , " &  -- VDD[21]
                           "n10  , " &  -- VDD[20]
                           "m9  , " &  -- VDD[19]
                           "m17  , " &  -- VDD[18]
                           "m15  , " &  -- VDD[17]
                           "m13  , " &  -- VDD[16]
                           "m11  , " &  -- VDD[15]
                           "l18  , " &  -- VDD[14]
                           "l16  , " &  -- VDD[13]
                           "l14  , " &  -- VDD[12]
                           "l12  , " &  -- VDD[11]
                           "l10  , " &  -- VDD[10]
                           "k9  , " &  -- VDD[9]
                           "k17  , " &  -- VDD[8]
                           "k15  , " &  -- VDD[7]
                           "k13  , " &  -- VDD[6]
                           "k11  , " &  -- VDD[5]
                           "j18  , " &  -- VDD[4]
                           "j16  , " &  -- VDD[3]
                           "j14  , " &  -- VDD[2]
                           "j12  , " &  -- VDD[1]
                           "j10 ), " &  -- VDD[0]

    "SP_VDD               	:(ae17  , " &  -- SP_VDD[111]
                           "ae13  , " &  -- SP_VDD[110]
                           "ae9  , " &  -- SP_VDD[109]
                           "ae5  , " &  -- SP_VDD[108]
                           "ad20  , " &  -- SP_VDD[107]
                           "ad18  , " &  -- SP_VDD[106]
                           "ad16  , " &  -- SP_VDD[105]
                           "ad14  , " &  -- SP_VDD[104]
                           "ad12  , " &  -- SP_VDD[103]
                           "ad10  , " &  -- SP_VDD[102]
                           "ad8  , " &  -- SP_VDD[101]
                           "ad6  , " &  -- SP_VDD[100]
                           "ab25  , " &  -- SP_VDD[99]
                           "ab15  , " &  -- SP_VDD[98]
                           "ab7  , " &  -- SP_VDD[97]
                           "aa24  , " &  -- SP_VDD[96]
                           "aa21  , " &  -- SP_VDD[95]
                           "aa20  , " &  -- SP_VDD[94]
                           "aa18  , " &  -- SP_VDD[93]
                           "aa16  , " &  -- SP_VDD[92]
                           "aa14  , " &  -- SP_VDD[91]
                           "aa12  , " &  -- SP_VDD[90]
                           "aa10  , " &  -- SP_VDD[89]
                           "aa8  , " &  -- SP_VDD[88]
                           "aa6  , " &  -- SP_VDD[87]
                           "y22  , " &  -- SP_VDD[86]
                           "y17  , " &  -- SP_VDD[85]
                           "y15  , " &  -- SP_VDD[84]
                           "y13  , " &  -- SP_VDD[83]
                           "y11  , " &  -- SP_VDD[82]
                           "y9  , " &  -- SP_VDD[81]
                           "w24  , " &  -- SP_VDD[80]
                           "w21  , " &  -- SP_VDD[79]
                           "v25  , " &  -- SP_VDD[78]
                           "v20  , " &  -- SP_VDD[77]
                           "v7  , " &  -- SP_VDD[76]
                           "u24  , " &  -- SP_VDD[75]
                           "u21  , " &  -- SP_VDD[74]
                           "u6  , " &  -- SP_VDD[73]
                           "u3  , " &  -- SP_VDD[72]
                           "t20  , " &  -- SP_VDD[71]
                           "t7  , " &  -- SP_VDD[70]
                           "r24  , " &  -- SP_VDD[69]
                           "r21  , " &  -- SP_VDD[68]
                           "r6  , " &  -- SP_VDD[67]
                           "r3  , " &  -- SP_VDD[66]
                           "p25  , " &  -- SP_VDD[65]
                           "p20  , " &  -- SP_VDD[64]
                           "p7  , " &  -- SP_VDD[63]
                           "p2  , " &  -- SP_VDD[62]
                           "n24  , " &  -- SP_VDD[61]
                           "n21  , " &  -- SP_VDD[60]
                           "n6  , " &  -- SP_VDD[59]
                           "n3  , " &  -- SP_VDD[58]
                           "m22  , " &  -- SP_VDD[57]
                           "m20  , " &  -- SP_VDD[56]
                           "m7  , " &  -- SP_VDD[55]
                           "m5  , " &  -- SP_VDD[54]
                           "l24  , " &  -- SP_VDD[53]
                           "l21  , " &  -- SP_VDD[52]
                           "l6  , " &  -- SP_VDD[51]
                           "l3  , " &  -- SP_VDD[50]
                           "k25  , " &  -- SP_VDD[49]
                           "k20  , " &  -- SP_VDD[48]
                           "k7  , " &  -- SP_VDD[47]
                           "k2  , " &  -- SP_VDD[46]
                           "j24  , " &  -- SP_VDD[45]
                           "j21  , " &  -- SP_VDD[44]
                           "j6  , " &  -- SP_VDD[43]
                           "j3  , " &  -- SP_VDD[42]
                           "h20  , " &  -- SP_VDD[41]
                           "h7  , " &  -- SP_VDD[40]
                           "g24  , " &  -- SP_VDD[39]
                           "g21  , " &  -- SP_VDD[38]
                           "g20  , " &  -- SP_VDD[37]
                           "g18  , " &  -- SP_VDD[36]
                           "g16  , " &  -- SP_VDD[35]
                           "g14  , " &  -- SP_VDD[34]
                           "g12  , " &  -- SP_VDD[33]
                           "g10  , " &  -- SP_VDD[32]
                           "g8  , " &  -- SP_VDD[31]
                           "g6  , " &  -- SP_VDD[30]
                           "g3  , " &  -- SP_VDD[29]
                           "f21  , " &  -- SP_VDD[28]
                           "f19  , " &  -- SP_VDD[27]
                           "f17  , " &  -- SP_VDD[26]
                           "f15  , " &  -- SP_VDD[25]
                           "f13  , " &  -- SP_VDD[24]
                           "f11  , " &  -- SP_VDD[23]
                           "f9  , " &  -- SP_VDD[22]
                           "f7  , " &  -- SP_VDD[21]
                           "f2  , " &  -- SP_VDD[20]
                           "e20  , " &  -- SP_VDD[19]
                           "e12  , " &  -- SP_VDD[18]
                           "e6  , " &  -- SP_VDD[17]
                           "e3  , " &  -- SP_VDD[16]
                           "d5  , " &  -- SP_VDD[15]
                           "c21  , " &  -- SP_VDD[14]
                           "c19  , " &  -- SP_VDD[13]
                           "c17  , " &  -- SP_VDD[12]
                           "c15  , " &  -- SP_VDD[11]
                           "c13  , " &  -- SP_VDD[10]
                           "c11  , " &  -- SP_VDD[9]
                           "c9  , " &  -- SP_VDD[8]
                           "c7  , " &  -- SP_VDD[7]
                           "c6  , " &  -- SP_VDD[6]
                           "c3  , " &  -- SP_VDD[5]
                           "b22  , " &  -- SP_VDD[4]
                           "b18  , " &  -- SP_VDD[3]
                           "b14  , " &  -- SP_VDD[2]
                           "b10  , " &  -- SP_VDD[1]
                           "b2 ), " &  -- SP_VDD[0]

    "SP_AVDD               	:(ab19  , " &  -- SP_AVDD[15]
                           "ab17  , " &  -- SP_AVDD[14]
                           "ab11  , " &  -- SP_AVDD[13]
                           "ab9  , " &  -- SP_AVDD[12]
                           "v22  , " &  -- SP_AVDD[11]
                           "t22  , " &  -- SP_AVDD[10]
                           "t5  , " &  -- SP_AVDD[9]
                           "p5  , " &  -- SP_AVDD[8]
                           "k22  , " &  -- SP_AVDD[7]
                           "h22  , " &  -- SP_AVDD[6]
                           "h5  , " &  -- SP_AVDD[5]
                           "f5  , " &  -- SP_AVDD[4]
                           "e18  , " &  -- SP_AVDD[3]
                           "e16  , " &  -- SP_AVDD[2]
                           "e10  , " &  -- SP_AVDD[1]
                           "e8 ), " &  -- SP_AVDD[0]
    "REF_AVDD             :(c26  , " &  -- REF_AVDD[1]
                           "c24 )  " ;  -- REF_AVDD[0]

--    "DEV_ID_SEL           :(190  , " &  -- DEV_ID_SEL[1]
--                           "191 )  " ;  -- DEV_ID_SEL[0]

    attribute PORT_GROUPING of Tsi578 : entity is 
        "Differential_Current ( (SP0_TB_P, SP0_TB_N), " &
                                "(SP0_RB_P, SP0_RB_N), " &
                                "(SP0_TA_P, SP0_TA_N), " &
                                "(SP0_RA_P, SP0_RA_N), " &
                                "(SP0_TC_P, SP0_TC_N), " &
                                "(SP0_RC_P, SP0_RC_N), " &
                                "(SP0_TD_P, SP0_TD_N), " &
                                "(SP0_RD_P, SP0_RD_N), " &
                                "(SP2_TB_P, SP2_TB_N), " &
                                "(SP2_RB_P, SP2_RB_N), " &
                                "(SP2_TA_P, SP2_TA_N), " &
                                "(SP2_RA_P, SP2_RA_N), " &
                                "(SP2_TC_P, SP2_TC_N), " &
                                "(SP2_RC_P, SP2_RC_N), " &
                                "(SP2_TD_P, SP2_TD_N), " &
                                "(SP2_RD_P, SP2_RD_N), " &
                                "(SP4_TB_P, SP4_TB_N), " &
                                "(SP4_RB_P, SP4_RB_N), " &
                                "(SP4_TA_P, SP4_TA_N), " &
                                "(SP4_RA_P, SP4_RA_N), " &
                                "(SP4_TC_P, SP4_TC_N), " &
                                "(SP4_RC_P, SP4_RC_N), " &
                                "(SP4_TD_P, SP4_TD_N), " &
                                "(SP4_RD_P, SP4_RD_N), " &
                                "(SP6_TB_P, SP6_TB_N), " &
                                "(SP6_RB_P, SP6_RB_N), " &
                                "(SP6_TA_P, SP6_TA_N), " &
                                "(SP6_RA_P, SP6_RA_N), " &
                                "(SP6_TC_P, SP6_TC_N), " &
                                "(SP6_RC_P, SP6_RC_N), " &
                                "(SP6_TD_P, SP6_TD_N), " &
                                "(SP6_RD_P, SP6_RD_N), " &
                                "(SP8_TB_P, SP8_TB_N), " &
                                "(SP8_RB_P, SP8_RB_N), " &
                                "(SP8_TA_P, SP8_TA_N), " &
                                "(SP8_RA_P, SP8_RA_N), " &
                                "(SP8_TC_P, SP8_TC_N), " &
                                "(SP8_RC_P, SP8_RC_N), " &
                                "(SP8_TD_P, SP8_TD_N), " &
                                "(SP8_RD_P, SP8_RD_N), " &
                                "(SP10_TB_P, SP10_TB_N), " &
                                "(SP10_RB_P, SP10_RB_N), " &
                                "(SP10_TA_P, SP10_TA_N), " &
                                "(SP10_RA_P, SP10_RA_N), " &
                                "(SP10_TC_P, SP10_TC_N), " &
                                "(SP10_RC_P, SP10_RC_N), " &
                                "(SP10_TD_P, SP10_TD_N), " &
                                "(SP10_RD_P, SP10_RD_N), " &
                                "(SP12_TB_P, SP12_TB_N), " &
                                "(SP12_RB_P, SP12_RB_N), " &
                                "(SP12_TA_P, SP12_TA_N), " &
                                "(SP12_RA_P, SP12_RA_N), " &
                                "(SP12_TC_P, SP12_TC_N), " &
                                "(SP12_RC_P, SP12_RC_N), " &
                                "(SP12_TD_P, SP12_TD_N), " &
                                "(SP12_RD_P, SP12_RD_N), " &
                                "(SP14_TB_P, SP14_TB_N), " &
                                "(SP14_RB_P, SP14_RB_N), " &
                                "(SP14_TA_P, SP14_TA_N), " &
                                "(SP14_RA_P, SP14_RA_N), " &
                                "(SP14_TC_P, SP14_TC_N), " &
                                "(SP14_RC_P, SP14_RC_N), " &
                                "(SP14_TD_P, SP14_TD_N), " &
                                "(SP14_RD_P, SP14_RD_N)) " ;
 
 
 
   attribute TAP_SCAN_RESET of TRST_B                       : signal is true;
   attribute TAP_SCAN_IN    of TDI                          : signal is true;
   attribute TAP_SCAN_MODE  of TMS                          : signal is true;
   attribute TAP_SCAN_OUT   of TDO                          : signal is true;
   attribute TAP_SCAN_CLOCK of TCK                          : signal is (1.0000000000000000000e+07, BOTH);

 
   attribute COMPLIANCE_PATTERNS of Tsi578 : entity is
	"(BCE ) (1)"; 

   attribute INSTRUCTION_LENGTH of Tsi578: entity is 61;
 
   attribute INSTRUCTION_OPCODE of Tsi578: entity is
      "IDCODE       (1111111111111111111111111111111111111111111111111111111111110)," &
      "BYPASS       (0000000000000000000000000000000000000000000000000000000000000, 1111111111111111111111111111111111111111111111111111111111111)," &
      "EXTEST       (1111111111111111111111000000111111001111111111111111111101000)," &
      "EXTEST_PULSE (1111111111111111111111000000111111001111111101111111111101000)," &
      "EXTEST_TRAIN (1111111111111111111111000000111111001111111011111111111101000)," &
      "SAMPLE       (1111111111111111111111000000111111001111111111111111111111000)," &
      "PRELOAD      (1111111111111111111111000000111111001111111111111111111111000)," &
      "CLAMP        (1111111111111111111111000000111111001111111111111111111101111) " ;
 
   attribute INSTRUCTION_CAPTURE of Tsi578: entity is "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx01";
 
   attribute IDCODE_REGISTER of Tsi578: entity is
      "0010"             & -- version
      "0000010101110011" & -- part number
      "00010110011"      & -- manufacturer's identity
      "1";                   -- required by 1149.1
 
   attribute REGISTER_ACCESS of Tsi578: entity is
      "BOUNDARY     ( EXTEST_PULSE, EXTEST_TRAIN )," &
      "BOUNDARY     ( SAMPLE, PRELOAD )," &
      "BYPASS       (  CLAMP, BYPASS ) " ;


    --Boundary scan definition
    attribute BOUNDARY_LENGTH of Tsi578: entity is 183;

    attribute BOUNDARY_REGISTER of Tsi578: entity is 
    -- num  cell         port               function       safe     [ccell disval  rslt]
    "  182  (BC_1       , *                , control      , 0   )                          ,"&
    "  181  (AC_1       , SP0_TB_P         , output3      , X    ,   182    , 0     , Z   ),"&
    "  180  (BC_4       , SP0_RB_P         , observe_only , X   )                          ,"&
    "  179  (BC_4       , SP0_RB_N         , observe_only , X   )                          ,"&
    "  178  (BC_1       , *                , control      , 0   )                          ,"&
    "  177  (AC_1       , SP0_TA_P         , output3      , X    ,   178    , 0     , Z   ),"&
    "  176  (BC_4       , SP0_RA_P         , observe_only , X   )                          ,"&
    "  175  (BC_4       , SP0_RA_N         , observe_only , X   )                          ,"&
    "  174  (BC_1       , *                , control      , 0   )                          ,"&
    "  173  (AC_1       , SP0_TC_P         , output3      , X    ,   174    , 0     , Z   ),"&
    "  172  (BC_4       , SP0_RC_P         , observe_only , X   )                          ,"&
    "  171  (BC_4       , SP0_RC_N         , observe_only , X   )                          ,"&
    "  170  (BC_1       , *                , control      , 0   )                          ,"&
    "  169  (AC_1       , SP0_TD_P         , output3      , X    ,   170    , 0     , Z   ),"&
    "  168  (BC_4       , SP0_RD_P         , observe_only , X   )                          ,"&
    "  167  (BC_4       , SP0_RD_N         , observe_only , X   )                          ,"&
    "  166  (BC_1       , *                , control      , 0   )                          ,"&
    "  165  (AC_1       , SP2_TB_P         , output3      , X    ,   166    , 0     , Z   ),"&
    "  164  (BC_4       , SP2_RB_P         , observe_only , X   )                          ,"&
    "  163  (BC_4       , SP2_RB_N         , observe_only , X   )                          ,"&
    "  162  (BC_1       , *                , control      , 0   )                          ,"&
    "  161  (AC_1       , SP2_TA_P         , output3      , X    ,   162    , 0     , Z   ),"&
    "  160  (BC_4       , SP2_RA_P         , observe_only , X   )                          ,"&
    "  159  (BC_4       , SP2_RA_N         , observe_only , X   )                          ,"&
    "  158  (BC_1       , *                , control      , 0   )                          ,"&
    "  157  (AC_1       , SP2_TC_P         , output3      , X    ,   158    , 0     , Z   ),"&
    "  156  (BC_4       , SP2_RC_P         , observe_only , X   )                          ,"&
    "  155  (BC_4       , SP2_RC_N         , observe_only , X   )                          ,"&
    "  154  (BC_1       , *                , control      , 0   )                          ,"&
    "  153  (AC_1       , SP2_TD_P         , output3      , X    ,   154    , 0     , Z   ),"&
    "  152  (BC_4       , SP2_RD_P         , observe_only , X   )                          ,"&
    "  151  (BC_4       , SP2_RD_N         , observe_only , X   )                          ,"&
    "  150  (BC_1       , *                , control      , 0   )                          ,"&
    "  149  (AC_1       , SP4_TB_P         , output3      , X    ,   150    , 0     , Z   ),"&
    "  148  (BC_4       , SP4_RB_P         , observe_only , X   )                          ,"&
    "  147  (BC_4       , SP4_RB_N         , observe_only , X   )                          ,"&
    "  146  (BC_1       , *                , control      , 0   )                          ,"&
    "  145  (AC_1       , SP4_TA_P         , output3      , X    ,   146    , 0     , Z   ),"&
    "  144  (BC_4       , SP4_RA_P         , observe_only , X   )                          ,"&
    "  143  (BC_4       , SP4_RA_N         , observe_only , X   )                          ,"&
    "  142  (BC_1       , *                , control      , 0   )                          ,"&
    "  141  (AC_1       , SP4_TC_P         , output3      , X    ,   142    , 0     , Z   ),"&
    "  140  (BC_4       , SP4_RC_P         , observe_only , X   )                          ,"&
    "  139  (BC_4       , SP4_RC_N         , observe_only , X   )                          ,"&
    "  138  (BC_1       , *                , control      , 0   )                          ,"&
    "  137  (AC_1       , SP4_TD_P         , output3      , X    ,   138    , 0     , Z   ),"&
    "  136  (BC_4       , SP4_RD_P         , observe_only , X   )                          ,"&
    "  135  (BC_4       , SP4_RD_N         , observe_only , X   )                          ,"&
    "  134  (BC_1       , *                , control      , 0   )                          ,"&
    "  133  (AC_1       , SP6_TB_P         , output3      , X    ,   134    , 0     , Z   ),"&
    "  132  (BC_4       , SP6_RB_P         , observe_only , X   )                          ,"&
    "  131  (BC_4       , SP6_RB_N         , observe_only , X   )                          ,"&
    "  130  (BC_1       , *                , control      , 0   )                          ,"&
    "  129  (AC_1       , SP6_TA_P         , output3      , X    ,   130    , 0     , Z   ),"&
    "  128  (BC_4       , SP6_RA_P         , observe_only , X   )                          ,"&
    "  127  (BC_4       , SP6_RA_N         , observe_only , X   )                          ,"&
    "  126  (BC_1       , *                , control      , 0   )                          ,"&
    "  125  (AC_1       , SP6_TC_P         , output3      , X    ,   126    , 0     , Z   ),"&
    "  124  (BC_4       , SP6_RC_P         , observe_only , X   )                          ,"&
    "  123  (BC_4       , SP6_RC_N         , observe_only , X   )                          ,"&
    "  122  (BC_1       , *                , control      , 0   )                          ,"&
    "  121  (AC_1       , SP6_TD_P         , output3      , X    ,   122    , 0     , Z   ),"&
    "  120  (BC_4       , SP6_RD_P         , observe_only , X   )                          ,"&
    "  119  (BC_4       , SP6_RD_N         , observe_only , X   )                          ,"&
    "  118  (BC_1       , *                , control      , 0   )                          ,"&
    "  117  (AC_1       , SP8_TB_P         , output3      , X    ,   118    , 0     , Z   ),"&
    "  116  (BC_4       , SP8_RB_P         , observe_only , X   )                          ,"&
    "  115  (BC_4       , SP8_RB_N         , observe_only , X   )                          ,"&
    "  114  (BC_1       , *                , control      , 0   )                          ,"&
    "  113  (AC_1       , SP8_TA_P         , output3      , X    ,   114    , 0     , Z   ),"&
    "  112  (BC_4       , SP8_RA_P         , observe_only , X   )                          ,"&
    "  111  (BC_4       , SP8_RA_N         , observe_only , X   )                          ,"&
    "  110  (BC_1       , *                , control      , 0   )                          ,"&
    "  109  (AC_1       , SP8_TC_P         , output3      , X    ,   110    , 0     , Z   ),"&
    "  108  (BC_4       , SP8_RC_P         , observe_only , X   )                          ,"&
    "  107  (BC_4       , SP8_RC_N         , observe_only , X   )                          ,"&
    "  106  (BC_1       , *                , control      , 0   )                          ,"&
    "  105  (AC_1       , SP8_TD_P         , output3      , X    ,   106    , 0     , Z   ),"&
    "  104  (BC_4       , SP8_RD_P         , observe_only , X   )                          ,"&
    "  103  (BC_4       , SP8_RD_N         , observe_only , X   )                          ,"&
    "  102  (BC_1       , *                , control      , 0   )                          ,"&
    "  101  (AC_1       , SP10_TB_P        , output3      , X    ,   102    , 0     , Z   ),"&
    "  100  (BC_4       , SP10_RB_P        , observe_only , X   )                          ,"&
    "  99   (BC_4       , SP10_RB_N        , observe_only , X   )                          ,"&
    "  98   (BC_1       , *                , control      , 0   )                          ,"&
    "  97   (AC_1       , SP10_TA_P        , output3      , X    ,   98     , 0     , Z   ),"&
    "  96   (BC_4       , SP10_RA_P        , observe_only , X   )                          ,"&
    "  95   (BC_4       , SP10_RA_N        , observe_only , X   )                          ,"&
    "  94   (BC_1       , *                , control      , 0   )                          ,"&
    "  93   (AC_1       , SP10_TC_P        , output3      , X    ,   94     , 0     , Z   ),"&
    "  92   (BC_4       , SP10_RC_P        , observe_only , X   )                          ,"&
    "  91   (BC_4       , SP10_RC_N        , observe_only , X   )                          ,"&
    "  90   (BC_1       , *                , control      , 0   )                          ,"&
    "  89   (AC_1       , SP10_TD_P        , output3      , X    ,   90     , 0     , Z   ),"&
    "  88   (BC_4       , SP10_RD_P        , observe_only , X   )                          ,"&
    "  87   (BC_4       , SP10_RD_N        , observe_only , X   )                          ,"&
    "  86   (BC_1       , *                , control      , 0   )                          ,"&
    "  85   (AC_1       , SP12_TB_P        , output3      , X    ,   86     , 0     , Z   ),"&
    "  84   (BC_4       , SP12_RB_P        , observe_only , X   )                          ,"&
    "  83   (BC_4       , SP12_RB_N        , observe_only , X   )                          ,"&
    "  82   (BC_1       , *                , control      , 0   )                          ,"&
    "  81   (AC_1       , SP12_TA_P        , output3      , X    ,   82     , 0     , Z   ),"&
    "  80   (BC_4       , SP12_RA_P        , observe_only , X   )                          ,"&
    "  79   (BC_4       , SP12_RA_N        , observe_only , X   )                          ,"&
    "  78   (BC_1       , *                , control      , 0   )                          ,"&
    "  77   (AC_1       , SP12_TC_P        , output3      , X    ,   78     , 0     , Z   ),"&
    "  76   (BC_4       , SP12_RC_P        , observe_only , X   )                          ,"&
    "  75   (BC_4       , SP12_RC_N        , observe_only , X   )                          ,"&
    "  74   (BC_1       , *                , control      , 0   )                          ,"&
    "  73   (AC_1       , SP12_TD_P        , output3      , X    ,   74     , 0     , Z   ),"&
    "  72   (BC_4       , SP12_RD_P        , observe_only , X   )                          ,"&
    "  71   (BC_4       , SP12_RD_N        , observe_only , X   )                          ,"&
    "  70   (BC_1       , *                , control      , 0   )                          ,"&
    "  69   (AC_1       , SP14_TB_P        , output3      , X    ,   70     , 0     , Z   ),"&
    "  68   (BC_4       , SP14_RB_P        , observe_only , X   )                          ,"&
    "  67   (BC_4       , SP14_RB_N        , observe_only , X   )                          ,"&
    "  66   (BC_1       , *                , control      , 0   )                          ,"&
    "  65   (AC_1       , SP14_TA_P        , output3      , X    ,   66     , 0     , Z   ),"&
    "  64   (BC_4       , SP14_RA_P        , observe_only , X   )                          ,"&
    "  63   (BC_4       , SP14_RA_N        , observe_only , X   )                          ,"&
    "  62   (BC_1       , *                , control      , 0   )                          ,"&
    "  61   (AC_1       , SP14_TC_P        , output3      , X    ,   62     , 0     , Z   ),"&
    "  60   (BC_4       , SP14_RC_P        , observe_only , X   )                          ,"&
    "  59   (BC_4       , SP14_RC_N        , observe_only , X   )                          ,"&
    "  58   (BC_1       , *                , control      , 0   )                          ,"&
    "  57   (AC_1       , SP14_TD_P        , output3      , X    ,   58     , 0     , Z   ),"&
    "  56   (BC_4       , SP14_RD_P        , observe_only , X   )                          ,"&
    "  55   (BC_4       , SP14_RD_N        , observe_only , X   )                          ,"&
    "  54   (BC_4       , P_CLK            , clock        , X   )                          ,"&
    "  53   (BC_2       , *                , control      , 0   )                          ,"&
    "  52   (LV_BC_7    , I2C_SCLK         , bidir        , X    ,   53     , 0     , Z   ),"&
    "  51   (BC_2       , *                , control      , 0   )                          ,"&
    "  50   (LV_BC_7    , I2C_SD           , bidir        , X    ,   51     , 0     , Z   ),"&
    "  49   (BC_2       , *                , control      , 0   )                          ,"&
    "  48   (LV_BC_7    , I2C_DISABLE      , bidir        , X    ,   49     , 0     , Z   ),"&
    "  47   (BC_2       , *                , control      , 0   )                          ,"&
    "  46   (LV_BC_7    , I2C_MA           , bidir        , X    ,   47     , 0     , Z   ),"&
    "  45   (LV_BC_7    , I2C_SA(1)        , bidir        , X    ,   47     , 0     , Z   ),"&
    "  44   (LV_BC_7    , I2C_SA(0)        , bidir        , X    ,   47     , 0     , Z   ),"&
    "  43   (LV_BC_7    , I2C_SEL          , bidir        , X    ,   47     , 0     , Z   ),"&
    "  42   (BC_2       , *                , control      , 0   )                          ,"&
    "  41   (LV_BC_7    , INT_B            , bidir        , X    ,   42     , 0     , Z   ),"&
    "  40   (BC_2       , *                , control      , 0   )                          ,"&
    "  39   (LV_BC_7    , SW_RST_B         , bidir        , X    ,   40     , 0     , Z   ),"&
    "  38   (BC_0       , *               , internal        , 0   )                          ,"&
    "  37   (BC_2       , *                , control      , 0   )                          ,"&
    "  36   (BC_2       , DO               , output3      , X    ,   37     , 0     , Z   ),"&
    "  35   (BC_2       , *                , control      , 0   )                          ,"&
    "  34   (LV_BC_7    , SP_RX_SWAP       , bidir        , X    ,   35     , 0     , Z   ),"&
    "  33   (LV_BC_7    , SP_TX_SWAP       , bidir        , X    ,   35     , 0     , Z   ),"&
    "  32   (LV_BC_7    , SP_IO_SPEED(1)   , bidir        , X    ,   35     , 0     , Z   ),"&
    "  31   (LV_BC_7    , SP_IO_SPEED(0)   , bidir        , X    ,   35     , 0     , Z   ),"&
    "  30   (BC_2       , *                , control      , 0   )                          ,"&
    "  29   (LV_BC_7    , SP1_PWRDN        , bidir        , X    ,   30     , 0     , Z   ),"&
    "  28   (LV_BC_7    , SP2_PWRDN        , bidir        , X    ,   30     , 0     , Z   ),"&
    "  27   (LV_BC_7    , SP3_PWRDN        , bidir        , X    ,   30     , 0     , Z   ),"&
    "  26   (BC_2       , *                , control      , 0   )                          ,"&
    "  25   (LV_BC_7    , SP4_PWRDN        , bidir        , X    ,   26     , 0     , Z   ),"&
    "  24   (LV_BC_7    , SP5_PWRDN        , bidir        , X    ,   26     , 0     , Z   ),"&
    "  23   (LV_BC_7    , SP6_PWRDN        , bidir        , X    ,   26     , 0     , Z   ),"&
    "  22   (LV_BC_7    , SP7_PWRDN        , bidir        , X    ,   26     , 0     , Z   ),"&
    "  21   (BC_2       , *                , control      , 0   )                          ,"&
    "  20   (LV_BC_7    , SP8_PWRDN        , bidir        , X    ,   21     , 0     , Z   ),"&
    "  19   (LV_BC_7    , SP9_PWRDN        , bidir        , X    ,   21     , 0     , Z   ),"&
    "  18   (LV_BC_7    , SP10_PWRDN       , bidir        , X    ,   21     , 0     , Z   ),"&
    "  17   (LV_BC_7    , SP11_PWRDN       , bidir        , X    ,   21     , 0     , Z   ),"&
    "  16   (BC_2       , *                , control      , 0   )                          ,"&
    "  15   (LV_BC_7    , SP12_PWRDN       , bidir        , X    ,   16     , 0     , Z   ),"&
    "  14   (LV_BC_7    , SP13_PWRDN       , bidir        , X    ,   16     , 0     , Z   ),"&
    "  13   (LV_BC_7    , SP14_PWRDN       , bidir        , X    ,   16     , 0     , Z   ),"&
    "  12   (LV_BC_7    , SP15_PWRDN       , bidir        , X    ,   16     , 0     , Z   ),"&
    "  11   (LV_BC_7    , SP0_MODESEL      , bidir        , X    ,   30     , 0     , Z   ),"&
    "  10   (BC_2       , *                , control      , 0   )                          ,"&
    "  9    (LV_BC_7    , SP2_MODESEL      , bidir        , X    ,   10     , 0     , Z   ),"&
    "  8    (BC_2       , *                , control      , 0   )                          ,"&
    "  7    (LV_BC_7    , SP4_MODESEL      , bidir        , X    ,   8      , 0     , Z   ),"&
    "  6    (LV_BC_7    , SP6_MODESEL      , bidir        , X    ,   8      , 0     , Z   ),"&
    "  5    (LV_BC_7    , SP8_MODESEL      , bidir        , X    ,   8      , 0     , Z   ),"&
    "  4    (LV_BC_7    , SP10_MODESEL     , bidir        , X    ,   8      , 0     , Z   ),"&
    "  3    (LV_BC_7    , SP12_MODESEL     , bidir        , X    ,   10     , 0     , Z   ),"&
    "  2    (LV_BC_7    , SP14_MODESEL     , bidir        , X    ,   10     , 0     , Z   ),"&
    "  1    (BC_2       , *                , control      , 0   )                          ,"&
    "  0    (LV_BC_7    , MCES             , bidir        , X    ,   1      , 0     , Z   ) ";

    attribute AIO_COMPONENT_CONFORMANCE of Tsi578: entity is "STD_1149_6_2003";


    attribute AIO_Pin_Behavior of Tsi578: entity is 
        "SP0_TD_P;"&
        "SP0_TC_P;"&
        "SP0_TB_P;"&
        "SP0_TA_P;"&
        "SP2_TD_P;"&
        "SP2_TC_P;"&
        "SP2_TB_P;"&
        "SP2_TA_P;"&
        "SP4_TD_P;"&
        "SP4_TC_P;"&
        "SP4_TB_P;"&
        "SP4_TA_P;"&
        "SP6_TD_P;"&
        "SP6_TC_P;"&
        "SP6_TB_P;"&
        "SP6_TA_P;"&
        "SP8_TD_P;"&
        "SP8_TC_P;"&
        "SP8_TB_P;"&
        "SP8_TA_P;"&
        "SP10_TD_P;"&
        "SP10_TC_P;"&
        "SP10_TB_P;"&
        "SP10_TA_P;"&
        "SP12_TD_P;"&
        "SP12_TC_P;"&
        "SP12_TB_P;"&
        "SP12_TA_P;"&
        "SP14_TD_P;"&
        "SP14_TC_P;"&
        "SP14_TB_P;"&
        "SP14_TA_P;"&
        "SP0_RB_P[180]            : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
        "SP0_RA_P[176]            : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
        "SP0_RC_P[172]            : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
        "SP0_RD_P[168]            : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
        "SP2_RB_P[164]            : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
        "SP2_RA_P[160]            : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
        "SP2_RC_P[156]            : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
        "SP2_RD_P[152]            : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
        "SP4_RB_P[148]            : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
        "SP4_RA_P[144]            : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
        "SP4_RC_P[140]            : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
        "SP4_RD_P[136]            : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
        "SP6_RB_P[132]            : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
        "SP6_RA_P[128]            : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
        "SP6_RC_P[124]            : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
        "SP6_RD_P[120]            : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
        "SP8_RB_P[116]            : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
        "SP8_RA_P[112]            : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
        "SP8_RC_P[108]            : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
        "SP8_RD_P[104]            : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
        "SP10_RB_P[100]           : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
        "SP10_RA_P[96]            : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
        "SP10_RC_P[92]            : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
        "SP10_RD_P[88]            : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
        "SP12_RB_P[84]            : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
        "SP12_RA_P[80]            : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
        "SP12_RC_P[76]            : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
        "SP12_RD_P[72]            : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
        "SP14_RB_P[68]            : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
        "SP14_RA_P[64]            : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
        "SP14_RC_P[60]            : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
        "SP14_RD_P[56]            : LP_Time=2.30e-07 HP_Time=7.00e-06";
end Tsi578;
-- VHDL package to be uploaded
--package LVS_BSCAN_CELLS is
--    use STD_1149_1_2001.all;
--        constant LV_BC_7: CELL_INFO;
--
--end LVS_BSCAN_CELLS;
--package body LVS_BSCAN_CELLS is
--    use STD_1149_1_2001.all;
--        constant LV_BC_7: CELL_INFO := 
--           ((BIDIR_IN, EXTEST,  PI),  (BIDIR_OUT, EXTEST,  PO),
--           (BIDIR_IN, SAMPLE,  PI),  (BIDIR_OUT, SAMPLE,  PI),
--           (BIDIR_IN, INTEST,  X),  (BIDIR_OUT, INTEST,  PI));
--
--end LVS_BSCAN_CELLS;
--