-- ===================================================================
-- $Id: DS3104_BGA81.bsdl.rca 1.3 Thu Dec 7 13:59:31 2006 $
-- ===================================================================
-- Copyright (c) 2006 Microsemi Corporation
-- All Rights Reserved.
--
-- THIS MATERIAL IS CONSIDERED CONFIDENTIAL AND PROPRIETARY BY
-- Microsemi Corporation. UNAUTHORIZED ACCESS OR USE IS PROHIBITED.
-- ===================================================================
-- $RCSfile: DS3104_BGA81.bsdl.rca $
--
-- $Author: aw $
-- ===================================================================
--
-- Abstract :
--
-- Detail :
--
-- Usage :
--
-- File usage :
--
-- This file was script-generated.
--
-- ===================================================================
-- ===================================================================
-- BSDL file for design DS3104_BGA81
-- Created by 31IP38 JTAG script
-- Company: Microsemi Corporation
-- Date:
-- ***********************************************************************
entity DS3104_BGA81 is
-- This section identifies the default device package selected.
generic (PHYSICAL_PIN_MAP: string:= "BGA81");
-- This section declares all the ports in the design.
port (
AVDD_PLL1 : linkage bit;
AVDD_PLL2 : linkage bit;
AVDD_PLL3 : linkage bit;
AVDD_PLL4 : linkage bit;
AVSS_PLL1 : linkage bit;
AVSS_PLL2 : linkage bit;
AVSS_PLL3 : linkage bit;
AVSS_PLL4 : linkage bit;
CPHA : inout bit;
CPOL : inout bit;
CS_N : inout bit;
FSYNC : linkage bit;
IC1NEG : linkage bit;
IC1POS : linkage bit;
IC2NEG : linkage bit;
IC2POS : linkage bit;
IC3 : inout bit;
IC4 : inout bit;
IC5NEG : linkage bit;
IC5POS : linkage bit;
IC6NEG : linkage bit;
IC6POS : linkage bit;
IC8 : inout bit;
IC9 : inout bit;
INTREQ : inout bit;
JTCLK : in bit;
JTDI : in bit;
JTDO : out bit;
JTMS : in bit;
JTRST_N : in bit;
LOCK : inout bit;
MFSYNC : linkage bit;
OC1 : linkage bit;
OC1B : linkage bit;
OC2 : linkage bit;
OC2B : linkage bit;
OC3 : linkage bit;
OC3B : linkage bit;
OC4 : linkage bit;
OC4B : linkage bit;
OC4NEG : linkage bit;
OC4POS : linkage bit;
OC5 : linkage bit;
OC5B : linkage bit;
OC5NEG : linkage bit;
OC5POS : linkage bit;
OC6NEG : linkage bit;
OC6POS : linkage bit;
OC7NEG : linkage bit;
OC7POS : linkage bit;
REFCLK : inout bit;
RST_N : inout bit;
SCLK : inout bit;
SDI : inout bit;
SDO : inout bit;
SONSDH : inout bit;
SRCSW : inout bit;
SRFAIL : inout bit;
SYNC1 : inout bit;
SYNC2 : inout bit;
SYNC3 : inout bit;
TEST : inout bit;
VDD : linkage bit_vector (0 to 2);
VDDIO : linkage bit_vector (0 to 3);
VDDIOB : linkage bit;
VDD_OC45 : linkage bit;
VDD_OC67 : linkage bit;
VSS : linkage bit_vector (0 to 5);
VSS_OC45 : linkage bit;
VSS_OC67 : linkage bit;
WDT : inout bit
);
use STD_1149_1_1994.all;
attribute COMPONENT_CONFORMANCE of DS3104_BGA81: entity is "STD_1149_1_1993";
attribute PIN_MAP of DS3104_BGA81: entity is PHYSICAL_PIN_MAP;
-- This section specifies the pin map for each port. This information
-- is extracted from the port-to-pin map file that was read in using
-- the "read_pin_map" command.
constant BGA81: PIN_MAP_STRING :=
"AVDD_PLL1 : B2," &
"AVDD_PLL2 : C2," &
"AVDD_PLL3 : F2," &
"AVDD_PLL4 : F3," &
"AVSS_PLL1 : A1," &
"AVSS_PLL2 : C3," &
"AVSS_PLL3 : F1," &
"AVSS_PLL4 : G2," &
"CPHA : E7," &
"CPOL : D7," &
"CS_N : D9," &
"FSYNC : H1," &
"IC1NEG : J5," &
"IC1POS : H5," &
"IC2NEG : J7," &
"IC2POS : H7," &
"IC3 : J8," &
"IC4 : J9," &
"IC5NEG : J4," &
"IC5POS : H4," &
"IC6NEG : J6," &
"IC6POS : H6," &
"IC8 : F9," &
"IC9 : G9," &
"INTREQ : B1," &
"JTCLK : A9," &
"JTDI : A8," &
"JTDO : C8," &
"JTMS : E9," &
"JTRST_N : F8," &
"LOCK : G7," &
"MFSYNC : J1," &
"OC1 : B8," &
"OC1B : B4," &
"OC2 : A7," &
"OC2B : A5," &
"OC3 : B7," &
"OC3B : B5," &
"OC4 : A3," &
"OC4B : A6," &
"OC4NEG : D1," &
"OC4POS : D2," &
"OC5 : A4," &
"OC5B : B6," &
"OC5NEG : E1," &
"OC5POS : E2," &
"OC6NEG : J2," &
"OC6POS : H2," &
"OC7NEG : J3," &
"OC7POS : H3," &
"REFCLK : C1," &
"RST_N : B9," &
"SCLK : C9," &
"SDI : E8," &
"SDO : C7," &
"SONSDH : B3," &
"SRCSW : G1," &
"SRFAIL : F7," &
"SYNC1 : H8," &
"SYNC2 : H9," &
"SYNC3 : G8," &
"TEST : A2," &
"VDD :(C5, E6, G6)," &
"VDDIO :(C4, D6, F6, G3)," &
"VDDIOB : C6," &
"VDD_OC45 : E3," &
"VDD_OC67 : G5," &
"VSS :(D4, D5, E4, E5, F4, F5)," &
"VSS_OC45 : D3," &
"VSS_OC67 : G4," &
"WDT : D8" ;
-- This section specifies the TAP ports.
-- For the TAP TCK port, the parameters in the brackets are:
-- First Field : Maximum TCK frequency.
-- Second Field: Allowable states TCK may be stopped in.
attribute TAP_SCAN_CLOCK of JTCLK : signal is (10.0e6, BOTH);
attribute TAP_SCAN_IN of JTDI : signal is true;
attribute TAP_SCAN_MODE of JTMS : signal is true;
attribute TAP_SCAN_OUT of JTDO : signal is true;
attribute TAP_SCAN_RESET of JTRST_N : signal is true;
-- Specifies the number of bits in the instruction register.
attribute INSTRUCTION_LENGTH of DS3104_BGA81: entity is 3;
-- Specifies the boundary-scan instructions implemented in the
-- design and their opcodes.
attribute INSTRUCTION_OPCODE of DS3104_BGA81: entity is
"BYPASS (111)," &
"EXTEST (000)," &
"SAMPLE (010)," &
"CLAMP (011)," &
"HIGHZ (100)," &
"USER1 (101)," &
"USER2 (110)," &
"IDCODE (001)";
-- Specifies the bit pattern that is loaded into the instruction
-- register when the TAP controller passes through the Capture-IR
-- state. The standard mandates that the two LSBs must be "01".
-- The remaining bits are design specific.
attribute INSTRUCTION_CAPTURE of DS3104_BGA81: entity is "001";
-- Specifies the bit pattern that is loaded into the DEVICE_ID
-- register during the IDCODE instruction when the TAP controller
-- passes through the Capture-DR state.
attribute IDCODE_REGISTER of DS3104_BGA81: entity is
"0000" & -- 4-bit version number
"0000000010100010" & -- 16-bit part number
"00010100001" & -- 11-bit identity of the manufacturer
"1"; -- Required by IEEE Std 1149.1
-- This section specifies the test data register placed between TDI
-- and TDO for each implemented instruction.
attribute REGISTER_ACCESS of DS3104_BGA81: entity is
"BYPASS (BYPASS, CLAMP, HIGHZ, USER1, USER2)," &
"BOUNDARY (EXTEST, SAMPLE)," &
"DEVICE_ID (IDCODE)";
-- Specifies the length of the boundary scan register.
attribute BOUNDARY_LENGTH of DS3104_BGA81: entity is 48;
-- The following list specifies the characteristics of each cell
-- in the boundary scan register from TDI to TDO.
-- The following is a description of the label fields:
-- num : Is the cell number.
-- cell : Is the cell type as defined by the standard.
-- port : Is the design port name. Control cells do not
-- have a port name.
-- function: Is the function of the cell as defined by the
-- standard. Is one of input, output2, output3,
-- bidir, control or controlr.
-- safe : Specifies the value that the BSR cell should be
-- loaded with for safe operation when the software
-- might otherwise choose a random value.
-- ccell : The control cell number. Specifies the control
-- cell that drives the output enable for this port.
-- disval : Specifies the value that is loaded into the
-- control cell to disable the output enable for
-- the corresponding port.
-- rslt : Resulting state. Shows the state of the driver
-- when it is disabled.
attribute BOUNDARY_REGISTER of DS3104_BGA81: entity is
--
-- num cell port function safe [ccell disval rslt]
--
"47 (BC_1, *, controlr, 0), " &
"46 (BC_0, SDO, bidir, X, 47 , 0, Z), " &
"45 (BC_0, *, internal, 0), " &
"44 (BC_0, *, internal, X), " &
"43 (BC_1, *, controlr, 0), " &
"42 (BC_0, SONSDH, bidir, X, 43 , 0, Z), " &
"41 (BC_1, *, controlr, 0), " &
"40 (BC_0, TEST, bidir, X, 41 , 0, Z), " &
"39 (BC_1, *, controlr, 0), " &
"38 (BC_0, INTREQ, bidir, X, 39 , 0, Z), " &
"37 (BC_1, *, controlr, 0), " &
"36 (BC_0, REFCLK, bidir, X, 37 , 0, Z), " &
"35 (BC_1, *, controlr, 0), " &
"34 (BC_0, SRCSW, bidir, X, 35 , 0, Z), " &
"33 (BC_1, *, controlr, 0), " &
"32 (BC_0, SYNC1, bidir, X, 33 , 0, Z), " &
"31 (BC_1, *, controlr, 0), " &
"30 (BC_0, IC3, bidir, X, 31 , 0, Z), " &
"29 (BC_1, *, controlr, 0), " &
"28 (BC_0, IC4, bidir, X, 29 , 0, Z), " &
"27 (BC_1, *, controlr, 0), " &
"26 (BC_0, SYNC2, bidir, X, 27 , 0, Z), " &
"25 (BC_1, *, controlr, 0), " &
"24 (BC_0, IC9, bidir, X, 25 , 0, Z), " &
"23 (BC_1, *, controlr, 0), " &
"22 (BC_0, SYNC3, bidir, X, 23 , 0, Z), " &
"21 (BC_1, *, controlr, 0), " &
"20 (BC_0, LOCK, bidir, X, 21 , 0, Z), " &
"19 (BC_1, *, controlr, 0), " &
"18 (BC_0, IC8, bidir, X, 19 , 0, Z), " &
"17 (BC_1, *, controlr, 0), " &
"16 (BC_0, SRFAIL, bidir, X, 17 , 0, Z), " &
"15 (BC_1, *, controlr, 0), " &
"14 (BC_0, CPHA, bidir, X, 15 , 0, Z), " &
"13 (BC_1, *, controlr, 0), " &
"12 (BC_0, SDI, bidir, X, 13 , 0, Z), " &
"11 (BC_1, *, controlr, 0), " &
"10 (BC_0, CS_N, bidir, X, 11 , 0, Z), " &
"9 (BC_1, *, controlr, 0), " &
"8 (BC_0, WDT, bidir, X, 9 , 0, Z), " &
"7 (BC_0, *, internal, 0), " &
"6 (BC_0, *, internal, X), " &
"5 (BC_1, *, controlr, 0), " &
"4 (BC_0, CPOL, bidir, X, 5 , 0, Z), " &
"3 (BC_1, *, controlr, 0), " &
"2 (BC_0, SCLK, bidir, X, 3 , 0, Z), " &
"1 (BC_1, *, controlr, 0), " &
"0 (BC_0, RST_N, bidir, X, 1 , 0, Z) " ;
end DS3104_BGA81;
-- ===================================================================
-- Revision History :
--
-- $Log: DS3104_BGA81.bsdl.rca $
--
-- Revision: 1.3 Thu Dec 7 13:59:31 2006
--
-- updated to match datasheet pin names
--
-- ===================================================================
