----------------------------------------------------------------------
-- BSDL file for:
--
-- ADSP_BF539 Digital Signal Processor in mBGA Package
-- ADSP_BF539F Digital Signal Processor in mBGA Package
--
----------------------------------------------------------------------
-- Revision: 0.0
-- Date: 02/08/2005
-- Revision Summary:
--
-- Initial Revision
----------------------------------------------------------------------
-- Revision: 0.1
-- Date: 01/23/2007
-- Revision Summary:
--
-- General clean-up and made pin name corrections:
-- CRX --> CANRX
-- CTX --> CANTX
-- FCE --> FCE_B
-- MISO --> MISO0
-- MOSI --> MOSI0
-- MTXON --> MTXON_B
-- NMI --> NMI_B
-- PPCLK --> PPI_CLK
-- PP --> PPI
-- SPI1SEL --> SPI1SEL1_B
-- SPI1SS --> SPI1SS_B
-- SPI2SEL --> SPI2SEL1_B
-- SPI2SS --> SPI2SS_B
-- RX --> RX0
-- SCK --> SCK0
-- TX --> TX0
-- VDD_EXT --> VDDEXT
-- VDD_INT --> VDDINT
-- VDD_RTC --> VDDRTC
--
-- Changed GND(B16) to be MXEGND(B16).
--
-- Changed output3 and control for pins MRX, MRXON_B, and CRX into
-- internal as these are "input-only" pins.
----------------------------------------------------------------------
entity ADSP_BF539 is
generic (PHYSICAL_PIN_MAP : string:="BGA_PACKAGE");
port( ABE_B: out bit_vector(0 to 1);
ADDR: out bit_vector(1 to 19);
AMS_B: out bit_vector(0 to 3);
AOE_B: out bit;
ARDY: in bit;
ARE_B: out bit;
AWE_B: out bit;
BG_B: buffer bit;
BGH_B: buffer bit;
BMODE: in bit_vector(0 to 1);
BR_B: in bit;
CANRX: in bit;
CANTX: inout bit;
CLKIN: linkage bit;
CLKOUT: out bit;
DATA: inout bit_vector(0 to 15);
DR0PRI: in bit;
DR0SEC: in bit;
DR1PRI: in bit;
DR1SEC: in bit;
DR2PRI: inout bit;
DR2SEC: inout bit;
DR3PRI: inout bit;
DR3SEC: inout bit;
DT0PRI: out bit;
DT0SEC: out bit;
DT1PRI: out bit;
DT1SEC: out bit;
DT2PRI: inout bit;
DT2SEC: inout bit;
DT3PRI: inout bit;
DT3SEC: inout bit;
EMU_B: linkage bit;
FCE_B: linkage bit;
FRESET_B: linkage bit;
GND: linkage bit_vector(0 to 115);
GP: linkage bit;
MBCLK: inout bit;
MFS: inout bit;
MMCLK: inout bit;
MLF: linkage bit;
MISO0: inout bit;
MISO1: inout bit;
MISO2: inout bit;
MOSI0: inout bit;
MOSI1: inout bit;
MOSI2: inout bit;
MPIVDD: linkage bit;
MRXON_B: in bit;
MRX: in bit;
MTX: inout bit;
MTXON_B: inout bit;
MXEGND: linkage bit;
MXEVDD: linkage bit;
MXI: linkage bit;
MXO: linkage bit;
NMI_B: in bit;
PF: inout bit_vector(0 to 15);
PPI_CLK: in bit;
PPI: inout bit_vector(0 to 3);
RESET_B: in bit;
RFS0: inout bit;
RFS1: inout bit;
RFS2: inout bit;
RFS3: inout bit;
RSCLK0: inout bit;
RSCLK1: inout bit;
RSCLK2: inout bit;
RSCLK3: inout bit;
RTXI: linkage bit;
RTXO: linkage bit;
RX0: in bit;
RX1: inout bit;
RX2: inout bit;
SA10: out bit;
SCAS_B: out bit;
SCK0: inout bit;
SCK1: inout bit;
SCK2: inout bit;
SCKE: out bit;
SCL0: inout bit;
SCL1: inout bit;
SDA0: inout bit;
SDA1: inout bit;
SMS_B: out bit;
SPI1SS_B: inout bit;
SPI1SEL1_B: inout bit;
SPI2SS_B: inout bit;
SPI2SEL1_B: inout bit;
SRAS_B: out bit;
SWE_B: out bit;
TCK: in bit;
TDI: in bit;
TDO: out bit;
TFS0: inout bit;
TFS1: inout bit;
TFS2: inout bit;
TFS3: inout bit;
TMR0: inout bit;
TMR1: inout bit;
TMR2: inout bit;
TMS: in bit;
TRST_B: in bit;
TSCLK0: inout bit;
TSCLK1: inout bit;
TSCLK2: inout bit;
TSCLK3: inout bit;
TX0: buffer bit;
TX1: inout bit;
TX2: inout bit;
VDDEXT: linkage bit_vector(0 to 18);
VDDINT: linkage bit_vector(0 to 10);
VDDRTC: linkage bit;
VROUT: linkage bit_vector(0 to 1);
XTAL: linkage bit);
use STD_1149_1_1990.all;
attribute PIN_MAP of ADSP_BF539: entity is PHYSICAL_PIN_MAP;
constant BGA_PACKAGE: PIN_MAP_STRING:=
"ABE_B: (M19,M20)," &
"ADDR: (N19,N20,P19,P20,R19,R20,T19,T20,U19," &
"U20,V19,V20,W18,W20,W17,Y19,Y18,W16,Y17)," &
"AMS_B: (J18,K19,J19,K18)," &
"AOE_B: K20," &
"ARDY: E20," &
"ARE_B: L19," &
"AWE_B: L20," &
"BG_B: V14," &
"BGH_B: V15," &
"BMODE: (V5,V4)," &
"BR_B: G18," &
"CANRX: B11," &
"CANTX: B12," &
"CLKIN: A13," &
"CLKOUT: G19," &
"DATA: (Y10,W10,Y9,W9,Y8,W8,Y7,W7,Y6,W6,Y5,W5,Y4,W4,Y3,W3)," &
"DR0PRI: N2," &
"DR0SEC: J3," &
"DR1PRI: J2," &
"DR1SEC: H3," &
"DR2PRI: W12," &
"DR2SEC: V13," &
"DR3PRI: R18," &
"DR3SEC: P18," &
"DT0PRI: M1," &
"DT0SEC: G3," &
"DT1PRI: H1," &
"DT1SEC: D3," &
"DT2PRI: W13," &
"DT2SEC: V16," &
"DT3PRI: F18," &
"DT3SEC: N18," &
"EMU_B: T2," &
"FCE_B: H18," &
"FRESET_B: Y14," &
"GND: (B18,E3,F3,L3,M3,M8,M9,M10,M11,M12,M13,N3,N8,N9,N10,N11,N12,N13,P3,P8," &
"P9,P10,P11,P12,P13,R3,R8,R9,R10,R11,R12,R13,T3,U3,V6,A1,A20,B2,B19,C3,C18,D7,D8,D9,D10," &
"D11,D12,D13,D14,D18,E7,E8,E9,E10,E11,E12,E13,E14,E18,F7,F8,F9,F10,F11,F12,F13,F14,G7,G8,G9," &
"G10,G11,G12,G13,G14,H7,H8,H9,H10,H11,H12,H13,H14,J7,J8,J9,J10,J11,J12,J13,J14,K7,K8,K9,K10,K11,K12," &
"K13,K14,L7,L8,L9,L10,L11,L12,L13,L14,V3,V17,V18,W2,W19,Y1,Y20,A12,V2)," &
"GP: K3," &
"MBCLK: D19," &
"MFS: F20," &
"MMCLK: C19," &
"MLF: A15," &
"MISO0: F2," &
"MISO1: C14," &
"MISO2: C10," &
"MOSI0: G2," &
"MOSI1: C16," &
"MOSI2: C9," &
"MPIVDD: C12," &
"MRXON_B: A18," &
"MRX: F19," &
"MTX: E19," &
"MTXON_B: B17," &
"MXEGND: B16," &
"MXEVDD: B15," &
"MXI: A17," &
"MXO: A16," &
"NMI_B: B13," &
"PF: (F1,E1,E2,B4,D1,D2,C1,C2,B1,B3,A2,A3,B8,A8,B7,A7)," &
"PPI_CLK: A4," &
"PPI: (A5,B5,A6,B6)," &
"RESET_B: B14," &
"RFS0: P2," &
"RFS1: K1," &
"RFS2: Y11," &
"RFS3: T18," &
"RSCLK0: R2," &
"RSCLK1: L1," &
"RSCLK2: W11," &
"RSCLK3: U18," &
"RTXI: A11," &
"RTXO: A10," &
"RX0: T1," &
"RX1: C5," &
"RX2: W14," &
"SA10: J20," &
"SCAS_B: H19," &
"SCK0: G1," &
"SCK1: C17," &
"SCK2: C11," &
"SCKE: C20," &
"SCL0: B9," &
"SCL1: Y15," &
"SDA0: B10," &
"SDA1: Y16," &
"SMS_B: D20," &
"SPI1SEL1_B: C13," &
"SPI1SS_B: C15," &
"SPI2SEL1_B: C7," &
"SPI2SS_B: C8," &
"SRAS_B: G20," &
"SWE_B: H20," &
"TCK: W1," &
"TDI: V1," &
"TDO: Y2," &
"TFS0: N1," &
"TFS1: J1," &
"TFS2: Y13," &
"TFS3: M18," &
"TMR0: M2," &
"TMR1: L2," &
"TMR2: K2," &
"TMS: U2," &
"TRST_B: U1," &
"TSCLK0: P1," &
"TSCLK1: H2," &
"TSCLK2: Y12," &
"TSCLK3: L18," &
"TX0: R1," &
"TX1: C6," &
"TX2: W15," &
"VDDEXT: (M7,N7,P7,R7,T7,T8,T9,T10,T11,U7,U8,U9,U10,U11,V7,V8,V9,V10,V11)," &
"VDDINT: (M14,N14,P14,R14,T12,T13,T14,U12,U13,U14,V12)," &
"VDDRTC: A9," &
"VROUT: (B20,A19)," &
"XTAL: A14" ;
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_RESET of TRST_B : signal is true;
attribute TAP_SCAN_CLOCK of TCK : signal is (50.0e6, BOTH);
attribute INSTRUCTION_LENGTH of ADSP_BF539: entity is 5;
-- Unspecified opcodes assigned to Bypass.
attribute INSTRUCTION_OPCODE of ADSP_BF539: entity is
"BYPASS (11111)," &
"EXTEST (00000)," &
"SAMPLE (10000)," &
"IDCODE (00010)," &
"MEMBIST (01010)," &
"EMULATION (00100,10100,01000,11110,01100)," &
"CUSTOMER_KEY (10110)," &
"TESTKEY (00110)";
attribute INSTRUCTION_CAPTURE of ADSP_BF539: entity is
"00001";
attribute INSTRUCTION_PRIVATE of ADSP_BF539: entity is
"EMULATION," &
"MEMBIST," &
"CUSTOMER_KEY," &
"TESTKEY" ;
attribute IDCODE_REGISTER of ADSP_BF539: entity is
"0001" & -- Silicon Revision ID
"0010011111000100" &
"00001100101" &
"1";
-- Silicon Revision ID's:
-- Rev 0.0: 0000
-- Rev 0.1: 0001
-- Rev 0.2: 0010
-- Rev 0.3: 0011
-- Rev 0.4: 0100
attribute BOUNDARY_CELLS of ADSP_BF539: entity is
"BC_1, BC_2, BC_3, BC_4";
-- BC_1: output, control; BC_2: input;
-- BC_3: internal; BC_4: clock;
attribute BOUNDARY_LENGTH of ADSP_BF539: entity is 325;
attribute BOUNDARY_REGISTER of ADSP_BF539: entity is
--num cell port function safe [ccell disval rslt ]
" 0 ( BC_1 , BG_B , output2 , X ) , " &
" 1 ( BC_1 , BGH_B , output2 , X ) , " &
" 2 ( BC_2 , TFS2 , input , X ) , " &
" 3 ( BC_1 , TFS2 , output3 , X , 4 , 0 , Z ) , " &
" 4 ( BC_1 , * , control , 0 ) , " &
" 5 ( BC_1 , ADDR(19) , output3 , X , 26 , 0 , Z ) , " &
" 6 ( BC_1 , ADDR(18) , output3 , X , 26 , 0 , Z ) , " &
" 7 ( BC_1 , ADDR(17) , output3 , X , 26 , 0 , Z ) , " &
" 8 ( BC_1 , ADDR(16) , output3 , X , 26 , 0 , Z ) , " &
" 9 ( BC_1 , ADDR(15) , output3 , X , 26 , 0 , Z ) , " &
" 10 ( BC_2 , DT2PRI , input , X ) , " &
" 11 ( BC_1 , DT2PRI , output3 , X , 12 , 0 , Z ) , " &
" 12 ( BC_1 , * , control , 0 ) , " &
" 13 ( BC_2 , DT2SEC , input , X ) , " &
" 14 ( BC_1 , DT2SEC , output3 , X , 15 , 0 , Z ) , " &
" 15 ( BC_1 , * , control , 0 ) , " &
" 16 ( BC_1 , ADDR(14) , output3 , X , 26 , 0 , Z ) , " &
" 17 ( BC_1 , ADDR(13) , output3 , X , 26 , 0 , Z ) , " &
" 18 ( BC_1 , ADDR(12) , output3 , X , 26 , 0 , Z ) , " &
" 19 ( BC_1 , ADDR(11) , output3 , X , 26 , 0 , Z ) , " &
" 20 ( BC_1 , ADDR(10) , output3 , X , 26 , 0 , Z ) , " &
" 21 ( BC_1 , ADDR(9) , output3 , X , 26 , 0 , Z ) , " &
" 22 ( BC_1 , ADDR(8) , output3 , X , 26 , 0 , Z ) , " &
" 23 ( BC_1 , ADDR(7) , output3 , X , 26 , 0 , Z ) , " &
" 24 ( BC_1 , ADDR(6) , output3 , X , 26 , 0 , Z ) , " &
" 25 ( BC_1 , ADDR(5) , output3 , X , 26 , 0 , Z ) , " &
" 26 ( BC_1 , * , control , 0 ) , " &
" 27 ( BC_1 , ADDR(4) , output3 , X , 26 , 0 , Z ) , " &
" 28 ( BC_1 , ADDR(3) , output3 , X , 26 , 0 , Z ) , " &
" 29 ( BC_1 , ADDR(2) , output3 , X , 26 , 0 , Z ) , " &
" 30 ( BC_1 , ADDR(1) , output3 , X , 26 , 0 , Z ) , " &
" 31 ( BC_2 , TX2 , input , X ) , " &
" 32 ( BC_1 , TX2 , output3 , X , 33 , 0 , Z ) , " &
" 33 ( BC_1 , * , control , 0 ) , " &
" 34 ( BC_2 , RSCLK3 , input , X ) , " &
" 35 ( BC_1 , RSCLK3 , output3 , X , 36 , 0 , Z ) , " &
" 36 ( BC_1 , * , control , 0 ) , " &
" 37 ( BC_2 , RFS3 , input , X ) , " &
" 38 ( BC_1 , RFS3 , output3 , X , 39 , 0 , Z ) , " &
" 39 ( BC_1 , * , control , 0 ) , " &
" 40 ( BC_1 , ABE_B(1) , output3 , X , 26 , 0 , Z ) , " &
" 41 ( BC_1 , ABE_B(0) , output3 , X , 26 , 0 , Z ) , " &
" 42 ( BC_1 , AWE_B , output3 , X , 45 , 0 , Z ) , " &
" 43 ( BC_1 , ARE_B , output3 , X , 45 , 0 , Z ) , " &
" 44 ( BC_1 , AOE_B , output3 , X , 45 , 0 , Z ) , " &
" 45 ( BC_1 , * , control , 0 ) , " &
" 46 ( BC_1 , AMS_B(3) , output3 , X , 45 , 0 , Z ) , " &
" 47 ( BC_1 , AMS_B(2) , output3 , X , 45 , 0 , Z ) , " &
" 48 ( BC_1 , AMS_B(1) , output3 , X , 45 , 0 , Z ) , " &
" 49 ( BC_2 , DR3PRI , input , X ) , " &
" 50 ( BC_1 , DR3PRI , output3 , X , 51 , 0 , Z ) , " &
" 51 ( BC_1 , * , control , 0 ) , " &
" 52 ( BC_2 , DR3SEC , input , X ) , " &
" 53 ( BC_1 , DR3SEC , output3 , X , 54 , 0 , Z ) , " &
" 54 ( BC_1 , * , control , 0 ) , " &
" 55 ( BC_2 , TSCLK3 , input , X ) , " &
" 56 ( BC_1 , TSCLK3 , output3 , X , 57 , 0 , Z ) , " &
" 57 ( BC_1 , * , control , 0 ) , " &
" 58 ( BC_1 , AMS_B(0) , output3 , X , 45 , 0 , Z ) , " &
" 59 ( BC_2 , MRX , input , X ) , " &
" 60 ( BC_1 , * , internal , 0 ) , " &
" 61 ( BC_1 , * , internal , 0 ) , " &
" 62 ( BC_2 , MTX , input , X ) , " &
" 63 ( BC_1 , MTX , output3 , X , 64 , 0 , Z ) , " &
" 64 ( BC_1 , * , control , 0 ) , " &
" 65 ( BC_2 , MFS , input , X ) , " &
" 66 ( BC_1 , MFS , output3 , X , 67 , 0 , Z ) , " &
" 67 ( BC_1 , * , control , 0 ) , " &
" 68 ( BC_1 , SA10 , output3 , X , 84 , 0 , Z ) , " &
" 69 ( BC_1 , SWE_B , output3 , X , 84 , 0 , Z ) , " &
" 70 ( BC_1 , SCAS_B , output3 , X , 84 , 0 , Z ) , " &
" 71 ( BC_1 , SRAS_B , output3 , X , 84 , 0 , Z ) , " &
" 72 ( BC_2 , TFS3 , input , X ) , " &
" 73 ( BC_1 , TFS3 , output3 , X , 74 , 0 , Z ) , " &
" 74 ( BC_1 , * , control , 0 ) , " &
" 75 ( BC_2 , DT3PRI , input , X ) , " &
" 76 ( BC_1 , DT3PRI , output3 , X , 77 , 0 , Z ) , " &
" 77 ( BC_1 , * , control , 0 ) , " &
" 78 ( BC_2 , DT3SEC , input , X ) , " &
" 79 ( BC_1 , DT3SEC , output3 , X , 80 , 0 , Z ) , " &
" 80 ( BC_1 , * , control , 0 ) , " &
" 81 ( BC_2 , BR_B , input , X ) , " &
" 82 ( BC_2 , ARDY , input , X ) , " &
" 83 ( BC_1 , CLKOUT , output3 , X , 84 , 0 , Z ) , " &
" 84 ( BC_1 , * , control , 0 ) , " &
" 85 ( BC_2 , MBCLK , input , X ) , " &
" 86 ( BC_1 , MBCLK , output3 , X , 87 , 0 , Z ) , " &
" 87 ( BC_1 , * , control , 0 ) , " &
" 88 ( BC_2 , MMCLK , input , X ) , " &
" 89 ( BC_1 , MMCLK , output3 , X , 90 , 0 , Z ) , " &
" 90 ( BC_1 , * , control , 0 ) , " &
" 91 ( BC_1 , SMS_B , output3 , X , 84 , 0 , Z ) , " &
" 92 ( BC_1 , SCKE , output3 , X , 84 , 0 , Z ) , " &
" 93 ( BC_2 , MRXON_B , input , X ) , " &
" 94 ( BC_1 , * , internal , 0 ) , " &
" 95 ( BC_1 , * , internal , 0 ) , " &
" 96 ( BC_2 , MTXON_B , input , X ) , " &
" 97 ( BC_1 , MTXON_B , output3 , X , 98 , 0 , Z ) , " &
" 98 ( BC_1 , * , control , 0 ) , " &
" 99 ( BC_2 , SDA1 , input , X ) , " &
" 100 ( BC_1 , SDA1 , output3 , X , 101 , 0 , Z ) , " &
" 101 ( BC_1 , * , control , 0 ) , " &
" 102 ( BC_2 , SCL1 , input , X ) , " &
" 103 ( BC_1 , SCL1 , output3 , X , 104 , 0 , Z ) , " &
" 104 ( BC_1 , * , control , 0 ) , " &
" 105 ( BC_2 , SCK1 , input , X ) , " &
" 106 ( BC_1 , SCK1 , output3 , X , 107 , 0 , Z ) , " &
" 107 ( BC_1 , * , control , 0 ) , " &
" 108 ( BC_2 , MISO1 , input , X ) , " &
" 109 ( BC_1 , MISO1 , output3 , X , 110 , 0 , Z ) , " &
" 110 ( BC_1 , * , control , 0 ) , " &
" 111 ( BC_2 , MOSI1 , input , X ) , " &
" 112 ( BC_1 , MOSI1 , output3 , X , 113 , 0 , Z ) , " &
" 113 ( BC_1 , * , control , 0 ) , " &
" 114 ( BC_2 , SPI1SS_B , input , X ) , " &
" 115 ( BC_1 , SPI1SS_B , output3 , X , 116 , 0 , Z ) , " &
" 116 ( BC_1 , * , control , 0 ) , " &
" 117 ( BC_2 , SPI1SEL1_B , input , X ) , " &
" 118 ( BC_1 , SPI1SEL1_B , output3 , X , 119 , 0 , Z ) , " &
" 119 ( BC_1 , * , control , 0 ) , " &
" 120 ( BC_2 , SCK2 , input , X ) , " &
" 121 ( BC_1 , SCK2 , output3 , X , 122 , 0 , Z ) , " &
" 122 ( BC_1 , * , control , 0 ) , " &
" 123 ( BC_2 , RESET_B , input , X ) , " &
" 124 ( BC_2 , NMI_B , input , X ) , " &
" 125 ( BC_2 , MISO2 , input , X ) , " &
" 126 ( BC_1 , MISO2 , output3 , X , 127 , 0 , Z ) , " &
" 127 ( BC_1 , * , control , 0 ) , " &
" 128 ( BC_2 , MOSI2 , input , X ) , " &
" 129 ( BC_1 , MOSI2 , output3 , X , 130 , 0 , Z ) , " &
" 130 ( BC_1 , * , control , 0 ) , " &
" 131 ( BC_2 , SPI2SS_B , input , X ) , " &
" 132 ( BC_1 , SPI2SS_B , output3 , X , 133 , 0 , Z ) , " &
" 133 ( BC_1 , * , control , 0 ) , " &
" 134 ( BC_2 , SPI2SEL1_B , input , X ) , " &
" 135 ( BC_1 , SPI2SEL1_B , output3 , X , 136 , 0 , Z ) , " &
" 136 ( BC_1 , * , control , 0 ) , " &
" 137 ( BC_2 , CANTX , input , X ) , " &
" 138 ( BC_1 , CANTX , output3 , X , 139 , 0 , Z ) , " &
" 139 ( BC_1 , * , control , 0 ) , " &
" 140 ( BC_2 , CANRX , input , X ) , " &
" 141 ( BC_1 , * , internal , 0 ) , " &
" 142 ( BC_1 , * , internal , 0 ) , " &
" 143 ( BC_2 , SDA0 , input , X ) , " &
" 144 ( BC_1 , SDA0 , output3 , X , 145 , 0 , Z ) , " &
" 145 ( BC_1 , * , control , 0 ) , " &
" 146 ( BC_2 , SCL0 , input , X ) , " &
" 147 ( BC_1 , SCL0 , output3 , X , 148 , 0 , Z ) , " &
" 148 ( BC_1 , * , control , 0 ) , " &
" 149 ( BC_2 , PPI_CLK , input , X ) , " &
" 150 ( BC_2 , TX1 , input , X ) , " &
" 151 ( BC_1 , TX1 , output3 , X , 152 , 0 , Z ) , " &
" 152 ( BC_1 , * , control , 0 ) , " &
" 153 ( BC_2 , RX1 , input , X ) , " &
" 154 ( BC_1 , RX1 , output3 , X , 155 , 0 , Z ) , " &
" 155 ( BC_1 , * , control , 0 ) , " &
" 156 ( BC_2 , PPI(0) , input , X ) , " &
" 157 ( BC_1 , PPI(0) , output3 , X , 158 , 0 , Z ) , " &
" 158 ( BC_1 , * , control , 0 ) , " &
" 159 ( BC_2 , PPI(1) , input , X ) , " &
" 160 ( BC_1 , PPI(1) , output3 , X , 161 , 0 , Z ) , " &
" 161 ( BC_1 , * , control , 0 ) , " &
" 162 ( BC_2 , PPI(2) , input , X ) , " &
" 163 ( BC_1 , PPI(2) , output3 , X , 164 , 0 , Z ) , " &
" 164 ( BC_1 , * , control , 0 ) , " &
" 165 ( BC_2 , PPI(3) , input , X ) , " &
" 166 ( BC_1 , PPI(3) , output3 , X , 167 , 0 , Z ) , " &
" 167 ( BC_1 , * , control , 0 ) , " &
" 168 ( BC_2 , PF(15) , input , X ) , " &
" 169 ( BC_1 , PF(15) , output3 , X , 170 , 0 , Z ) , " &
" 170 ( BC_1 , * , control , 0 ) , " &
" 171 ( BC_2 , PF(14) , input , X ) , " &
" 172 ( BC_1 , PF(14) , output3 , X , 173 , 0 , Z ) , " &
" 173 ( BC_1 , * , control , 0 ) , " &
" 174 ( BC_2 , PF(13) , input , X ) , " &
" 175 ( BC_1 , PF(13) , output3 , X , 176 , 0 , Z ) , " &
" 176 ( BC_1 , * , control , 0 ) , " &
" 177 ( BC_2 , PF(12) , input , X ) , " &
" 178 ( BC_1 , PF(12) , output3 , X , 179 , 0 , Z ) , " &
" 179 ( BC_1 , * , control , 0 ) , " &
" 180 ( BC_2 , PF(11) , input , X ) , " &
" 181 ( BC_1 , PF(11) , output3 , X , 182 , 0 , Z ) , " &
" 182 ( BC_1 , * , control , 0 ) , " &
" 183 ( BC_2 , PF(10) , input , X ) , " &
" 184 ( BC_1 , PF(10) , output3 , X , 185 , 0 , Z ) , " &
" 185 ( BC_1 , * , control , 0 ) , " &
" 186 ( BC_2 , PF(9) , input , X ) , " &
" 187 ( BC_1 , PF(9) , output3 , X , 188 , 0 , Z ) , " &
" 188 ( BC_1 , * , control , 0 ) , " &
" 189 ( BC_2 , PF(8) , input , X ) , " &
" 190 ( BC_1 , PF(8) , output3 , X , 191 , 0 , Z ) , " &
" 191 ( BC_1 , * , control , 0 ) , " &
" 192 ( BC_2 , PF(7) , input , X ) , " &
" 193 ( BC_1 , PF(7) , output3 , X , 194 , 0 , Z ) , " &
" 194 ( BC_1 , * , control , 0 ) , " &
" 195 ( BC_2 , SCK0 , input , X ) , " &
" 196 ( BC_1 , SCK0 , output3 , X , 197 , 0 , Z ) , " &
" 197 ( BC_1 , * , control , 0 ) , " &
" 198 ( BC_1 , DT1SEC , output3 , X , 199 , 0 , Z ) , " &
" 199 ( BC_1 , * , control , 0 ) , " &
" 200 ( BC_2 , MISO0 , input , X ) , " &
" 201 ( BC_1 , MISO0 , output3 , X , 202 , 0 , Z ) , " &
" 202 ( BC_1 , * , control , 0 ) , " &
" 203 ( BC_2 , MOSI0 , input , X ) , " &
" 204 ( BC_1 , MOSI0 , output3 , X , 205 , 0 , Z ) , " &
" 205 ( BC_1 , * , control , 0 ) , " &
" 206 ( BC_2 , PF(6) , input , X ) , " &
" 207 ( BC_1 , PF(6) , output3 , X , 208 , 0 , Z ) , " &
" 208 ( BC_1 , * , control , 0 ) , " &
" 209 ( BC_1 , DT1PRI , output3 , X , 210 , 0 , Z ) , " &
" 210 ( BC_1 , * , control , 0 ) , " &
" 211 ( BC_2 , TFS1 , input , X ) , " &
" 212 ( BC_1 , TFS1 , output3 , X , 213 , 0 , Z ) , " &
" 213 ( BC_1 , * , control , 0 ) , " &
" 214 ( BC_2 , TSCLK1 , input , X ) , " &
" 215 ( BC_1 , TSCLK1 , output3 , X , 216 , 0 , Z ) , " &
" 216 ( BC_1 , * , control , 0 ) , " &
" 217 ( BC_2 , PF(5) , input , X ) , " &
" 218 ( BC_1 , PF(5) , output3 , X , 219 , 0 , Z ) , " &
" 219 ( BC_1 , * , control , 0 ) , " &
" 220 ( BC_2 , PF(4) , input , X ) , " &
" 221 ( BC_1 , PF(4) , output3 , X , 222 , 0 , Z ) , " &
" 222 ( BC_1 , * , control , 0 ) , " &
" 223 ( BC_2 , PF(3) , input , X ) , " &
" 224 ( BC_1 , PF(3) , output3 , X , 225 , 0 , Z ) , " &
" 225 ( BC_1 , * , control , 0 ) , " &
" 226 ( BC_2 , PF(2) , input , X ) , " &
" 227 ( BC_1 , PF(2) , output3 , X , 228 , 0 , Z ) , " &
" 228 ( BC_1 , * , control , 0 ) , " &
" 229 ( BC_2 , PF(1) , input , X ) , " &
" 230 ( BC_1 , PF(1) , output3 , X , 231 , 0 , Z ) , " &
" 231 ( BC_1 , * , control , 0 ) , " &
" 232 ( BC_2 , PF(0) , input , X ) , " &
" 233 ( BC_1 , PF(0) , output3 , X , 234 , 0 , Z ) , " &
" 234 ( BC_1 , * , control , 0 ) , " &
" 235 ( BC_1 , DT0SEC , output3 , X , 236 , 0 , Z ) , " &
" 236 ( BC_1 , * , control , 0 ) , " &
" 237 ( BC_1 , DT0PRI , output3 , X , 238 , 0 , Z ) , " &
" 238 ( BC_1 , * , control , 0 ) , " &
" 239 ( BC_2 , TFS0 , input , X ) , " &
" 240 ( BC_1 , TFS0 , output3 , X , 241 , 0 , Z ) , " &
" 241 ( BC_1 , * , control , 0 ) , " &
" 242 ( BC_2 , TSCLK0 , input , X ) , " &
" 243 ( BC_1 , TSCLK0 , output3 , X , 244 , 0 , Z ) , " &
" 244 ( BC_1 , * , control , 0 ) , " &
" 245 ( BC_2 , DR1SEC , input , X ) , " &
" 246 ( BC_2 , DR1PRI , input , X ) , " &
" 247 ( BC_2 , RFS1 , input , X ) , " &
" 248 ( BC_1 , RFS1 , output3 , X , 249 , 0 , Z ) , " &
" 249 ( BC_1 , * , control , 0 ) , " &
" 250 ( BC_2 , DR0SEC , input , X ) , " &
" 251 ( BC_2 , DR0PRI , input , X ) , " &
" 252 ( BC_2 , RFS0 , input , X ) , " &
" 253 ( BC_1 , RFS0 , output3 , X , 254 , 0 , Z ) , " &
" 254 ( BC_1 , * , control , 0 ) , " &
" 255 ( BC_2 , RSCLK0 , input , X ) , " &
" 256 ( BC_1 , RSCLK0 , output3 , X , 257 , 0 , Z ) , " &
" 257 ( BC_1 , * , control , 0 ) , " &
" 258 ( BC_2 , TMR2 , input , X ) , " &
" 259 ( BC_1 , TMR2 , output3 , X , 260 , 0 , Z ) , " &
" 260 ( BC_1 , * , control , 0 ) , " &
" 261 ( BC_2 , TMR1 , input , X ) , " &
" 262 ( BC_1 , TMR1 , output3 , X , 263 , 0 , Z ) , " &
" 263 ( BC_1 , * , control , 0 ) , " &
" 264 ( BC_2 , TMR0 , input , X ) , " &
" 265 ( BC_1 , TMR0 , output3 , X , 266 , 0 , Z ) , " &
" 266 ( BC_1 , * , control , 0 ) , " &
" 267 ( BC_2 , RSCLK1 , input , X ) , " &
" 268 ( BC_1 , RSCLK1 , output3 , X , 269 , 0 , Z ) , " &
" 269 ( BC_1 , * , control , 0 ) , " &
" 270 ( BC_1 , TX0 , output2 , X ) , " &
" 271 ( BC_2 , RX0 , input , X ) , " &
" 272 ( BC_2 , BMODE(1) , input , X ) , " &
" 273 ( BC_2 , BMODE(0) , input , X ) , " &
" 274 ( BC_2 , DATA(15) , input , X ) , " &
" 275 ( BC_1 , DATA(15) , output3 , X , 324 , 0 , Z ) , " &
" 276 ( BC_2 , DATA(14) , input , X ) , " &
" 277 ( BC_1 , DATA(14) , output3 , X , 324 , 0 , Z ) , " &
" 278 ( BC_2 , DATA(13) , input , X ) , " &
" 279 ( BC_1 , DATA(13) , output3 , X , 324 , 0 , Z ) , " &
" 280 ( BC_2 , DATA(12) , input , X ) , " &
" 281 ( BC_1 , DATA(12) , output3 , X , 324 , 0 , Z ) , " &
" 282 ( BC_2 , RX2 , input , X ) , " &
" 283 ( BC_1 , RX2 , output3 , X , 284 , 0 , Z ) , " &
" 284 ( BC_1 , * , control , 0 ) , " &
" 285 ( BC_2 , RSCLK2 , input , X ) , " &
" 286 ( BC_1 , RSCLK2 , output3 , X , 287 , 0 , Z ) , " &
" 287 ( BC_1 , * , control , 0 ) , " &
" 288 ( BC_2 , DATA(11) , input , X ) , " &
" 289 ( BC_1 , DATA(11) , output3 , X , 324 , 0 , Z ) , " &
" 290 ( BC_2 , DATA(10) , input , X ) , " &
" 291 ( BC_1 , DATA(10) , output3 , X , 324 , 0 , Z ) , " &
" 292 ( BC_2 , DATA(9) , input , X ) , " &
" 293 ( BC_1 , DATA(9) , output3 , X , 324 , 0 , Z ) , " &
" 294 ( BC_2 , DATA(8) , input , X ) , " &
" 295 ( BC_1 , DATA(8) , output3 , X , 324 , 0 , Z ) , " &
" 296 ( BC_2 , DATA(7) , input , X ) , " &
" 297 ( BC_1 , DATA(7) , output3 , X , 324 , 0 , Z ) , " &
" 298 ( BC_2 , RFS2 , input , X ) , " &
" 299 ( BC_1 , RFS2 , output3 , X , 300 , 0 , Z ) , " &
" 300 ( BC_1 , * , control , 0 ) , " &
" 301 ( BC_2 , DATA(6) , input , X ) , " &
" 302 ( BC_1 , DATA(6) , output3 , X , 324 , 0 , Z ) , " &
" 303 ( BC_2 , DATA(5) , input , X ) , " &
" 304 ( BC_1 , DATA(5) , output3 , X , 324 , 0 , Z ) , " &
" 305 ( BC_2 , DATA(4) , input , X ) , " &
" 306 ( BC_1 , DATA(4) , output3 , X , 324 , 0 , Z ) , " &
" 307 ( BC_2 , DATA(3) , input , X ) , " &
" 308 ( BC_1 , DATA(3) , output3 , X , 324 , 0 , Z ) , " &
" 309 ( BC_2 , DR2PRI , input , X ) , " &
" 310 ( BC_1 , DR2PRI , output3 , X , 311 , 0 , Z ) , " &
" 311 ( BC_1 , * , control , 0 ) , " &
" 312 ( BC_2 , DR2SEC , input , X ) , " &
" 313 ( BC_1 , DR2SEC , output3 , X , 314 , 0 , Z ) , " &
" 314 ( BC_1 , * , control , 0 ) , " &
" 315 ( BC_2 , TSCLK2 , input , X ) , " &
" 316 ( BC_1 , TSCLK2 , output3 , X , 317 , 0 , Z ) , " &
" 317 ( BC_1 , * , control , 0 ) , " &
" 318 ( BC_2 , DATA(2) , input , X ) , " &
" 319 ( BC_1 , DATA(2) , output3 , X , 324 , 0 , Z ) , " &
" 320 ( BC_2 , DATA(1) , input , X ) , " &
" 321 ( BC_1 , DATA(1) , output3 , X , 324 , 0 , Z ) , " &
" 322 ( BC_2 , DATA(0) , input , X ) , " &
" 323 ( BC_1 , DATA(0) , output3 , X , 324 , 0 , Z ) , " &
" 324 ( BC_1 , * , control , 0 ) ";
end ADSP_BF539;