-- Generated by boundaryScanGenerate 4.2-Build20040928.017 on 06/09/05 12:01:25
-- BSDL Version 2001
entity dp83849i is
generic (PHYSICAL_PIN_MAP : string := "DEFAULT_PACKAGE_NAME");
port (
-- Port List
IO_VSS4 : linkage bit;
IO_VDD4 : linkage bit;
RX_CLK_A : inout bit;
RX_DV_A : inout bit;
CRS_A : inout bit;
RX_ER_A : inout bit;
COL_A : inout bit;
RXD_0_A : inout bit;
RXD_1_A : inout bit;
CORE_VSS1 : linkage bit;
CORE_VDD1 : linkage bit;
RXD_2_A : inout bit;
RXD_3_A : inout bit;
IO_VSS1 : linkage bit;
IO_VDD1 : linkage bit;
TX_CLK_A : inout bit;
TX_EN_A : inout bit;
TXD_0_A : inout bit;
TXD_1_A : inout bit;
TXD_2_A : inout bit;
TXD_3_A : inout bit;
PWRDN_INTN_A : inout bit;
LED_LNK_A : inout bit;
LED_SPD_A : inout bit;
LED_ACTCOL_A : inout bit;
ANA18VSS1_A : linkage bit;
TPRDM_A : linkage bit;
TPRDP_A : linkage bit;
CDVSS_A : linkage bit;
TPTDM_A : linkage bit;
TPTDP_A : linkage bit;
ANA18VDD_A : linkage bit;
ANA18VSS2_A : linkage bit;
ANA33VDD : linkage bit;
REG_OUT : linkage bit;
VREF : linkage bit;
ANA18VSS2_B : linkage bit;
ANA18VDD_B : linkage bit;
TPTDP_B : linkage bit;
TPTDM_B : linkage bit;
CDVSS_B : linkage bit;
TPRDP_B : linkage bit;
TPRDM_B : linkage bit;
ANA18VSS1_B : linkage bit;
LED_ACTCOL_B : inout bit;
LED_SPD_B : inout bit;
LED_LNK_B : inout bit;
PWRDN_INTN_B : inout bit;
TXD_3_B : inout bit;
TXD_2_B : inout bit;
TXD_1_B : inout bit;
TXD_0_B : inout bit;
TX_EN_B : inout bit;
TX_CLK_B : inout bit;
IO_VDD2 : linkage bit;
IO_VSS2 : linkage bit;
RXD_3_B : inout bit;
RXD_2_B : inout bit;
CORE_VDD2 : linkage bit;
CORE_VSS2 : linkage bit;
RXD_1_B : inout bit;
RXD_0_B : inout bit;
COL_B : inout bit;
RX_ER_B : inout bit;
CRS_B : inout bit;
RX_DV_B : inout bit;
RX_CLK_B : inout bit;
IO_VSS3 : linkage bit;
IO_VDD3 : linkage bit;
MDIO : inout bit;
MDC : in bit;
CLK2MAC : inout bit;
X2 : linkage bit;
X1 : linkage bit;
RESET_N : in bit;
TCK : in bit;
TDO : out bit;
TMS : in bit;
TRST_N : in bit;
TDI : in bit);
use STD_1149_1_2001.all;
use LVS_BSCAN_CELLS.all;
attribute COMPONENT_CONFORMANCE of dp83849i: entity is "STD_1149_1_2001";
--Pin mappings
attribute PIN_MAP of dp83849i: entity is PHYSICAL_PIN_MAP;
constant DEFAULT_PACKAGE_NAME: PIN_MAP_STRING :=
"IO_VSS4 : 77 , " &
"IO_VDD4 : 78 , " &
"RX_CLK_A : 79 , " &
"RX_DV_A : 80 , " &
"CRS_A : 1 , " &
"RX_ER_A : 2 , " &
"COL_A : 3 , " &
"RXD_0_A : 4 , " &
"RXD_1_A : 5 , " &
"CORE_VSS1 : 6 , " &
"CORE_VDD1 : 7 , " &
"RXD_2_A : 8 , " &
"RXD_3_A : 9 , " &
"IO_VSS1 : 10 , " &
"IO_VDD1 : 11 , " &
"TX_CLK_A : 12 , " &
"TX_EN_A : 13 , " &
"TXD_0_A : 14 , " &
"TXD_1_A : 15 , " &
"TXD_2_A : 16 , " &
"TXD_3_A : 17 , " &
"PWRDN_INTN_A : 18 , " &
"LED_LNK_A : 19 , " &
"LED_SPD_A : 20 , " &
"LED_ACTCOL_A : 21 , " &
"ANA18VSS1_A : 22 , " &
"TPRDM_A : 23 , " &
"TPRDP_A : 24 , " &
"CDVSS_A : 25 , " &
"TPTDM_A : 26 , " &
"TPTDP_A : 27 , " &
"ANA18VDD_A : 28 , " &
"ANA18VSS2_A : 29 , " &
"ANA33VDD : 30 , " &
"REG_OUT : 31 , " &
"VREF : 32 , " &
"ANA18VSS2_B : 33 , " &
"ANA18VDD_B : 34 , " &
"TPTDP_B : 35 , " &
"TPTDM_B : 36 , " &
"CDVSS_B : 37 , " &
"TPRDP_B : 38 , " &
"TPRDM_B : 39 , " &
"ANA18VSS1_B : 40 , " &
"LED_ACTCOL_B : 41 , " &
"LED_SPD_B : 42 , " &
"LED_LNK_B : 43 , " &
"PWRDN_INTN_B : 44 , " &
"TXD_3_B : 45 , " &
"TXD_2_B : 46 , " &
"TXD_1_B : 47 , " &
"TXD_0_B : 48 , " &
"TX_EN_B : 49 , " &
"TX_CLK_B : 50 , " &
"IO_VDD2 : 51 , " &
"IO_VSS2 : 52 , " &
"RXD_3_B : 53 , " &
"CORE_VDD2 : 54 , " &
"CORE_VSS2 : 55 , " &
"RXD_2_B : 56 , " &
"RXD_1_B : 57 , " &
"RXD_0_B : 58 , " &
"COL_B : 59 , " &
"RX_ER_B : 60 , " &
"CRS_B : 61 , " &
"RX_DV_B : 62 , " &
"RX_CLK_B : 63 , " &
"IO_VSS3 : 64 , " &
"IO_VDD3 : 65 , " &
"MDIO : 66 , " &
"MDC : 67 , " &
"CLK2MAC : 68 , " &
"X2 : 69 , " &
"X1 : 70 , " &
"RESET_N : 71 , " &
"TCK : 72 , " &
"TDO : 73 , " &
"TMS : 74 , " &
"TRST_N : 75 , " &
"TDI : 76 " ;
attribute TAP_SCAN_RESET of TRST_N : signal is true;
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_CLOCK of TCK : signal is (1.0000000000000000000e+07, BOTH);
attribute INSTRUCTION_LENGTH of dp83849i: entity is 5;
attribute INSTRUCTION_OPCODE of dp83849i: entity is
"IDCODE (11110)," &
"BYPASS (11111)," &
"EXTEST (11001)," &
"SAMPLE (11000)," &
"PRELOAD (11000)," &
"HIGHZ (11011) " ;
attribute INSTRUCTION_CAPTURE of dp83849i: entity is "xxx01";
attribute IDCODE_REGISTER of dp83849i: entity is
"0000" & -- version
"1000000000100000" & -- part number
"00000001111" & -- manufacturer's identity
"1"; -- required by 1149.1
attribute REGISTER_ACCESS of dp83849i: entity is
"BOUNDARY ( SAMPLE, PRELOAD )," &
"BYPASS (HIGHZ) " ;
--Boundary scan definition
attribute BOUNDARY_LENGTH of dp83849i: entity is 82;
attribute BOUNDARY_REGISTER of dp83849i: entity is
-- num cell port function safe [ccell disval rslt]
" 81 (BC_2 , * , control , 0 ) ,"&
" 80 (LV_BC_7 , RX_CLK_A , bidir , X , 81 , 0 , Z ),"&
" 79 (BC_2 , * , control , 0 ) ,"&
" 78 (LV_BC_7 , RX_DV_A , bidir , X , 79 , 0 , Z ),"&
" 77 (BC_2 , * , control , 0 ) ,"&
" 76 (LV_BC_7 , CRS_A , bidir , X , 77 , 0 , Z ),"&
" 75 (BC_2 , * , control , 0 ) ,"&
" 74 (LV_BC_7 , RX_ER_A , bidir , X , 75 , 0 , Z ),"&
" 73 (BC_2 , * , control , 0 ) ,"&
" 72 (LV_BC_7 , COL_A , bidir , X , 73 , 0 , Z ),"&
" 71 (BC_2 , * , control , 0 ) ,"&
" 70 (LV_BC_7 , RXD_0_A , bidir , X , 71 , 0 , Z ),"&
" 69 (BC_2 , * , control , 0 ) ,"&
" 68 (LV_BC_7 , RXD_1_A , bidir , X , 69 , 0 , Z ),"&
" 67 (BC_2 , * , control , 0 ) ,"&
" 66 (LV_BC_7 , RXD_2_A , bidir , X , 67 , 0 , Z ),"&
" 65 (BC_2 , * , control , 0 ) ,"&
" 64 (LV_BC_7 , RXD_3_A , bidir , X , 65 , 0 , Z ),"&
" 63 (BC_2 , * , control , 0 ) ,"&
" 62 (LV_BC_7 , TX_CLK_A , bidir , X , 63 , 0 , Z ),"&
" 61 (BC_2 , * , control , 0 ) ,"&
" 60 (LV_BC_7 , TX_EN_A , bidir , X , 61 , 0 , Z ),"&
" 59 (BC_2 , * , control , 0 ) ,"&
" 58 (LV_BC_7 , TXD_0_A , bidir , X , 59 , 0 , Z ),"&
" 57 (BC_2 , * , control , 0 ) ,"&
" 56 (LV_BC_7 , TXD_1_A , bidir , X , 57 , 0 , Z ),"&
" 55 (BC_2 , * , control , 0 ) ,"&
" 54 (LV_BC_7 , TXD_2_A , bidir , X , 55 , 0 , Z ),"&
" 53 (BC_2 , * , control , 0 ) ,"&
" 52 (LV_BC_7 , TXD_3_A , bidir , X , 53 , 0 , Z ),"&
" 51 (BC_2 , * , control , 0 ) ,"&
" 50 (LV_BC_7 , PWRDN_INTN_A , bidir , X , 51 , 0 , Z ),"&
" 49 (BC_2 , * , control , 0 ) ,"&
" 48 (LV_BC_7 , LED_LNK_A , bidir , X , 49 , 0 , Z ),"&
" 47 (BC_2 , * , control , 0 ) ,"&
" 46 (LV_BC_7 , LED_SPD_A , bidir , X , 47 , 0 , Z ),"&
" 45 (BC_2 , * , control , 0 ) ,"&
" 44 (LV_BC_7 , LED_ACTCOL_A , bidir , X , 45 , 0 , Z ),"&
" 43 (BC_2 , * , control , 0 ) ,"&
" 42 (LV_BC_7 , LED_ACTCOL_B , bidir , X , 43 , 0 , Z ),"&
" 41 (BC_2 , * , control , 0 ) ,"&
" 40 (LV_BC_7 , LED_SPD_B , bidir , X , 41 , 0 , Z ),"&
" 39 (BC_2 , * , control , 0 ) ,"&
" 38 (LV_BC_7 , LED_LNK_B , bidir , X , 39 , 0 , Z ),"&
" 37 (BC_2 , * , control , 0 ) ,"&
" 36 (LV_BC_7 , PWRDN_INTN_B , bidir , X , 37 , 0 , Z ),"&
" 35 (BC_2 , * , control , 0 ) ,"&
" 34 (LV_BC_7 , TXD_3_B , bidir , X , 35 , 0 , Z ),"&
" 33 (BC_2 , * , control , 0 ) ,"&
" 32 (LV_BC_7 , TXD_2_B , bidir , X , 33 , 0 , Z ),"&
" 31 (BC_2 , * , control , 0 ) ,"&
" 30 (LV_BC_7 , TXD_1_B , bidir , X , 31 , 0 , Z ),"&
" 29 (BC_2 , * , control , 0 ) ,"&
" 28 (LV_BC_7 , TXD_0_B , bidir , X , 29 , 0 , Z ),"&
" 27 (BC_2 , * , control , 0 ) ,"&
" 26 (LV_BC_7 , TX_EN_B , bidir , X , 27 , 0 , Z ),"&
" 25 (BC_2 , * , control , 0 ) ,"&
" 24 (LV_BC_7 , TX_CLK_B , bidir , X , 25 , 0 , Z ),"&
" 23 (BC_2 , * , control , 0 ) ,"&
" 22 (LV_BC_7 , RXD_3_B , bidir , X , 23 , 0 , Z ),"&
" 21 (BC_2 , * , control , 0 ) ,"&
" 20 (LV_BC_7 , RXD_2_B , bidir , X , 21 , 0 , Z ),"&
" 19 (BC_2 , * , control , 0 ) ,"&
" 18 (LV_BC_7 , RXD_1_B , bidir , X , 19 , 0 , Z ),"&
" 17 (BC_2 , * , control , 0 ) ,"&
" 16 (LV_BC_7 , RXD_0_B , bidir , X , 17 , 0 , Z ),"&
" 15 (BC_2 , * , control , 0 ) ,"&
" 14 (LV_BC_7 , COL_B , bidir , X , 15 , 0 , Z ),"&
" 13 (BC_2 , * , control , 0 ) ,"&
" 12 (LV_BC_7 , RX_ER_B , bidir , X , 13 , 0 , Z ),"&
" 11 (BC_2 , * , control , 0 ) ,"&
" 10 (LV_BC_7 , CRS_B , bidir , X , 11 , 0 , Z ),"&
" 9 (BC_2 , * , control , 0 ) ,"&
" 8 (LV_BC_7 , RX_DV_B , bidir , X , 9 , 0 , Z ),"&
" 7 (BC_2 , * , control , 0 ) ,"&
" 6 (LV_BC_7 , RX_CLK_B , bidir , X , 7 , 0 , Z ),"&
" 5 (BC_2 , * , control , 0 ) ,"&
" 4 (LV_BC_7 , MDIO , bidir , X , 5 , 0 , Z ),"&
" 3 (BC_2 , MDC , input , X ) ,"&
" 2 (BC_2 , * , control , 0 ) ,"&
" 1 (LV_BC_7 , CLK2MAC , bidir , X , 2 , 0 , Z ),"&
" 0 (BC_2 , RESET_N , input , X ) ";
end dp83849i;