-- BSDL listing from io_top_create.pl, Fri Sep 20 19:42:08 2013
--
-- pins not part of boundary scan are listed as type 'linkage'
entity LPC15xx is
generic (PHYSICAL_PIN_MAP : string := "LQFP64");
port (
P0_30 : inout bit; -- P0_30_ADC0_11
P0_0 : inout bit; -- P0_0_ADC0_10
P0_31 : inout bit; -- P0_31_ADC0_9
P1_0 : inout bit; -- P1_0_ADC0_8
P0_1 : inout bit; -- P0_1_ADC0_7
P0_2 : inout bit; -- P0_2_ADC0_6
P0_3 : inout bit; -- P0_3_ADC0_5
P0_4 : inout bit; -- P0_4_ADC0_4
P0_5 : inout bit; -- P0_5_ADC0_3
P0_6 : inout bit; -- P0_6_ADC0_2
P0_7 : inout bit; -- P0_7_ADC0_1
P0_8 : out bit; -- P0_8_ADC0_0_TDO
VREFP_ADC1 : linkage bit; -- VREFP_ADC
VREFN_DAC1 : linkage bit; -- VREFN_DAC_VREFN_ADC
P1_1 : inout bit; -- P1_1_ADC1_0
P0_9 : in bit; -- P0_9_ADC1_1_TDI
P0_18 : inout bit; -- P0_18
VREFCMP : linkage bit; -- VREFCMP_VREFP_DAC
P0_10 : inout bit; -- P0_10_ADC1_2
VDDA1 : linkage bit; -- VDDA
VSSA1 : linkage bit; -- VSSA
vdde1 : linkage bit; -- VDDIO
P0_11 : inout bit; -- P0_11_ADC1_3
DAC_VOUT : linkage bit; -- DAC_VOUT_P0_12
P1_2 : inout bit; -- P1_2_ADC1_4
gnd1 : linkage bit; -- VSSIO
gnd2 : linkage bit; -- GND
P1_3 : inout bit; -- P1_3_ADC1_5
P0_13 : inout bit; -- P0_13_ADC1_6
P0_14 : inout bit; -- P0_14_ADC1_7
P0_15 : inout bit; -- P0_15_ADC1_8
P0_16 : inout bit; -- P0_16_ADC1_9
P1_4 : inout bit; -- P1_4_ADC1_10
P1_5 : inout bit; -- P1_5_ADC1_11
XTALOUT : linkage bit; -- XTALOUT
XTALIN : linkage bit; -- XTALIN
VDDMAIN_EXT1 : linkage bit; -- VDDMAIN_EXT
P1_11 : inout bit; -- P1_11
P0_17 : in bit; -- P0_17_WAKEUP_TRSTN
P0_19 : in bit; -- SWCLK_P0_19_TCK
VBAT1 : linkage bit; -- VBAT
RTCX1 : linkage bit; -- RTCX1
RTCX2 : linkage bit; -- RTCX2
P0_20 : in bit; -- SWDIO_P0_20_TMS
P0_21 : in bit; -- RESETN_P0_21
P1_6 : inout bit; -- P1_6_COMP_COM1
USB_DP : linkage bit; -- USB_DP
USB_DM : linkage bit; -- USB_DM
P0_22 : inout bit; -- P0_22_SCL
P0_23 : inout bit; -- P0_23_SDA
P1_7 : inout bit; -- P1_7_COMP3_1
vdde2 : linkage bit; -- VDDIO
P1_8 : inout bit; -- P1_8_COMP3_0
P1_9 : inout bit; -- P1_9_COMP2_1
gnd3 : linkage bit; -- VSSIO
gnd4 : linkage bit; -- GND
VDDMAIN_EXT21 : linkage bit; -- VDDMAIN_EXT
P0_24 : inout bit; -- P0_24_20MA
P1_10 : inout bit; -- P1_10_COMP1_1
P0_25 : inout bit; -- P0_25_COMP0_1
P0_26 : inout bit; -- P0_26_COMP0_0
P0_27 : inout bit; -- P0_27_COMP_COM0
P0_28 : inout bit; -- P0_28_COMP1_0
P0_29 : inout bit -- P0_29_COMP2_0
);
use STD_1149_1_2001.all;
attribute COMPONENT_CONFORMANCE of LPC15xx : entity is "std_1149_1_2001";
attribute PIN_MAP of LPC15xx : entity is PHYSICAL_PIN_MAP;
constant LQFP64 : PIN_MAP_STRING :=
"P0_30 : 1," &
"P0_0 : 2," &
"P0_31 : 3," &
"P1_0 : 4," &
"P0_1 : 5," &
"P0_2 : 6," &
"P0_3 : 7," &
"P0_4 : 8," &
"P0_5 : 9," &
"P0_6 : 10," &
"P0_7 : 11," &
"P0_8 : 12," &
"VREFP_ADC1 : 13," &
"VREFN_DAC1 : 14," &
"P1_1 : 15," &
"P0_9 : 16," &
"P0_18 : 17," &
"VREFCMP : 18," &
"P0_10 : 19," &
"VDDA1 : 20," &
"VSSA1 : 21," &
"vdde1 : 22," &
"P0_11 : 23," &
"DAC_VOUT : 24," &
"P1_2 : 25," &
"gnd1 : 26," &
"gnd2 : 27," &
"P1_3 : 28," &
"P0_13 : 29," &
"P0_14 : 30," &
"P0_15 : 31," &
"P0_16 : 32," &
"P1_4 : 33," &
"P1_5 : 34," &
"XTALOUT : 35," &
"XTALIN : 36," &
"VDDMAIN_EXT1 : 37," &
"P1_11 : 38," &
"P0_17 : 39," &
"P0_19 : 40," &
"VBAT1 : 41," &
"RTCX1 : 42," &
"RTCX2 : 43," &
"P0_20 : 44," &
"P0_21 : 45," &
"P1_6 : 46," &
"USB_DP : 47," &
"USB_DM : 48," &
"P0_22 : 49," &
"P0_23 : 50," &
"P1_7 : 51," &
"vdde2 : 52," &
"P1_8 : 53," &
"P1_9 : 54," &
"gnd3 : 55," &
"gnd4 : 56," &
"VDDMAIN_EXT21 : 57," &
"P0_24 : 58," &
"P1_10 : 59," &
"P0_25 : 60," &
"P0_26 : 61," &
"P0_27 : 62," &
"P0_28 : 63," &
"P0_29 : 64";
-- *********************************************************************
-- * IEEE 1149.1 TAP PORTS *
-- *********************************************************************
-- This section specifies the TAP ports. For the TAP TCK port, the
-- parameters in the brackets are:
-- First Field : Maximum TCK frequency.
-- Second Field: Allowable states where TCK may be stopped.
attribute TAP_SCAN_CLOCK of P0_19 : signal is (10.00e+06,BOTH);
attribute TAP_SCAN_IN of P0_9 : signal is true;
attribute TAP_SCAN_MODE of P0_20 : signal is true;
attribute TAP_SCAN_OUT of P0_8 : signal is true;
attribute TAP_SCAN_RESET of P0_17 : signal is true;
-- Specifies the compliance enable patterns for the design. It lists a set of
-- design ports and the values that they should be set to, in order to enable
-- compliance to IEEE Std 1149.1
attribute COMPLIANCE_PATTERNS of LPC15xx: entity is
"(P0_21) (0)";
-- *********************************************************************
-- * INSTRUCTIONS AND REGISTER ACCESS *
-- *********************************************************************
attribute INSTRUCTION_LENGTH of LPC15xx : entity is 5;
attribute INSTRUCTION_OPCODE of LPC15xx : entity is
"extest (00000)," &
"sample (00001)," &
"preload (00001)," &
"highz (00010)," &
"clamp (00011)," &
"idcode (00100)," &
"resrvd (00101, 00110, 00111, 01000, 01001, 01010, 01011, 01100)," &
"bypass (11111)";
attribute INSTRUCTION_CAPTURE of LPC15xx : entity is "00001";
attribute INSTRUCTION_PRIVATE of LPC15xx : entity is "resrvd";
attribute IDCODE_REGISTER of LPC15xx : entity is
"00xx" & -- Version Number
"1001110101101100" & -- Part Number
"00000010101" & -- Manufacturer ID
"1"; -- Required by IEEE
attribute REGISTER_ACCESS of LPC15xx : entity is
"BOUNDARY (extest, sample, preload), " &
"DEVICE_ID (idcode), " &
"BYPASS (highz, clamp, bypass)";
-- *********************************************************************
-- * BOUNDARY SCAN CELL INFORMATION *
-- *********************************************************************
attribute BOUNDARY_LENGTH of LPC15xx : entity is 216;
attribute BOUNDARY_REGISTER of LPC15xx : entity is
-- # cell name function safe control disable disable
-- type bit signal value result
"215 (BC_0, * , INTERNAL, X ),"&
"214 (BC_0, * , INTERNAL, X ),"&
"213 (BC_0, * , INTERNAL, X ),"&
"212 (BC_4, P0_18 , INPUT, X ),"&
"211 (BC_1, P0_18 , OUTPUT3, X, 210, 0, Z ),"&
"210 (BC_1, * , CONTROL, 0 ),"&
"209 (BC_4, P0_10 , INPUT, X ),"&
"208 (BC_1, P0_10 , OUTPUT3, X, 207, 0, Z ),"&
"207 (BC_1, * , CONTROL, 0 ),"&
"206 (BC_0, * , INTERNAL, X ),"&
"205 (BC_0, * , INTERNAL, X ),"&
"204 (BC_0, * , INTERNAL, X ),"&
"203 (BC_4, P0_11 , INPUT, X ),"&
"202 (BC_1, P0_11 , OUTPUT3, X, 201, 0, Z ),"&
"201 (BC_1, * , CONTROL, 0 ),"&
"200 (BC_0, * , INTERNAL, X ),"&
"199 (BC_0, * , INTERNAL, X ),"&
"198 (BC_0, * , INTERNAL, X ),"&
"197 (BC_0, * , INTERNAL, X ),"&
"196 (BC_0, * , INTERNAL, X ),"&
"195 (BC_0, * , INTERNAL, X ),"&
"194 (BC_4, P1_2 , INPUT, X ),"&
"193 (BC_1, P1_2 , OUTPUT3, X, 192, 0, Z ),"&
"192 (BC_1, * , CONTROL, 0 ),"&
"191 (BC_0, * , INTERNAL, X ),"&
"190 (BC_0, * , INTERNAL, X ),"&
"189 (BC_0, * , INTERNAL, X ),"&
"188 (BC_0, * , INTERNAL, X ),"&
"187 (BC_0, * , INTERNAL, X ),"&
"186 (BC_0, * , INTERNAL, X ),"&
"185 (BC_4, P1_3 , INPUT, X ),"&
"184 (BC_1, P1_3 , OUTPUT3, X, 183, 0, Z ),"&
"183 (BC_1, * , CONTROL, 0 ),"&
"182 (BC_0, * , INTERNAL, X ),"&
"181 (BC_0, * , INTERNAL, X ),"&
"180 (BC_0, * , INTERNAL, X ),"&
"179 (BC_4, P0_13 , INPUT, X ),"&
"178 (BC_1, P0_13 , OUTPUT3, X, 177, 0, Z ),"&
"177 (BC_1, * , CONTROL, 0 ),"&
"176 (BC_0, * , INTERNAL, X ),"&
"175 (BC_0, * , INTERNAL, X ),"&
"174 (BC_0, * , INTERNAL, X ),"&
"173 (BC_4, P0_14 , INPUT, X ),"&
"172 (BC_1, P0_14 , OUTPUT3, X, 171, 0, Z ),"&
"171 (BC_1, * , CONTROL, 0 ),"&
"170 (BC_0, * , INTERNAL, X ),"&
"169 (BC_0, * , INTERNAL, X ),"&
"168 (BC_0, * , INTERNAL, X ),"&
"167 (BC_4, P0_15 , INPUT, X ),"&
"166 (BC_1, P0_15 , OUTPUT3, X, 165, 0, Z ),"&
"165 (BC_1, * , CONTROL, 0 ),"&
"164 (BC_0, * , INTERNAL, X ),"&
"163 (BC_0, * , INTERNAL, X ),"&
"162 (BC_0, * , INTERNAL, X ),"&
"161 (BC_4, P0_16 , INPUT, X ),"&
"160 (BC_1, P0_16 , OUTPUT3, X, 159, 0, Z ),"&
"159 (BC_1, * , CONTROL, 0 ),"&
"158 (BC_0, * , INTERNAL, X ),"&
"157 (BC_0, * , INTERNAL, X ),"&
"156 (BC_0, * , INTERNAL, X ),"&
"155 (BC_4, P1_4 , INPUT, X ),"&
"154 (BC_1, P1_4 , OUTPUT3, X, 153, 0, Z ),"&
"153 (BC_1, * , CONTROL, 0 ),"&
"152 (BC_4, P1_5 , INPUT, X ),"&
"151 (BC_1, P1_5 , OUTPUT3, X, 150, 0, Z ),"&
"150 (BC_1, * , CONTROL, 0 ),"&
"149 (BC_0, * , INTERNAL, X ),"&
"148 (BC_0, * , INTERNAL, X ),"&
"147 (BC_0, * , INTERNAL, X ),"&
"146 (BC_0, * , INTERNAL, X ),"&
"145 (BC_0, * , INTERNAL, X ),"&
"144 (BC_0, * , INTERNAL, X ),"&
"143 (BC_4, P1_11 , INPUT, X ),"&
"142 (BC_1, P1_11 , OUTPUT3, X, 141, 0, Z ),"&
"141 (BC_1, * , CONTROL, 0 ),"&
"140 (BC_0, * , INTERNAL, X ),"&
"139 (BC_0, * , INTERNAL, X ),"&
"138 (BC_0, * , INTERNAL, X ),"&
"137 (BC_0, * , INTERNAL, X ),"&
"136 (BC_0, * , INTERNAL, X ),"&
"135 (BC_0, * , INTERNAL, X ),"&
"134 (BC_0, * , INTERNAL, X ),"&
"133 (BC_0, * , INTERNAL, X ),"&
"132 (BC_0, * , INTERNAL, X ),"&
"131 (BC_0, * , INTERNAL, X ),"&
"130 (BC_0, * , INTERNAL, X ),"&
"129 (BC_0, * , INTERNAL, X ),"&
"128 (BC_0, * , INTERNAL, X ),"&
"127 (BC_0, * , INTERNAL, X ),"&
"126 (BC_0, * , INTERNAL, X ),"&
"125 (BC_4, P1_6 , INPUT, X ),"&
"124 (BC_1, P1_6 , OUTPUT3, X, 123, 0, Z ),"&
"123 (BC_1, * , CONTROL, 0 ),"&
"122 (BC_0, * , INTERNAL, X ),"&
"121 (BC_0, * , INTERNAL, X ),"&
"120 (BC_0, * , INTERNAL, X ),"&
"119 (BC_0, * , INTERNAL, X ),"&
"118 (BC_0, * , INTERNAL, X ),"&
"117 (BC_0, * , INTERNAL, X ),"&
"116 (BC_0, * , INTERNAL, X ),"&
"115 (BC_0, * , INTERNAL, X ),"&
"114 (BC_0, * , INTERNAL, X ),"&
"113 (BC_0, * , INTERNAL, X ),"&
"112 (BC_0, * , INTERNAL, X ),"&
"111 (BC_0, * , INTERNAL, X ),"&
"110 (BC_4, P0_22 , INPUT, X ),"&
"109 (BC_1, P0_22 , OUTPUT3, X, 108, 0, WEAK1 ),"&
"108 (BC_1, * , CONTROL, 0 ),"&
"107 (BC_4, P0_23 , INPUT, X ),"&
"106 (BC_1, P0_23 , OUTPUT3, X, 105, 0, WEAK1 ),"&
"105 (BC_1, * , CONTROL, 0 ),"&
"104 (BC_0, * , INTERNAL, X ),"&
"103 (BC_0, * , INTERNAL, X ),"&
"102 (BC_0, * , INTERNAL, X ),"&
"101 (BC_4, P1_7 , INPUT, X ),"&
"100 (BC_1, P1_7 , OUTPUT3, X, 99, 0, Z ),"&
" 99 (BC_1, * , CONTROL, 0 ),"&
" 98 (BC_0, * , INTERNAL, X ),"&
" 97 (BC_0, * , INTERNAL, X ),"&
" 96 (BC_0, * , INTERNAL, X ),"&
" 95 (BC_4, P1_8 , INPUT, X ),"&
" 94 (BC_1, P1_8 , OUTPUT3, X, 93, 0, Z ),"&
" 93 (BC_1, * , CONTROL, 0 ),"&
" 92 (BC_4, P1_9 , INPUT, X ),"&
" 91 (BC_1, P1_9 , OUTPUT3, X, 90, 0, Z ),"&
" 90 (BC_1, * , CONTROL, 0 ),"&
" 89 (BC_0, * , INTERNAL, X ),"&
" 88 (BC_0, * , INTERNAL, X ),"&
" 87 (BC_0, * , INTERNAL, X ),"&
" 86 (BC_4, P0_24 , INPUT, X ),"&
" 85 (BC_1, P0_24 , OUTPUT3, X, 84, 0, Z ),"&
" 84 (BC_1, * , CONTROL, 0 ),"&
" 83 (BC_4, P1_10 , INPUT, X ),"&
" 82 (BC_1, P1_10 , OUTPUT3, X, 81, 0, Z ),"&
" 81 (BC_1, * , CONTROL, 0 ),"&
" 80 (BC_0, * , INTERNAL, X ),"&
" 79 (BC_0, * , INTERNAL, X ),"&
" 78 (BC_0, * , INTERNAL, X ),"&
" 77 (BC_4, P0_25 , INPUT, X ),"&
" 76 (BC_1, P0_25 , OUTPUT3, X, 75, 0, Z ),"&
" 75 (BC_1, * , CONTROL, 0 ),"&
" 74 (BC_0, * , INTERNAL, X ),"&
" 73 (BC_0, * , INTERNAL, X ),"&
" 72 (BC_0, * , INTERNAL, X ),"&
" 71 (BC_4, P0_26 , INPUT, X ),"&
" 70 (BC_1, P0_26 , OUTPUT3, X, 69, 0, Z ),"&
" 69 (BC_1, * , CONTROL, 0 ),"&
" 68 (BC_0, * , INTERNAL, X ),"&
" 67 (BC_0, * , INTERNAL, X ),"&
" 66 (BC_0, * , INTERNAL, X ),"&
" 65 (BC_4, P0_27 , INPUT, X ),"&
" 64 (BC_1, P0_27 , OUTPUT3, X, 63, 0, Z ),"&
" 63 (BC_1, * , CONTROL, 0 ),"&
" 62 (BC_4, P0_28 , INPUT, X ),"&
" 61 (BC_1, P0_28 , OUTPUT3, X, 60, 0, Z ),"&
" 60 (BC_1, * , CONTROL, 0 ),"&
" 59 (BC_0, * , INTERNAL, X ),"&
" 58 (BC_0, * , INTERNAL, X ),"&
" 57 (BC_0, * , INTERNAL, X ),"&
" 56 (BC_4, P0_29 , INPUT, X ),"&
" 55 (BC_1, P0_29 , OUTPUT3, X, 54, 0, Z ),"&
" 54 (BC_1, * , CONTROL, 0 ),"&
" 53 (BC_4, P0_30 , INPUT, X ),"&
" 52 (BC_1, P0_30 , OUTPUT3, X, 51, 0, Z ),"&
" 51 (BC_1, * , CONTROL, 0 ),"&
" 50 (BC_4, P0_0 , INPUT, X ),"&
" 49 (BC_1, P0_0 , OUTPUT3, X, 48, 0, Z ),"&
" 48 (BC_1, * , CONTROL, 0 ),"&
" 47 (BC_4, P0_31 , INPUT, X ),"&
" 46 (BC_1, P0_31 , OUTPUT3, X, 45, 0, Z ),"&
" 45 (BC_1, * , CONTROL, 0 ),"&
" 44 (BC_4, P1_0 , INPUT, X ),"&
" 43 (BC_1, P1_0 , OUTPUT3, X, 42, 0, Z ),"&
" 42 (BC_1, * , CONTROL, 0 ),"&
" 41 (BC_4, P0_1 , INPUT, X ),"&
" 40 (BC_1, P0_1 , OUTPUT3, X, 39, 0, Z ),"&
" 39 (BC_1, * , CONTROL, 0 ),"&
" 38 (BC_4, P0_2 , INPUT, X ),"&
" 37 (BC_1, P0_2 , OUTPUT3, X, 36, 0, Z ),"&
" 36 (BC_1, * , CONTROL, 0 ),"&
" 35 (BC_0, * , INTERNAL, X ),"&
" 34 (BC_0, * , INTERNAL, X ),"&
" 33 (BC_0, * , INTERNAL, X ),"&
" 32 (BC_4, P0_3 , INPUT, X ),"&
" 31 (BC_1, P0_3 , OUTPUT3, X, 30, 0, Z ),"&
" 30 (BC_1, * , CONTROL, 0 ),"&
" 29 (BC_0, * , INTERNAL, X ),"&
" 28 (BC_0, * , INTERNAL, X ),"&
" 27 (BC_0, * , INTERNAL, X ),"&
" 26 (BC_0, * , INTERNAL, X ),"&
" 25 (BC_0, * , INTERNAL, X ),"&
" 24 (BC_0, * , INTERNAL, X ),"&
" 23 (BC_4, P0_4 , INPUT, X ),"&
" 22 (BC_1, P0_4 , OUTPUT3, X, 21, 0, Z ),"&
" 21 (BC_1, * , CONTROL, 0 ),"&
" 20 (BC_4, P0_5 , INPUT, X ),"&
" 19 (BC_1, P0_5 , OUTPUT3, X, 18, 0, Z ),"&
" 18 (BC_1, * , CONTROL, 0 ),"&
" 17 (BC_0, * , INTERNAL, X ),"&
" 16 (BC_0, * , INTERNAL, X ),"&
" 15 (BC_0, * , INTERNAL, X ),"&
" 14 (BC_4, P0_6 , INPUT, X ),"&
" 13 (BC_1, P0_6 , OUTPUT3, X, 12, 0, Z ),"&
" 12 (BC_1, * , CONTROL, 0 ),"&
" 11 (BC_4, P0_7 , INPUT, X ),"&
" 10 (BC_1, P0_7 , OUTPUT3, X, 9, 0, Z ),"&
" 9 (BC_1, * , CONTROL, 0 ),"&
" 8 (BC_0, * , INTERNAL, X ),"&
" 7 (BC_0, * , INTERNAL, X ),"&
" 6 (BC_0, * , INTERNAL, X ),"&
" 5 (BC_0, * , INTERNAL, X ),"&
" 4 (BC_0, * , INTERNAL, X ),"&
" 3 (BC_0, * , INTERNAL, X ),"&
" 2 (BC_4, P1_1 , INPUT, X ),"&
" 1 (BC_1, P1_1 , OUTPUT3, X, 0, 0, Z ),"&
" 0 (BC_1, * , CONTROL, 0 )";
end LPC15xx;