-- Revision History:
-- 22.Apr.03: This model contains JEDEC pinout of the PBGA package
entity MPC850 is
generic (PHYSICAL_PIN_MAP : string := "BGA");
port ( a: inout bit_vector(6 to 31);
aleb_dsc: inout bit;
bb_b: inout bit;
bdip_b_g: buffer bit;
bg_b: inout bit;
bi_b: inout bit;
br_b: inout bit;
burst_b: inout bit;
clk4in: in bit;
clkout: buffer bit;
cs0_b: buffer bit;
cs1_b: buffer bit;
cs2_b: buffer bit;
cs3_b: buffer bit;
cs4_b: buffer bit;
cs5_b: buffer bit;
cs6_b_ce: buffer bit;
cs7_b_ce: buffer bit;
d: inout bit_vector(0 to 31);
dp0_irq3: inout bit;
dp1_irq4: inout bit;
dp2_irq5: inout bit;
dp3_irq6: inout bit;
extal: linkage bit;
frz_irq6: inout bit;
gpla0_b: buffer bit;
gpla4_b: inout bit;
gpla5_b: buffer bit;
gplab2_b: buffer bit;
gplab3_b: buffer bit;
gplb4_b: inout bit;
hreset_b: inout bit;
ipb0_iwp: inout bit;
ipb1_iwp: inout bit;
ipb2_ioi: inout bit;
ipb3_iwp: inout bit;
ipb4_lwp: inout bit;
ipb5_lwp: inout bit;
ipb6_dsd: inout bit;
ipb7_ptr: inout bit;
irq0_b: in bit;
irq1_b: in bit;
irq7_b: in bit;
kapwr: linkage bit;
kr_b_irq: inout bit;
oe_b_gpl: buffer bit;
op2_modc: inout bit;
op3_modc: inout bit;
pa4: inout bit;
pa5: inout bit;
pa6: inout bit;
pa7: inout bit;
pa8: inout bit;
pa9: inout bit;
pa12: inout bit;
pa13: inout bit;
pa14: inout bit;
pa15: inout bit;
pb16: inout bit;
pb17: inout bit;
pb18: inout bit;
pb19: inout bit;
pb22: inout bit;
pb23: inout bit;
pb24: inout bit;
pb25: inout bit;
pb26: inout bit;
pb27: inout bit;
pb28: inout bit;
pb29: inout bit;
pb30: inout bit;
pb31: inout bit;
pc: inout bit_vector(4 to 15);
pd: inout bit_vector(3 to 15);
poreset: in bit;
rstconf: in bit;
rsv_b_ir: inout bit;
spare2: inout bit;
spare3: inout bit;
sreset_b: inout bit;
ta_b: inout bit;
tck_dsck: in bit;
tdi_dsdi: in bit;
tdo_dsdo: out bit;
tea_b: inout bit;
texp: buffer bit;
tms: in bit;
trst_b: in bit;
ts_b: inout bit;
tsiz0_re: inout bit;
tsiz1: inout bit;
vdd: linkage bit_vector(1 to 4);
vddh: linkage bit_vector(1 to 27);
vddsyn: linkage bit;
vss: linkage bit_vector(1 to 36);
vsssyn: linkage bit;
vsssyn1: linkage bit;
waitb_b: in bit;
we0_b_bs: buffer bit;
we1_b_bs: buffer bit;
we2_b_bs: buffer bit;
we3_b_bs: buffer bit;
wr_b: inout bit;
xfc: linkage bit;
xtal: linkage bit);
use STD_1149_1_1994.all;
attribute COMPONENT_CONFORMANCE of MPC850 : entity is "STD_1149_1_1993";
attribute PIN_MAP of MPC850 : entity is PHYSICAL_PIN_MAP;
constant BGA : PIN_MAP_STRING :=
"vsssyn: B2, " &
"vsssyn1: B3, " &
"kapwr: B4, " &
"xtal: B5, " &
"extal: B6, " &
"clk4in: B7, " &
"vdd: (B8, K17, H2, U8), " &
"ipb0_iwp: B9, " &
"ipb3_iwp: B10, " &
"frz_irq6: B11, " &
"bb_b: B12, " &
"ta_b: B13, " &
"bdip_b_g: B14, " &
"cs1_b: B15, " &
"cs3_b: B16, " &
"vddsyn: C2, " &
"xfc: C3, " &
"poreset: C4, " &
"sreset_b: C5, " &
"hreset_b: C6, " &
"op3_modc: C7, " &
"kr_b_irq: C8, " &
"aleb_dsc: C9, " &
"ipb4_lwp: C10, " &
"burst_b: C11, " &
"br_b: C12, " &
"bi_b: C13, " &
"gplb4_b: C14, " &
"cs2_b: C15, " &
"cs7_b_ce: C16, " &
"cs4_b: C17, " &
"dp3_irq6: D3, " &
"dp0_irq3: D4, " &
"waitb_b: D5, " &
"rstconf: D6, " &
"ipb6_dsd: D8, " &
"ipb1_iwp: D9, " &
"ipb5_lwp: D10, " &
"bg_b: D11, " &
"tea_b: D12, " &
"gpla5_b: D13, " &
"wr_b: D14, " &
"cs6_b_ce: D15, " &
"gplab2_b: D16, " &
"oe_b_gpl: D17, " &
"clkout: E2, " &
"d: (N2, M2, K3, K2, M3, J2, G2, F2, N3, L3, L4, L2, N5, N4, K4, K5, J3, L5, J4, H3, " &
"H4, G3, J5, M5, G4, H5, F5, M4, G5, F3, E3, F4), " &
"dp2_irq5: E4, " &
"dp1_irq4: E5, " &
"texp: E6, " &
"op2_modc: E7, " &
"ipb2_ioi: E8, " &
"ipb7_ptr: E9, " &
"rsv_b_ir: E10, " &
"ts_b: E11, " &
"gpla4_b: E12, " &
"cs0_b: E13, " &
"cs5_b: E14, " &
"gplab3_b: E15, " &
"we2_b_bs: E16, " &
"we0_b_bs: E17, " &
"vddh: (G6, F7, F8, F9, F10, F11, F12, F13, N6, N7, N8, N9, N10, N11, N12, N13, H6, J6, " &
"K6, L6, M6, G13, H13, J13, K13, L13, M13), " &
"gpla0_b: F14, " &
"tsiz1: F16, " &
"we1_b_bs: F17, " &
"vss: (G7, G8, G9, G10, G11, G12, H7, H8, H9, H10, H11, H12, J7, J8, J9, J10, J11, J12, " &
"K7, K8, K9, K10, K11, K12, L7, L8, L9, L10, L11, L12, M7, M8, M9, M10, M11, M12), " &
"we3_b_bs: G14, " &
"a: (N14, P16, P17, N16, M14, N17, N15, M15, M16, M17, L15, L14, H14, L16, K16, K15, " &
"H15, J16, J14, J15, G15, L17, H17, J17, H16, G17), " &
"tsiz0_re: G16, " &
"irq0_b: P2, " &
"irq1_b: P3, " &
"irq7_b: P4, " &
"pd: (P5, R4, R3, T2, T3, U2, R5, U3, P6, T4, R6, U4, T5), " &
"pc: (U5, R7, P7, U6, P9, T9, R10, T11, U14, R14, U17, T17), " &
"pb17: P8, " &
"pa9: P11, " &
"pb25: P12, " &
"tdo_dsdo: P13, " &
"pb31: P15, " &
"spare3: R2, " &
"pb18: R8, " &
"pa6: R9, " &
"spare2: R11, " &
"trst_b: R12, " &
"pb26: R13, " &
"pb29: R15, " &
"pb30: R16, " &
"pa15: R17, " &
"pb16: T6, " &
"pa4: T7, " &
"pb19: T8, " &
"pb22: T10, " &
"tdi_dsdi: T12, " &
"tms: T13, " &
"pa12: T14, " &
"pa13: T15, " &
"pa14: T16, " &
"pa5: U7, " &
"pa7: U9, " &
"pa8: U10, " &
"pb23: U11, " &
"pb24: U12, " &
"tck_dsck: U13, " &
"pb27: U15, " &
"pb28: U16 ";
attribute TAP_SCAN_IN of tdi_dsdi : signal is true;
attribute TAP_SCAN_OUT of tdo_dsdo : signal is true;
attribute TAP_SCAN_MODE of tms : signal is true;
attribute TAP_SCAN_RESET of trst_b : signal is true;
attribute TAP_SCAN_CLOCK of tck_dsck : signal is (20.0e6, BOTH);
attribute INSTRUCTION_LENGTH of MPC850 : entity is 4;
attribute INSTRUCTION_OPCODE of MPC850 : entity is
"EXTEST (0000)," &
"SAMPLE (0001)," &
"CLAMP (0101)," &
"HIGHZ (0100)," &
"BYPASS (1111, 0010, 0011, 0110, 0111)";
attribute INSTRUCTION_CAPTURE of MPC850 : entity is "0101";
attribute BOUNDARY_LENGTH of MPC850 : entity is 397;
attribute BOUNDARY_REGISTER of MPC850 : entity is
-- num cell port func safe [ccell dis rslt]
"0 (BC_4, pb26, input, X)," &
"1 (BC_2, pb26, output3, 0, 2, 1, Z)," &
"2 (BC_2, *, controlr, 1)," &
"3 (BC_4, pc(12), input, X)," &
"4 (BC_2, pc(12), output3, 0, 5, 1, Z)," &
"5 (BC_2, *, controlr, 1)," &
"6 (BC_4, pa12, input, X)," &
"7 (BC_2, pa12, output3, 0, 8, 1, Z)," &
"8 (BC_2, *, controlr, 1)," &
"9 (BC_4, pb27, input, X)," &
"10 (BC_2, pb27, output3, 0, 11, 1, Z)," &
"11 (BC_2, *, controlr, 1)," &
"12 (BC_4, pc(13), input, X)," &
"13 (BC_2, pc(13), output3, 0, 14, 1, Z)," &
"14 (BC_2, *, controlr, 1)," &
"15 (BC_4, pa13, input, X)," &
"16 (BC_2, pa13, output3, 0, 17, 1, Z)," &
"17 (BC_2, *, controlr, 1)," &
"18 (BC_4, pb28, input, X)," &
"19 (BC_2, pb28, output3, 0, 20, 1, Z)," &
-- num cell port func safe [ccell dis rslt]
"20 (BC_2, *, controlr, 1)," &
"21 (BC_4, pc(14), input, X)," &
"22 (BC_2, pc(14), output3, 0, 23, 1, Z)," &
"23 (BC_2, *, controlr, 1)," &
"24 (BC_4, pa14, input, X)," &
"25 (BC_2, pa14, output3, 0, 26, 1, Z)," &
"26 (BC_2, *, controlr, 1)," &
"27 (BC_4, pb29, input, X)," &
"28 (BC_2, pb29, output3, 0, 29, 1, Z)," &
"29 (BC_2, *, controlr, 1)," &
"30 (BC_4, pc(15), input, X)," &
"31 (BC_2, pc(15), output3, 0, 32, 1, Z)," &
"32 (BC_2, *, controlr, 1)," &
"33 (BC_4, pb30, input, X)," &
"34 (BC_2, pb30, output3, 0, 35, 1, Z)," &
"35 (BC_2, *, controlr, 1)," &
"36 (BC_4, pa15, input, X)," &
"37 (BC_2, pa15, output3, 0, 38, 1, Z)," &
"38 (BC_2, *, controlr, 1)," &
"39 (BC_4, pb31, input, X)," &
-- num cell port func safe [ccell dis rslt]
"40 (BC_2, pb31, output3, 0, 41, 1, Z)," &
"41 (BC_2, *, controlr, 1)," &
"42 (BC_4, a(6), input, X)," &
"43 (BC_2, a(6), output3, 0, 44, 1, Z)," &
"44 (BC_2, *, controlr, 1)," &
"45 (BC_4, a(7), input, X)," &
"46 (BC_2, a(7), output3, 0, 44, 1, Z)," &
"47 (BC_4, a(8), input, X)," &
"48 (BC_2, a(8), output3, 0, 49, 1, Z)," &
"49 (BC_2, *, controlr, 1)," &
"50 (BC_4, a(9), input, X)," &
"51 (BC_2, a(9), output3, 0, 49, 1, Z)," &
"52 (BC_4, a(10), input, X)," &
"53 (BC_2, a(10), output3, 0, 49, 1, Z)," &
"54 (BC_4, a(11), input, X)," &
"55 (BC_2, a(11), output3, 0, 49, 1, Z)," &
"56 (BC_4, a(12), input, X)," &
"57 (BC_2, a(12), output3, 0, 49, 1, Z)," &
"58 (BC_4, a(13), input, X)," &
"59 (BC_2, a(13), output3, 0, 49, 1, Z)," &
-- num cell port func safe [ccell dis rslt]
"60 (BC_4, a(14), input, X)," &
"61 (BC_2, a(14), output3, 0, 49, 1, Z)," &
"62 (BC_4, a(15), input, X)," &
"63 (BC_2, a(15), output3, 0, 49, 1, Z)," &
"64 (BC_4, a(16), input, X)," &
"65 (BC_2, a(16), output3, 0, 66, 1, Z)," &
"66 (BC_2, *, controlr, 1)," &
"67 (BC_4, a(17), input, X)," &
"68 (BC_2, a(17), output3, 0, 66, 1, Z)," &
"69 (BC_4, a(19), input, X)," &
"70 (BC_2, a(19), output3, 0, 66, 1, Z)," &
"71 (BC_4, a(27), input, X)," &
"72 (BC_2, a(27), output3, 0, 66, 1, Z)," &
"73 (BC_4, a(20), input, X)," &
"74 (BC_2, a(20), output3, 0, 66, 1, Z)," &
"75 (BC_4, a(21), input, X)," &
"76 (BC_2, a(21), output3, 0, 66, 1, Z)," &
"77 (BC_4, a(24), input, X)," &
"78 (BC_2, a(24), output3, 0, 66, 1, Z)," &
"79 (BC_4, a(23), input, X)," &
-- num cell port func safe [ccell dis rslt]
"80 (BC_2, a(23), output3, 0, 66, 1, Z)," &
"81 (BC_4, a(29), input, X)," &
"82 (BC_2, a(29), output3, 0, 83, 1, Z)," &
"83 (BC_2, *, controlr, 1)," &
"84 (BC_4, a(25), input, X)," &
"85 (BC_2, a(25), output3, 0, 83, 1, Z)," &
"86 (BC_4, a(30), input, X)," &
"87 (BC_2, a(30), output3, 0, 83, 1, Z)," &
"88 (BC_4, a(18), input, X)," &
"89 (BC_2, a(18), output3, 0, 83, 1, Z)," &
"90 (BC_4, a(28), input, X)," &
"91 (BC_2, a(28), output3, 0, 83, 1, Z)," &
"92 (BC_4, a(22), input, X)," &
"93 (BC_2, a(22), output3, 0, 83, 1, Z)," &
"94 (BC_4, a(26), input, X)," &
"95 (BC_2, a(26), output3, 0, 83, 1, Z)," &
"96 (BC_4, a(31), input, X)," &
"97 (BC_2, a(31), output3, 0, 83, 1, Z)," &
"98 (BC_4, tsiz0_re, input, X)," &
"99 (BC_2, tsiz0_re, output3, 0, 102, 1, Z)," &
-- num cell port func safe [ccell dis rslt]
"100 (BC_4, tsiz1, input, X)," &
"101 (BC_2, tsiz1, output3, 0, 102, 1, Z)," &
"102 (BC_2, *, controlr, 1)," &
"103 (BC_2, we3_b_bs, output2, 0)," &
"104 (BC_2, we1_b_bs, output2, 0)," &
"105 (BC_2, we2_b_bs, output2, 0)," &
"106 (BC_2, we0_b_bs, output2, 0)," &
"107 (BC_2, gpla0_b, output2, 0)," &
"108 (BC_2, oe_b_gpl, output2, 0)," &
"109 (BC_2, gplab2_b, output2, 0)," &
"110 (BC_2, gplab3_b, output2, 0)," &
"111 (BC_2, cs4_b, output2, 0)," &
"112 (BC_2, cs5_b, output2, 0)," &
"113 (BC_2, cs6_b_ce, output2, 0)," &
"114 (BC_2, cs7_b_ce, output2, 0)," &
"115 (BC_2, cs3_b, output2, 0)," &
"116 (BC_2, cs2_b, output2, 0)," &
"117 (BC_2, cs1_b, output2, 0)," &
"118 (BC_2, cs0_b, output2, 0)," &
"119 (BC_4, wr_b, input, X)," &
-- num cell port func safe [ccell dis rslt]
"120 (BC_2, wr_b, output3, 0, 121, 1, Z)," &
"121 (BC_2, *, controlr, 1)," &
"122 (BC_4, gplb4_b, input, X)," &
"123 (BC_2, gplb4_b, output3, 0, 124, 1, Z)," &
"124 (BC_2, *, controlr, 1)," &
"125 (BC_2, gpla5_b, output2, 0)," &
"126 (BC_4, gpla4_b, input, X)," &
"127 (BC_2, gpla4_b, output3, 0, 128, 1, Z)," &
"128 (BC_2, *, controlr, 1)," &
"129 (BC_2, bdip_b_g, output2, 0)," &
"130 (BC_4, bi_b, input, X)," &
"131 (BC_2, bi_b, output3, 0, 132, 1, Z)," &
"132 (BC_2, *, controlr, 1)," &
"133 (BC_4, ta_b, input, X)," &
"134 (BC_2, ta_b, output3, 0, 135, 1, Z)," &
"135 (BC_2, *, controlr, 1)," &
"136 (BC_4, tea_b, input, X)," &
"137 (BC_2, tea_b, output3, 0, 138, 1, Z)," &
"138 (BC_2, *, controlr, 1)," &
"139 (BC_4, ts_b, input, X)," &
-- num cell port func safe [ccell dis rslt]
"140 (BC_2, ts_b, output3, 0, 141, 1, Z)," &
"141 (BC_2, *, controlr, 1)," &
"142 (BC_4, br_b, input, X)," &
"143 (BC_2, br_b, output3, 0, 144, 1, Z)," &
"144 (BC_2, *, controlr, 1)," &
"145 (BC_4, bg_b, input, X)," &
"146 (BC_2, bg_b, output3, 0, 147, 1, Z)," &
"147 (BC_2, *, controlr, 1)," &
"148 (BC_4, bb_b, input, X)," &
"149 (BC_2, bb_b, output3, 0, 150, 1, Z)," &
"150 (BC_2, *, controlr, 1)," &
"151 (BC_4, frz_irq6, input, X)," &
"152 (BC_2, frz_irq6, output3, 0, 153, 1, Z)," &
"153 (BC_2, *, controlr, 1)," &
"154 (BC_4, burst_b, input, X)," &
"155 (BC_2, burst_b, output3, 0, 156, 1, Z)," &
"156 (BC_2, *, controlr, 1)," &
"157 (BC_4, rsv_b_ir, input, X)," &
"158 (BC_2, rsv_b_ir, output3, 0, 159, 1, Z)," &
"159 (BC_2, *, controlr, 1)," &
-- num cell port func safe [ccell dis rslt]
"160 (BC_4, ipb5_lwp, input, X)," &
"161 (BC_2, ipb5_lwp, output3, 0, 162, 1, Z)," &
"162 (BC_2, *, controlr, 1)," &
"163 (BC_4, ipb4_lwp, input, X)," &
"164 (BC_2, ipb4_lwp, output3, 0, 165, 1, Z)," &
"165 (BC_2, *, controlr, 1)," &
"166 (BC_4, ipb3_iwp, input, X)," &
"167 (BC_2, ipb3_iwp, output3, 0, 168, 1, Z)," &
"168 (BC_2, *, controlr, 1)," &
"169 (BC_4, ipb1_iwp, input, X)," &
"170 (BC_2, ipb1_iwp, output3, 0, 165, 1, Z)," &
"171 (BC_4, ipb0_iwp, input, X)," &
"172 (BC_2, ipb0_iwp, output3, 0, 165, 1, Z)," &
"173 (BC_4, ipb7_ptr, input, X)," &
"174 (BC_2, ipb7_ptr, output3, 0, 175, 1, Z)," &
"175 (BC_2, *, controlr, 1)," &
"176 (BC_4, ipb2_ioi, input, X)," &
"177 (BC_2, ipb2_ioi, output3, 0, 178, 1, Z)," &
"178 (BC_2, *, controlr, 1)," &
"179 (BC_4, aleb_dsc, input, X)," &
-- num cell port func safe [ccell dis rslt]
"180 (BC_2, aleb_dsc, output3, 0, 181, 1, Z)," &
"181 (BC_2, *, controlr, 1)," &
"182 (BC_4, ipb6_dsd, input, X)," &
"183 (BC_2, ipb6_dsd, output3, 0, 184, 1, Z)," &
"184 (BC_2, *, controlr, 1)," &
"185 (BC_4, kr_b_irq, input, X)," &
"186 (BC_2, kr_b_irq, output3, 0, 187, 1, Z)," &
"187 (BC_2, *, controlr, 1)," &
"188 (BC_4, op2_modc, input, X)," &
"189 (BC_2, op2_modc, output3, 0, 190, 1, Z)," &
"190 (BC_2, *, controlr, 1)," &
"191 (BC_4, op3_modc, input, X)," &
"192 (BC_2, op3_modc, output3, 0, 193, 1, Z)," &
"193 (BC_2, *, controlr, 1)," &
"194 (BC_4, clk4in, input, X)," &
"195 (BC_2, texp, output2, 0)," &
"196 (BC_4, hreset_b, input, X)," &
"197 (BC_2, hreset_b, output3, 0, 198, 1, Z)," &
"198 (BC_2, *, controlr, 1)," &
"199 (BC_4, sreset_b, input, X)," &
-- num cell port func safe [ccell dis rslt]
"200 (BC_2, sreset_b, output3, 0, 201, 1, Z)," &
"201 (BC_2, *, controlr, 1)," &
"202 (BC_4, rstconf, input, X)," &
"203 (BC_4, poreset, input, X)," &
"204 (BC_4, waitb_b, input, X)," &
"205 (BC_2, clkout, output2, 0)," &
"206 (BC_4, dp0_irq3, input, X)," &
"207 (BC_2, dp0_irq3, output3, 0, 210, 1, Z)," &
"208 (BC_4, dp3_irq6, input, X)," &
"209 (BC_2, dp3_irq6, output3, 0, 210, 1, Z)," &
"210 (BC_2, *, controlr, 1)," &
"211 (BC_4, dp2_irq5, input, X)," &
"212 (BC_2, dp2_irq5, output3, 0, 210, 1, Z)," &
"213 (BC_4, dp1_irq4, input, X)," &
"214 (BC_2, dp1_irq4, output3, 0, 210, 1, Z)," &
"215 (BC_4, d(31), input, X)," &
"216 (BC_2, d(31), output3, 0, 217, 1, Z)," &
"217 (BC_2, *, controlr, 1)," &
"218 (BC_4, d(30), input, X)," &
"219 (BC_2, d(30), output3, 0, 217, 1, Z)," &
-- num cell port func safe [ccell dis rslt]
"220 (BC_4, d(29), input, X)," &
"221 (BC_2, d(29), output3, 0, 217, 1, Z)," &
"222 (BC_4, d(7), input, X)," &
"223 (BC_2, d(7), output3, 0, 217, 1, Z)," &
"224 (BC_4, d(28), input, X)," &
"225 (BC_2, d(28), output3, 0, 217, 1, Z)," &
"226 (BC_4, d(26), input, X)," &
"227 (BC_2, d(26), output3, 0, 217, 1, Z)," &
"228 (BC_4, d(25), input, X)," &
"229 (BC_2, d(25), output3, 0, 217, 1, Z)," &
"230 (BC_4, d(24), input, X)," &
"231 (BC_2, d(24), output3, 0, 217, 1, Z)," &
"232 (BC_4, d(21), input, X)," &
"233 (BC_2, d(21), output3, 0, 234, 1, Z)," &
"234 (BC_2, *, controlr, 1)," &
"235 (BC_4, d(22), input, X)," &
"236 (BC_2, d(22), output3, 0, 234, 1, Z)," &
"237 (BC_4, d(6), input, X)," &
"238 (BC_2, d(6), output3, 0, 234, 1, Z)," &
"239 (BC_4, d(20), input, X)," &
-- num cell port func safe [ccell dis rslt]
"240 (BC_2, d(20), output3, 0, 234, 1, Z)," &
"241 (BC_4, d(19), input, X)," &
"242 (BC_2, d(19), output3, 0, 234, 1, Z)," &
"243 (BC_4, d(18), input, X)," &
"244 (BC_2, d(18), output3, 0, 234, 1, Z)," &
"245 (BC_4, d(15), input, X)," &
"246 (BC_2, d(15), output3, 0, 234, 1, Z)," &
"247 (BC_4, d(16), input, X)," &
"248 (BC_2, d(16), output3, 0, 234, 1, Z)," &
"249 (BC_4, d(5), input, X)," &
"250 (BC_2, d(5), output3, 0, 251, 1, Z)," &
"251 (BC_2, *, controlr, 1)," &
"252 (BC_4, d(3), input, X)," &
"253 (BC_2, d(3), output3, 0, 251, 1, Z)," &
"254 (BC_4, d(14), input, X)," &
"255 (BC_2, d(14), output3, 0, 251, 1, Z)," &
"256 (BC_4, d(2), input, X)," &
"257 (BC_2, d(2), output3, 0, 251, 1, Z)," &
"258 (BC_4, d(11), input, X)," &
"259 (BC_2, d(11), output3, 0, 251, 1, Z)," &
-- num cell port func safe [ccell dis rslt]
"260 (BC_4, d(10), input, X)," &
"261 (BC_2, d(10), output3, 0, 251, 1, Z)," &
"262 (BC_4, d(9), input, X)," &
"263 (BC_2, d(9), output3, 0, 251, 1, Z)," &
"264 (BC_4, d(17), input, X)," &
"265 (BC_2, d(17), output3, 0, 251, 1, Z)," &
"266 (BC_4, d(27), input, X)," &
"267 (BC_2, d(27), output3, 0, 268, 1, Z)," &
"268 (BC_2, *, controlr, 1)," &
"269 (BC_4, d(23), input, X)," &
"270 (BC_2, d(23), output3, 0, 268, 1, Z)," &
"271 (BC_4, d(1), input, X)," &
"272 (BC_2, d(1), output3, 0, 268, 1, Z)," &
"273 (BC_4, d(4), input, X)," &
"274 (BC_2, d(4), output3, 0, 268, 1, Z)," &
"275 (BC_4, d(0), input, X)," &
"276 (BC_2, d(0), output3, 0, 268, 1, Z)," &
"277 (BC_4, d(12), input, X)," &
"278 (BC_2, d(12), output3, 0, 268, 1, Z)," &
"279 (BC_4, d(8), input, X)," &
-- num cell port func safe [ccell dis rslt]
"280 (BC_2, d(8), output3, 0, 268, 1, Z)," &
"281 (BC_4, d(13), input, X)," &
"282 (BC_2, d(13), output3, 0, 268, 1, Z)," &
"283 (BC_4, irq0_b, input, X)," &
"284 (BC_4, irq1_b, input, X)," &
"285 (BC_4, irq7_b, input, X)," &
"286 (BC_4, spare3, input, X)," &
"287 (BC_2, spare3, output3, 0, 288, 1, Z)," &
"288 (BC_2, *, controlr, 1)," &
"289 (BC_4, pd(3), input, X)," &
"290 (BC_2, pd(3), output3, 0, 291, 1, Z)," &
"291 (BC_2, *, controlr, 1)," &
"292 (BC_4, pd(5), input, X)," &
"293 (BC_2, pd(5), output3, 0, 294, 1, Z)," &
"294 (BC_2, *, controlr, 1)," &
"295 (BC_4, pd(6), input, X)," &
"296 (BC_2, pd(6), output3, 0, 297, 1, Z)," &
"297 (BC_2, *, controlr, 1)," &
"298 (BC_4, pd(4), input, X)," &
"299 (BC_2, pd(4), output3, 0, 300, 1, Z)," &
-- num cell port func safe [ccell dis rslt]
"300 (BC_2, *, controlr, 1)," &
"301 (BC_4, pd(7), input, X)," &
"302 (BC_2, pd(7), output3, 0, 303, 1, Z)," &
"303 (BC_2, *, controlr, 1)," &
"304 (BC_4, pd(8), input, X)," &
"305 (BC_2, pd(8), output3, 0, 306, 1, Z)," &
"306 (BC_2, *, controlr, 1)," &
"307 (BC_4, pd(9), input, X)," &
"308 (BC_2, pd(9), output3, 0, 309, 1, Z)," &
"309 (BC_2, *, controlr, 1)," &
"310 (BC_4, pd(10), input, X)," &
"311 (BC_2, pd(10), output3, 0, 312, 1, Z)," &
"312 (BC_2, *, controlr, 1)," &
"313 (BC_4, pd(11), input, X)," &
"314 (BC_2, pd(11), output3, 0, 315, 1, Z)," &
"315 (BC_2, *, controlr, 1)," &
"316 (BC_4, pd(12), input, X)," &
"317 (BC_2, pd(12), output3, 0, 318, 1, Z)," &
"318 (BC_2, *, controlr, 1)," &
"319 (BC_4, pd(13), input, X)," &
-- num cell port func safe [ccell dis rslt]
"320 (BC_2, pd(13), output3, 0, 321, 1, Z)," &
"321 (BC_2, *, controlr, 1)," &
"322 (BC_4, pd(14), input, X)," &
"323 (BC_2, pd(14), output3, 0, 324, 1, Z)," &
"324 (BC_2, *, controlr, 1)," &
"325 (BC_4, pd(15), input, X)," &
"326 (BC_2, pd(15), output3, 0, 327, 1, Z)," &
"327 (BC_2, *, controlr, 1)," &
"328 (BC_4, pc(4), input, X)," &
"329 (BC_2, pc(4), output3, 0, 330, 1, Z)," &
"330 (BC_2, *, controlr, 1)," &
"331 (BC_4, pc(5), input, X)," &
"332 (BC_2, pc(5), output3, 0, 333, 1, Z)," &
"333 (BC_2, *, controlr, 1)," &
"334 (BC_4, pb16, input, X)," &
"335 (BC_2, pb16, output3, 0, 336, 1, Z)," &
"336 (BC_2, *, controlr, 1)," &
"337 (BC_4, pc(6), input, X)," &
"338 (BC_2, pc(6), output3, 0, 339, 1, Z)," &
"339 (BC_2, *, controlr, 1)," &
-- num cell port func safe [ccell dis rslt]
"340 (BC_4, pb17, input, X)," &
"341 (BC_2, pb17, output3, 0, 342, 1, Z)," &
"342 (BC_2, *, controlr, 1)," &
"343 (BC_4, pc(7), input, X)," &
"344 (BC_2, pc(7), output3, 0, 345, 1, Z)," &
"345 (BC_2, *, controlr, 1)," &
"346 (BC_4, pa4, input, X)," &
"347 (BC_2, pa4, output3, 0, 348, 1, Z)," &
"348 (BC_2, *, controlr, 1)," &
"349 (BC_4, pb18, input, X)," &
"350 (BC_2, pb18, output3, 0, 351, 1, Z)," &
"351 (BC_2, *, controlr, 1)," &
"352 (BC_4, pa5, input, X)," &
"353 (BC_2, pa5, output3, 0, 354, 1, Z)," &
"354 (BC_2, *, controlr, 1)," &
"355 (BC_4, pb19, input, X)," &
"356 (BC_2, pb19, output3, 0, 357, 1, Z)," &
"357 (BC_2, *, controlr, 1)," &
"358 (BC_4, pa6, input, X)," &
"359 (BC_2, pa6, output3, 0, 360, 1, Z)," &
-- num cell port func safe [ccell dis rslt]
"360 (BC_2, *, controlr, 1)," &
"361 (BC_4, pc(8), input, X)," &
"362 (BC_2, pc(8), output3, 0, 363, 1, Z)," &
"363 (BC_2, *, controlr, 1)," &
"364 (BC_4, pa7, input, X)," &
"365 (BC_2, pa7, output3, 0, 366, 1, Z)," &
"366 (BC_2, *, controlr, 1)," &
"367 (BC_4, pc(9), input, X)," &
"368 (BC_2, pc(9), output3, 0, 369, 1, Z)," &
"369 (BC_2, *, controlr, 1)," &
"370 (BC_4, pa8, input, X)," &
"371 (BC_2, pa8, output3, 0, 372, 1, Z)," &
"372 (BC_2, *, controlr, 1)," &
"373 (BC_4, pb22, input, X)," &
"374 (BC_2, pb22, output3, 0, 375, 1, Z)," &
"375 (BC_2, *, controlr, 1)," &
"376 (BC_4, pc(10), input, X)," &
"377 (BC_2, pc(10), output3, 0, 378, 1, Z)," &
"378 (BC_2, *, controlr, 1)," &
"379 (BC_4, pa9, input, X)," &
-- num cell port func safe [ccell dis rslt]
"380 (BC_2, pa9, output3, 0, 381, 1, Z)," &
"381 (BC_2, *, controlr, 1)," &
"382 (BC_4, pb23, input, X)," &
"383 (BC_2, pb23, output3, 0, 384, 1, Z)," &
"384 (BC_2, *, controlr, 1)," &
"385 (BC_4, pc(11), input, X)," &
"386 (BC_2, pc(11), output3, 0, 387, 1, Z)," &
"387 (BC_2, *, controlr, 1)," &
"388 (BC_4, pb24, input, X)," &
"389 (BC_2, pb24, output3, 0, 390, 1, Z)," &
"390 (BC_2, *, controlr, 1)," &
"391 (BC_4, pb25, input, X)," &
"392 (BC_2, pb25, output3, 0, 393, 1, Z)," &
"393 (BC_2, *, controlr, 1)," &
"394 (BC_4, spare2, input, X)," &
"395 (BC_2, spare2, output3, 0, 396, 1, Z)," &
"396 (BC_2, *, controlr, 1)";
end MPC850;
