-- ***************************************************************
-- Company: Integrated Device Technology, Inc.
--
-- Document number: 35B8070_BS002_02
--
-- Title: BSDL file of Tsi577Z1 (Atlas)
-- Generated by : Andi Sugandi
--
-- Release status: formal issue
-- Security level: client use
-- BSDL Version 2001
-- Group ownership: DFT Revision Date:
-- Released by :
-- Revision History:
-- Jul 14, 2008: initial release
-- Jul 23, 2009: Updated with IDT formatting
--
-- BSDL Syntax Checker -> passed Jul 14, 2008
--
--
-- ***************************************************************
--
-- Generated by boundaryScanGenerate 4.2b-Build20051027.004 on 05/21/08 10:34:21
-- BSDL Version 2001
-- The default acjt_lvl[4:0] which is controled by IRbits[31:27] is set to 2'h03,
-- tx_lvl which is controlled by IRbits[37:33] is set to 4'h1F
-- To program acjt_lvl and tx_lvl IRbits[32] has to be set to 0
-- VHDL package LVS_BSCAN_CELLS is appended at the end of this file. This LVS_BSCAN_CELLS VHDL file need
-- to be uploaded when compiling this BSDL.
entity Tsi577Z1 is
generic (PHYSICAL_PIN_MAP : string := "HSBGA_399_21");
port (
-- Port List
TRST_b : in bit;
TCK : in bit;
TMS : in bit;
TDO : out bit;
TDI : in bit;
SP0_TD_p : out bit;
SP0_TD_n : out bit;
SP0_RD_p : in bit;
SP0_RD_n : in bit;
SP0_TC_p : out bit;
SP0_TC_n : out bit;
SP0_RC_p : in bit;
SP0_RC_n : in bit;
SP0_TB_p : out bit;
SP0_TB_n : out bit;
SP0_RB_p : in bit;
SP0_RB_n : in bit;
SP0_TA_p : out bit;
SP0_TA_n : out bit;
SP0_RA_p : in bit;
SP0_RA_n : in bit;
SP0_REXT : linkage bit;
SP10_TB_p : out bit;
SP10_TB_n : out bit;
SP10_RB_p : in bit;
SP10_RB_n : in bit;
SP10_TA_p : out bit;
SP10_TA_n : out bit;
SP10_RA_p : in bit;
SP10_RA_n : in bit;
SP2_TB_p : out bit;
SP2_TB_n : out bit;
SP2_RB_p : in bit;
SP2_RB_n : in bit;
SP2_TA_p : out bit;
SP2_TA_n : out bit;
SP2_RA_p : in bit;
SP2_RA_n : in bit;
SP2_REXT : linkage bit;
SP12_TB_p : out bit;
SP12_TB_n : out bit;
SP12_RB_p : in bit;
SP12_RB_n : in bit;
SP12_TA_p : out bit;
SP12_TA_n : out bit;
SP12_RA_p : in bit;
SP12_RA_n : in bit;
SP4_TB_p : out bit;
SP4_TB_n : out bit;
SP4_RB_p : in bit;
SP4_RB_n : in bit;
SP4_TA_p : out bit;
SP4_TA_n : out bit;
SP4_RA_p : in bit;
SP4_RA_n : in bit;
SP4_REXT : linkage bit;
SP6_TD_p : out bit;
SP6_TD_n : out bit;
SP6_RD_p : in bit;
SP6_RD_n : in bit;
SP6_TC_p : out bit;
SP6_TC_n : out bit;
SP6_RC_p : in bit;
SP6_RC_n : in bit;
SP6_TB_p : out bit;
SP6_TB_n : out bit;
SP6_RB_p : in bit;
SP6_RB_n : in bit;
SP6_TA_p : out bit;
SP6_TA_n : out bit;
SP6_RA_p : in bit;
SP6_RA_n : in bit;
SP6_REXT : linkage bit;
SP4_PWRDN : inout bit;
SP5_PWRDN : inout bit;
SP6_PWRDN : inout bit;
SP7_PWRDN : inout bit;
SP14_PWRDN : inout bit;
SP10_PWRDN : inout bit;
SP8_PWRDN : inout bit;
SP11_PWRDN : inout bit;
INT_b : inout bit;
MCES : inout bit;
SP2_MODESEL : inout bit;
SP15_PWRDN : inout bit;
SP_CLK_SEL : inout bit;
SW_RST_b : inout bit;
SP4_MODESEL : inout bit;
SP12_PWRDN : inout bit;
SP6_MODESEL : inout bit;
HARD_RST_b : linkage bit;
I2C_DISABLE : inout bit;
SP9_PWRDN : inout bit;
SP13_PWRDN : inout bit;
SP1_PWRDN : inout bit;
SP3_PWRDN : inout bit;
I2C_MA : inout bit;
I2C_SA : inout bit_vector( 1 downto 0 );
SP2_PWRDN : inout bit;
I2C_SCLK : inout bit;
SP0_MODESEL : inout bit;
SP_IO_SPEED : inout bit_vector( 1 downto 0 );
I2C_SD : inout bit;
I2C_SEL : inout bit;
SP_RX_SWAP : inout bit;
SP_TX_SWAP : inout bit;
BCE : in bit;
COMP_MODE : linkage bit_vector( 1 downto 0 );
S_CLK_p : linkage bit;
S_CLK_n : linkage bit;
VDD : linkage bit_vector( 31 downto 0 );
VSS : linkage bit_vector( 192 downto 0 );
SP_AVDD : linkage bit_vector( 13 downto 0 );
SP_VDD : linkage bit_vector( 30 downto 0 );
VDD_IO : linkage bit_vector( 10 downto 0 ) );
use STD_1149_1_2001.all;
use STD_1149_6_2003.all;
use LVS_BSCAN_CELLS.all;
attribute COMPONENT_CONFORMANCE of Tsi577Z1: entity is "STD_1149_1_2001";
--Pin mappings
attribute PIN_MAP of Tsi577Z1: entity is PHYSICAL_PIN_MAP;
constant HSBGA_399_21: PIN_MAP_STRING :=
"TRST_b : W20 , " &
"TCK : Y20 , " &
"TMS : U20 , " &
"TDO : V19 , " &
"TDI : V20 , " &
"SP0_TD_p : L1 , " &
"SP0_TD_n : L2 , " &
"SP0_RD_p : L5 , " &
"SP0_RD_n : L4 , " &
"SP0_TC_p : J2 , " &
"SP0_TC_n : J1 , " &
"SP0_RC_p : J4 , " &
"SP0_RC_n : J5 , " &
"SP0_TB_p : G1 , " &
"SP0_TB_n : G2 , " &
"SP0_RB_p : G5 , " &
"SP0_RB_n : G4 , " &
"SP0_TA_p : E2 , " &
"SP0_TA_n : E1 , " &
"SP0_RA_p : E4 , " &
"SP0_RA_n : E5 , " &
"SP0_REXT : H4 , " &
"SP10_TB_p : Y13 , " &
"SP10_TB_n : W13 , " &
"SP10_RB_p : T13 , " &
"SP10_RB_n : U13 , " &
"SP10_TA_p : W11 , " &
"SP10_TA_n : Y11 , " &
"SP10_RA_p : U11 , " &
"SP10_RA_n : T11 , " &
"SP2_TB_p : Y9 , " &
"SP2_TB_n : W9 , " &
"SP2_RB_p : T9 , " &
"SP2_RB_n : U9 , " &
"SP2_TA_p : W7 , " &
"SP2_TA_n : Y7 , " &
"SP2_RA_p : U7 , " &
"SP2_RA_n : T7 , " &
"SP2_REXT : U10 , " &
"SP12_TB_p : G20 , " &
"SP12_TB_n : G19 , " &
"SP12_RB_p : G16 , " &
"SP12_RB_n : G17 , " &
"SP12_TA_p : J19 , " &
"SP12_TA_n : J20 , " &
"SP12_RA_p : J17 , " &
"SP12_RA_n : J16 , " &
"SP4_TB_p : L20 , " &
"SP4_TB_n : L19 , " &
"SP4_RB_p : L16 , " &
"SP4_RB_n : L17 , " &
"SP4_TA_p : N19 , " &
"SP4_TA_n : N20 , " &
"SP4_RA_p : N17 , " &
"SP4_RA_n : N16 , " &
"SP4_REXT : K17 , " &
"SP6_TD_p : A8 , " &
"SP6_TD_n : B8 , " &
"SP6_RD_p : E8 , " &
"SP6_RD_n : D8 , " &
"SP6_TC_p : B10 , " &
"SP6_TC_n : A10 , " &
"SP6_RC_p : D10 , " &
"SP6_RC_n : E10 , " &
"SP6_TB_p : A12 , " &
"SP6_TB_n : B12 , " &
"SP6_RB_p : E12 , " &
"SP6_RB_n : D12 , " &
"SP6_TA_p : B14 , " &
"SP6_TA_n : A14 , " &
"SP6_RA_p : D14 , " &
"SP6_RA_n : E14 , " &
"SP6_REXT : D11 , " &
"SP4_PWRDN : N2 , " &
"SP5_PWRDN : N3 , " &
"SP6_PWRDN : P1 , " &
"SP7_PWRDN : P3 , " &
"SP14_PWRDN : N5 , " &
"SP10_PWRDN : R2 , " &
"SP8_PWRDN : T1 , " &
"SP11_PWRDN : R3 , " &
"INT_b : U2 , " &
"MCES : R19 , " &
"SP2_MODESEL : V1 , " &
"SP15_PWRDN : P5 , " &
"SP_CLK_SEL : T5 , " &
"SW_RST_b : V3 , " &
"SP4_MODESEL : V4 , " &
"SP12_PWRDN : V5 , " &
"SP6_MODESEL : U5 , " &
"HARD_RST_b : Y3 , " &
"I2C_DISABLE : U18 , " &
"SP9_PWRDN : Y5 , " &
"SP13_PWRDN : W5 , " &
"SP1_PWRDN : Y16 , " &
"SP3_PWRDN : Y17 , " &
"I2C_MA : W16 , " &
"I2C_SA :(R17 , " & -- I2C_SA[1]
"R16 ), " & -- I2C_SA[0]
"SP2_PWRDN : W17 , " &
"I2C_SCLK : Y19 , " &
"SP0_MODESEL : V16 , " &
"SP_IO_SPEED :(U16 , " & -- SP_IO_SPEED[1]
"T16 ), " & -- SP_IO_SPEED[0]
"I2C_SD : W18 , " &
"I2C_SEL : T17 , " &
"SP_RX_SWAP : T19 , " &
"SP_TX_SWAP : T20 , " &
"BCE : R20 , " &
"COMP_MODE :(U15 , " & -- COMP_MODE[1]
"T3 ), " & -- COMP_MODE[0]
"S_CLK_p : B18 , " &
"S_CLK_n : B19 , " &
"VDD :(P13 , " & -- VDD[31]
"P11 , " & -- VDD[30]
"P9 , " & -- VDD[29]
"P7 , " & -- VDD[28]
"N14 , " & -- VDD[27]
"N12 , " & -- VDD[26]
"N10 , " & -- VDD[25]
"N8 , " & -- VDD[24]
"M13 , " & -- VDD[23]
"M11 , " & -- VDD[22]
"M9 , " & -- VDD[21]
"M7 , " & -- VDD[20]
"L14 , " & -- VDD[19]
"L12 , " & -- VDD[18]
"L10 , " & -- VDD[17]
"L8 , " & -- VDD[16]
"K13 , " & -- VDD[15]
"K11 , " & -- VDD[14]
"K9 , " & -- VDD[13]
"K7 , " & -- VDD[12]
"J14 , " & -- VDD[11]
"J12 , " & -- VDD[10]
"J10 , " & -- VDD[9]
"J8 , " & -- VDD[8]
"H13 , " & -- VDD[7]
"H11 , " & -- VDD[6]
"H9 , " & -- VDD[5]
"H7 , " & -- VDD[4]
"G14 , " & -- VDD[3]
"G12 , " & -- VDD[2]
"G10 , " & -- VDD[1]
"G8 ), " & -- VDD[0]
"VSS :(Y18 , " & -- VSS[192]
"U14 , " & -- VSS[191] --
"W3 , " & -- VSS[190] --
"D19 , " & -- VSS[189] --
"D18 , " & -- VSS[188] --
"Y15 , " & -- VSS[187]
"Y14 , " & -- VSS[186]
"Y12 , " & -- VSS[185]
"Y10 , " & -- VSS[184]
"Y8 , " & -- VSS[183]
"Y6 , " & -- VSS[182]
"Y4 , " & -- VSS[181]
"W15 , " & -- VSS[180]
"W12 , " & -- VSS[179]
"W8 , " & -- VSS[178]
"W6 , " & -- VSS[177]
"W1 , " & -- VSS[176]
"V18 , " & -- VSS[175]
"V17 , " & -- VSS[174]
"V15 , " & -- VSS[173]
"V14 , " & -- VSS[172]
"V12 , " & -- VSS[171]
"V10 , " & -- VSS[170]
"V8 , " & -- VSS[169]
"V6 , " & -- VSS[168]
"U12 , " & -- VSS[167]
"U8 , " & -- VSS[166]
"U6 , " & -- VSS[165]
"U3 , " & -- VSS[164]
"U1 , " & -- VSS[163]
"T18 , " & -- VSS[162]
"T15 , " & -- VSS[161]
"T6 , " & -- VSS[160]
"T4 , " & -- VSS[159]
"R18 , " & -- VSS[158]
"R15 , " & -- VSS[157]
"R14 , " & -- VSS[156]
"R12 , " & -- VSS[155]
"R10 , " & -- VSS[154]
"R9 , " & -- VSS[153]
"R8 , " & -- VSS[152]
"R7 , " & -- VSS[151]
"R6 , " & -- VSS[150]
"R5 , " & -- VSS[149]
"R1 , " & -- VSS[148]
"P20 , " & -- VSS[147]
"P18 , " & -- VSS[146]
"P17 , " & -- VSS[145]
"P16 , " & -- VSS[144]
"P15 , " & -- VSS[143]
"P14 , " & -- VSS[142]
"P12 , " & -- VSS[141]
"P10 , " & -- VSS[140]
"P8 , " & -- VSS[139]
"P6 , " & -- VSS[138]
"P4 , " & -- VSS[137]
"N15 , " & -- VSS[136]
"N13 , " & -- VSS[135]
"N11 , " & -- VSS[134]
"N9 , " & -- VSS[133]
"N7 , " & -- VSS[132]
"N6 , " & -- VSS[131]
"N1 , " & -- VSS[130]
"M20 , " & -- VSS[129]
"M19 , " & -- VSS[128]
"M18 , " & -- VSS[127]
"M17 , " & -- VSS[126]
"M15 , " & -- VSS[125]
"M14 , " & -- VSS[124]
"M12 , " & -- VSS[123]
"M10 , " & -- VSS[122]
"M8 , " & -- VSS[121]
"M6 , " & -- VSS[120]
"M5 , " & -- VSS[119]
"M4 , " & -- VSS[118]
"M3 , " & -- VSS[117]
"M1 , " & -- VSS[116]
"L13 , " & -- VSS[115]
"L11 , " & -- VSS[114]
"L9 , " & -- VSS[113]
"L7 , " & -- VSS[112]
"K20 , " & -- VSS[111]
"K18 , " & -- VSS[110]
"K15 , " & -- VSS[109]
"K14 , " & -- VSS[108]
"K12 , " & -- VSS[107]
"K10 , " & -- VSS[106]
"K8 , " & -- VSS[105]
"K6 , " & -- VSS[104]
"K4 , " & -- VSS[103]
"K3 , " & -- VSS[102]
"K2 , " & -- VSS[101]
"K1 , " & -- VSS[100]
"J15 , " & -- VSS[99]
"J13 , " & -- VSS[98]
"J11 , " & -- VSS[97]
"J9 , " & -- VSS[96]
"J7 , " & -- VSS[95]
"J6 , " & -- VSS[94]
"H20 , " & -- VSS[93]
"H19 , " & -- VSS[92]
"H18 , " & -- VSS[91]
"H17 , " & -- VSS[90]
"H14 , " & -- VSS[89]
"H12 , " & -- VSS[88]
"H10 , " & -- VSS[87]
"H8 , " & -- VSS[86]
"H6 , " & -- VSS[85]
"H3 , " & -- VSS[84]
"H1 , " & -- VSS[83]
"G15 , " & -- VSS[82]
"G13 , " & -- VSS[81]
"G11 , " & -- VSS[80]
"G9 , " & -- VSS[79]
"G7 , " & -- VSS[78]
"G6 , " & -- VSS[77]
"F20 , " & -- VSS[76]
"F19 , " & -- VSS[75]
"F18 , " & -- VSS[74]
"F15 , " & -- VSS[73]
"F14 , " & -- VSS[72]
"F13 , " & -- VSS[71]
"F12 , " & -- VSS[70]
"F10 , " & -- VSS[69]
"F9 , " & -- VSS[68]
"F8 , " & -- VSS[67]
"F7 , " & -- VSS[66]
"F6 , " & -- VSS[65]
"F4 , " & -- VSS[64]
"F3 , " & -- VSS[63]
"F2 , " & -- VSS[62]
"F1 , " & -- VSS[61]
"E20 , " & -- VSS[60]
"E19 , " & -- VSS[59]
"E18 , " & -- VSS[58]
"E17 , " & -- VSS[57]
"E16 , " & -- VSS[56]
"E15 , " & -- VSS[55]
"E7 , " & -- VSS[54]
"E6 , " & -- VSS[53]
"D20 , " & -- VSS[52]
"D17 , " & -- VSS[51]
"D16 , " & -- VSS[50]
"D15 , " & -- VSS[49]
"D13 , " & -- VSS[48]
"D9 , " & -- VSS[47]
"D7 , " & -- VSS[46]
"D6 , " & -- VSS[45]
"D5 , " & -- VSS[44]
"D4 , " & -- VSS[43]
"D3 , " & -- VSS[42]
"D1 , " & -- VSS[41]
"C19 , " & -- VSS[40]
"C17 , " & -- VSS[39]
"C16 , " & -- VSS[38]
"C15 , " & -- VSS[37]
"C13 , " & -- VSS[36]
"C11 , " & -- VSS[35]
"C9 , " & -- VSS[34]
"C7 , " & -- VSS[33]
"C6 , " & -- VSS[32]
"C5 , " & -- VSS[31]
"C4 , " & -- VSS[30]
"C3 , " & -- VSS[29]
"C2 , " & -- VSS[28]
"C1 , " & -- VSS[27]
"B20 , " & -- VSS[26]
"B17 , " & -- VSS[25]
"B16 , " & -- VSS[24]
"B13 , " & -- VSS[23]
"B9 , " & -- VSS[22]
"B7 , " & -- VSS[21]
"B6 , " & -- VSS[20]
"B5 , " & -- VSS[19]
"B4 , " & -- VSS[18]
"B3 , " & -- VSS[17]
"B2 , " & -- VSS[16]
"B1 , " & -- VSS[15]
"A20 , " & -- VSS[14]
"A19 , " & -- VSS[13]
"A18 , " & -- VSS[12]
"A17 , " & -- VSS[11]
"A16 , " & -- VSS[10]
"A15 , " & -- VSS[9]
"A13 , " & -- VSS[8]
"A11 , " & -- VSS[7]
"A9 , " & -- VSS[6]
"A7 , " & -- VSS[5]
"A6 , " & -- VSS[4]
"A5 , " & -- VSS[3]
"A4 , " & -- VSS[2]
"A3 , " & -- VSS[1]
"A2 ), " & -- VSS[0]
"SP_AVDD :(T14 , " & -- SP_AVDD[13]
"T10 , " & -- SP_AVDD[12]
"R13 , " & -- SP_AVDD[11]
"R11 , " & -- SP_AVDD[10]
"L15 , " & -- SP_AVDD[9]
"L6 , " & -- SP_AVDD[8]
"K16 , " & -- SP_AVDD[7]
"K5 , " & -- SP_AVDD[6]
"H15 , " & -- SP_AVDD[5]
"H5 , " & -- SP_AVDD[4]
"F16 , " & -- SP_AVDD[3]
"F11 , " & -- SP_AVDD[2]
"E11 , " & -- SP_AVDD[1]
"E9 ), " & -- SP_AVDD[0]
"SP_VDD :(W14 , " & -- SP_VDD[30]
"W10 , " & -- SP_VDD[29]
"V13 , " & -- SP_VDD[28]
"V11 , " & -- SP_VDD[27]
"V9 , " & -- SP_VDD[26]
"V7 , " & -- SP_VDD[25]
"T12 , " & -- SP_VDD[24]
"T8 , " & -- SP_VDD[23]
"P19 , " & -- SP_VDD[22]
"N18 , " & -- SP_VDD[21]
"M16 , " & -- SP_VDD[20]
"M2 , " & -- SP_VDD[19]
"L18 , " & -- SP_VDD[18]
"L3 , " & -- SP_VDD[17]
"K19 , " & -- SP_VDD[16]
"J18 , " & -- SP_VDD[15]
"J3 , " & -- SP_VDD[14]
"H16 , " & -- SP_VDD[13]
"H2 , " & -- SP_VDD[12]
"G18 , " & -- SP_VDD[11]
"G3 , " & -- SP_VDD[10]
"F5 , " & -- SP_VDD[9]
"E13 , " & -- SP_VDD[8]
"E3 , " & -- SP_VDD[7]
"D2 , " & -- SP_VDD[6]
"C14 , " & -- SP_VDD[5]
"C12 , " & -- SP_VDD[4]
"C10 , " & -- SP_VDD[3]
"C8 , " & -- SP_VDD[2]
"B15 , " & -- SP_VDD[1]
"B11 ), " & -- SP_VDD[0]
"VDD_IO :(Y2 , " & -- VDD_IO[10]
"N4 , " & -- VDD_IO[9] --
"W19 , " & -- VDD_IO[8]
"W4 , " & -- VDD_IO[7]
"V2 , " & -- VDD_IO[6]
"U19 , " & -- VDD_IO[5]
"U17 , " & -- VDD_IO[4]
"U4 , " & -- VDD_IO[3]
"T2 , " & -- VDD_IO[2]
"R4 , " & -- VDD_IO[1]
"P2 ) " ; -- VDD_IO[0]
attribute PORT_GROUPING of Tsi577Z1 : entity is
"Differential_Current ( (SP0_TB_p, SP0_TB_n), " &
"(SP0_RB_p, SP0_RB_n), " &
"(SP0_TA_p, SP0_TA_n), " &
"(SP0_RA_p, SP0_RA_n), " &
"(SP0_TC_p, SP0_TC_n), " &
"(SP0_RC_p, SP0_RC_n), " &
"(SP0_TD_p, SP0_TD_n), " &
"(SP0_RD_p, SP0_RD_n), " &
"(SP2_TB_p, SP2_TB_n), " &
"(SP2_RB_p, SP2_RB_n), " &
"(SP2_TA_p, SP2_TA_n), " &
"(SP2_RA_p, SP2_RA_n), " &
"(SP10_TA_p, SP10_TA_n), " &
"(SP10_RA_p, SP10_RA_n), " &
"(SP10_TB_p, SP10_TB_n), " &
"(SP10_RB_p, SP10_RB_n), " &
"(SP4_TB_p, SP4_TB_n), " &
"(SP4_RB_p, SP4_RB_n), " &
"(SP4_TA_p, SP4_TA_n), " &
"(SP4_RA_p, SP4_RA_n), " &
"(SP12_TA_p, SP12_TA_n), " &
"(SP12_RA_p, SP12_RA_n), " &
"(SP12_TB_p, SP12_TB_n), " &
"(SP12_RB_p, SP12_RB_n), " &
"(SP6_TB_p, SP6_TB_n), " &
"(SP6_RB_p, SP6_RB_n), " &
"(SP6_TA_p, SP6_TA_n), " &
"(SP6_RA_p, SP6_RA_n), " &
"(SP6_TC_p, SP6_TC_n), " &
"(SP6_RC_p, SP6_RC_n), " &
"(SP6_TD_p, SP6_TD_n), " &
"(SP6_RD_p, SP6_RD_n)) " ;
attribute TAP_SCAN_RESET of TRST_b : signal is true;
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_CLOCK of TCK : signal is (1.0000000000000000000e+07, BOTH);
attribute COMPLIANCE_PATTERNS of Tsi577Z1 : entity is
"(BCE) (1)";
attribute INSTRUCTION_LENGTH of Tsi577Z1: entity is 61;
attribute INSTRUCTION_OPCODE of Tsi577Z1: entity is
"IDCODE (1111111111111111111111111111111111111111111111111111111111110)," &
"BYPASS (0000000000000000000000000000000000000000000000000000000000000, 1111111111111111111111111111111111111111111111111111111111111)," &
"EXTEST (1111111111111111111111100000011100111111111111111111111101000)," &
"EXTEST_PULSE (1111111111111111111111100000011100111111111101111111111101000)," &
"EXTEST_TRAIN (1111111111111111111111100000011100111111111011111111111101000)," &
"SAMPLE (1111111111111111111111100000011100111111111111111111111111000)," &
"PRELOAD (1111111111111111111111100000011100111111111111111111111111000)," &
"CLAMP (1111111111111111111111100000011100111111111111111111111101111) " ;
attribute INSTRUCTION_CAPTURE of Tsi577Z1: entity is "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx01";
attribute IDCODE_REGISTER of Tsi577Z1: entity is
"0000" & -- version
"0000010101110111" & -- part number
"00010110011" & -- manufacturer's identity
"1"; -- required by 1149.1
attribute REGISTER_ACCESS of Tsi577Z1: entity is
"BOUNDARY ( EXTEST_PULSE, EXTEST_TRAIN )," &
"BOUNDARY ( SAMPLE, PRELOAD )," &
"BYPASS ( CLAMP, BYPASS ) " ;
--Boundary scan definition
attribute BOUNDARY_LENGTH of Tsi577Z1: entity is 114;
attribute BOUNDARY_REGISTER of Tsi577Z1: entity is
-- num cell port function safe [ccell disval rslt]
" 113 (BC_1 , * , control , 0 ) ,"&
" 112 (AC_1 , SP0_TB_p , output3 , X , 113 , 0 , Z ),"&
" 111 (BC_4 , SP0_RB_p , observe_only , X ) ,"&
" 110 (BC_4 , SP0_RB_n , observe_only , X ) ,"&
" 109 (BC_1 , * , control , 0 ) ,"&
" 108 (AC_1 , SP0_TA_p , output3 , X , 109 , 0 , Z ),"&
" 107 (BC_4 , SP0_RA_p , observe_only , X ) ,"&
" 106 (BC_4 , SP0_RA_n , observe_only , X ) ,"&
" 105 (BC_1 , * , control , 0 ) ,"&
" 104 (AC_1 , SP0_TC_p , output3 , X , 105 , 0 , Z ),"&
" 103 (BC_4 , SP0_RC_p , observe_only , X ) ,"&
" 102 (BC_4 , SP0_RC_n , observe_only , X ) ,"&
" 101 (BC_1 , * , control , 0 ) ,"&
" 100 (AC_1 , SP0_TD_p , output3 , X , 101 , 0 , Z ),"&
" 99 (BC_4 , SP0_RD_p , observe_only , X ) ,"&
" 98 (BC_4 , SP0_RD_n , observe_only , X ) ,"&
" 97 (BC_1 , * , control , 0 ) ,"&
" 96 (AC_1 , SP2_TB_p , output3 , X , 97 , 0 , Z ),"&
" 95 (BC_4 , SP2_RB_p , observe_only , X ) ,"&
" 94 (BC_4 , SP2_RB_n , observe_only , X ) ,"&
" 93 (BC_1 , * , control , 0 ) ,"&
" 92 (AC_1 , SP2_TA_p , output3 , X , 93 , 0 , Z ),"&
" 91 (BC_4 , SP2_RA_p , observe_only , X ) ,"&
" 90 (BC_4 , SP2_RA_n , observe_only , X ) ,"&
" 89 (BC_1 , * , control , 0 ) ,"&
" 88 (AC_1 , SP10_TA_p , output3 , X , 89 , 0 , Z ),"&
" 87 (BC_4 , SP10_RA_p , observe_only , X ) ,"&
" 86 (BC_4 , SP10_RA_n , observe_only , X ) ,"&
" 85 (BC_1 , * , control , 0 ) ,"&
" 84 (AC_1 , SP10_TB_p , output3 , X , 85 , 0 , Z ),"&
" 83 (BC_4 , SP10_RB_p , observe_only , X ) ,"&
" 82 (BC_4 , SP10_RB_n , observe_only , X ) ,"&
" 81 (BC_1 , * , control , 0 ) ,"&
" 80 (AC_1 , SP4_TB_p , output3 , X , 81 , 0 , Z ),"&
" 79 (BC_4 , SP4_RB_p , observe_only , X ) ,"&
" 78 (BC_4 , SP4_RB_n , observe_only , X ) ,"&
" 77 (BC_1 , * , control , 0 ) ,"&
" 76 (AC_1 , SP4_TA_p , output3 , X , 77 , 0 , Z ),"&
" 75 (BC_4 , SP4_RA_p , observe_only , X ) ,"&
" 74 (BC_4 , SP4_RA_n , observe_only , X ) ,"&
" 73 (BC_1 , * , control , 0 ) ,"&
" 72 (AC_1 , SP12_TA_p , output3 , X , 73 , 0 , Z ),"&
" 71 (BC_4 , SP12_RA_p , observe_only , X ) ,"&
" 70 (BC_4 , SP12_RA_n , observe_only , X ) ,"&
" 69 (BC_1 , * , control , 0 ) ,"&
" 68 (AC_1 , SP12_TB_p , output3 , X , 69 , 0 , Z ),"&
" 67 (BC_4 , SP12_RB_p , observe_only , X ) ,"&
" 66 (BC_4 , SP12_RB_n , observe_only , X ) ,"&
" 65 (BC_1 , * , control , 0 ) ,"&
" 64 (AC_1 , SP6_TB_p , output3 , X , 65 , 0 , Z ),"&
" 63 (BC_4 , SP6_RB_p , observe_only , X ) ,"&
" 62 (BC_4 , SP6_RB_n , observe_only , X ) ,"&
" 61 (BC_1 , * , control , 0 ) ,"&
" 60 (AC_1 , SP6_TA_p , output3 , X , 61 , 0 , Z ),"&
" 59 (BC_4 , SP6_RA_p , observe_only , X ) ,"&
" 58 (BC_4 , SP6_RA_n , observe_only , X ) ,"&
" 57 (BC_1 , * , control , 0 ) ,"&
" 56 (AC_1 , SP6_TC_p , output3 , X , 57 , 0 , Z ),"&
" 55 (BC_4 , SP6_RC_p , observe_only , X ) ,"&
" 54 (BC_4 , SP6_RC_n , observe_only , X ) ,"&
" 53 (BC_1 , * , control , 0 ) ,"&
" 52 (AC_1 , SP6_TD_p , output3 , X , 53 , 0 , Z ),"&
" 51 (BC_4 , SP6_RD_p , observe_only , X ) ,"&
" 50 (BC_4 , SP6_RD_n , observe_only , X ) ,"&
" 49 (BC_2 , * , control , 0 ) ,"&
" 48 (LV_BC_7 , SP4_PWRDN , bidir , X , 49 , 0 , Z ),"&
" 47 (LV_BC_7 , SP5_PWRDN , bidir , X , 49 , 0 , Z ),"&
" 46 (LV_BC_7 , SP6_PWRDN , bidir , X , 49 , 0 , Z ),"&
" 45 (LV_BC_7 , SP7_PWRDN , bidir , X , 49 , 0 , Z ),"&
" 44 (BC_2 , * , control , 0 ) ,"&
" 43 (LV_BC_7 , SP14_PWRDN , bidir , X , 44 , 0 , Z ),"&
" 42 (LV_BC_7 , SP10_PWRDN , bidir , X , 44 , 0 , Z ),"&
" 41 (LV_BC_7 , SP8_PWRDN , bidir , X , 44 , 0 , Z ),"&
" 40 (LV_BC_7 , SP11_PWRDN , bidir , X , 44 , 0 , Z ),"&
" 39 (BC_2 , * , control , 0 ) ,"&
" 38 (LV_BC_7 , INT_b , bidir , X , 39 , 0 , Z ),"&
" 37 (BC_2 , * , control , 0 ) ,"&
" 36 (LV_BC_7 , MCES , bidir , X , 37 , 0 , Z ),"&
" 35 (BC_2 , * , control , 0 ) ,"&
" 34 (LV_BC_7 , SP2_MODESEL , bidir , X , 35 , 0 , Z ),"&
" 33 (LV_BC_7 , SP15_PWRDN , bidir , X , 35 , 0 , Z ),"&
" 32 (BC_0 , * , internal , 0 ) ,"&
" 31 (BC_0 , * , internal , X ),"&
" 30 (BC_2 , * , control , 0 ) ,"&
" 29 (LV_BC_7 , SP_CLK_SEL , bidir , X , 30 , 0 , Z ),"&
" 28 (BC_2 , * , control , 0 ) ,"&
" 27 (LV_BC_7 , SW_RST_b , bidir , X , 28 , 0 , Z ),"&
" 26 (LV_BC_7 , SP4_MODESEL , bidir , X , 35 , 0 , Z ),"&
" 25 (LV_BC_7 , SP12_PWRDN , bidir , X , 35 , 0 , Z ),"&
" 24 (BC_2 , * , control , 0 ) ,"&
" 23 (LV_BC_7 , SP6_MODESEL , bidir , X , 24 , 0 , Z ),"&
" 22 (BC_0 , * , internal , 0 ) ,"&
" 21 (LV_BC_7 , I2C_DISABLE , bidir , X , 30 , 0 , Z ),"&
" 20 (LV_BC_7 , SP9_PWRDN , bidir , X , 24 , 0 , Z ),"&
" 19 (LV_BC_7 , SP13_PWRDN , bidir , X , 24 , 0 , Z ),"&
" 18 (LV_BC_7 , SP1_PWRDN , bidir , X , 24 , 0 , Z ),"&
" 17 (BC_2 , * , control , 0 ) ,"&
" 16 (LV_BC_7 , SP3_PWRDN , bidir , X , 17 , 0 , Z ),"&
" 15 (LV_BC_7 , I2C_MA , bidir , X , 30 , 0 , Z ),"&
" 14 (LV_BC_7 , I2C_SA(0) , bidir , X , 30 , 0 , Z ),"&
" 13 (BC_2 , * , control , 0 ) ,"&
" 12 (LV_BC_7 , I2C_SA(1) , bidir , X , 13 , 0 , Z ),"&
" 11 (LV_BC_7 , SP2_PWRDN , bidir , X , 17 , 0 , Z ),"&
" 10 (BC_2 , * , control , 0 ) ,"&
" 9 (LV_BC_7 , I2C_SCLK , bidir , X , 10 , 0 , Z ),"&
" 8 (LV_BC_7 , SP0_MODESEL , bidir , X , 13 , 0 , Z ),"&
" 7 (LV_BC_7 , SP_IO_SPEED(0) , bidir , X , 13 , 0 , Z ),"&
" 6 (BC_2 , * , control , 0 ) ,"&
" 5 (LV_BC_7 , I2C_SD , bidir , X , 6 , 0 , Z ),"&
" 4 (LV_BC_7 , I2C_SEL , bidir , X , 13 , 0 , Z ),"&
" 3 (BC_2 , * , control , 0 ) ,"&
" 2 (LV_BC_7 , SP_IO_SPEED(1) , bidir , X , 3 , 0 , Z ),"&
" 1 (LV_BC_7 , SP_RX_SWAP , bidir , X , 3 , 0 , Z ),"&
" 0 (LV_BC_7 , SP_TX_SWAP , bidir , X , 3 , 0 , Z ) ";
attribute AIO_COMPONENT_CONFORMANCE of Tsi577Z1: entity is "STD_1149_6_2003";
attribute AIO_Pin_Behavior of Tsi577Z1: entity is
"SP6_TD_p;"&
"SP6_TC_p;"&
"SP6_TB_p;"&
"SP6_TA_p;"&
"SP12_TB_p;"&
"SP12_TA_p;"&
"SP4_TB_p;"&
"SP4_TA_p;"&
"SP10_TB_p;"&
"SP10_TA_p;"&
"SP2_TB_p;"&
"SP2_TA_p;"&
"SP0_TD_p;"&
"SP0_TC_p;"&
"SP0_TB_p;"&
"SP0_TA_p;"&
"SP0_RB_p[111] : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
"SP0_RA_p[107] : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
"SP0_RC_p[103] : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
"SP0_RD_p[99] : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
"SP2_RB_p[95] : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
"SP2_RA_p[91] : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
"SP10_RA_p[87] : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
"SP10_RB_p[83] : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
"SP4_RB_p[79] : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
"SP4_RA_p[75] : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
"SP12_RA_p[71] : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
"SP12_RB_p[67] : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
"SP6_RB_p[63] : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
"SP6_RA_p[59] : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
"SP6_RC_p[55] : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
"SP6_RD_p[51] : LP_Time=2.30e-07 HP_Time=7.00e-06";
end Tsi577Z1;
-- VHDL package to be uploaded
--package LVS_BSCAN_CELLS is
-- use STD_1149_1_2001.all;
-- constant LV_BC_7: CELL_INFO;
--
--end LVS_BSCAN_CELLS;
--package body LVS_BSCAN_CELLS is
-- use STD_1149_1_2001.all;
-- constant LV_BC_7: CELL_INFO :=
-- ((BIDIR_IN, EXTEST, PI), (BIDIR_OUT, EXTEST, PO),
-- (BIDIR_IN, SAMPLE, PI), (BIDIR_OUT, SAMPLE, PI),
-- (BIDIR_IN, INTEST, X), (BIDIR_OUT, INTEST, PI));
--
--end LVS_BSCAN_CELLS;
--