-- Copyright (C) 1998-2005 Altera Corporation
--
-- File Name : 7064SL84.BSD
-- Device : EPM7064SL84
-- Package : 84-Pin Plastic J-Leaded Chip Carrier
-- BSDL Version : 3.01
-- BSDL Status : Final
-- Date Created : 12/8/1998
-- Created by : Altera BSDL Generation Program Ver. 1.20
-- Verification : Software syntax checked on:
-- Agilent Technologies 3070 BSDL Compiler
-- ASSET ScanWorks ver. 3.1.1
-- Corelis ScanPlus TPG ver. 4.12
-- Genrad BSDL syntax checker ver. 4.01, a component
-- of Scan Pathfinder(tm) and BasicSCAN(tm)
-- GOEPEL Electronics' CASCON-GALAXY(R) ver. 4.0
-- JTAG Technologies BSDL Converter ver. 2.4
--
-- Documentation : MAX 7000 Family Datasheet
-- AN39: JTAG Boundary Scan Testing for Altera Devices
--
-- *********************************************************************
-- * IMPORTANT NOTICE *
-- *********************************************************************
--
-- Altera, MAX 7000S and EPM7064S are trademarks of Altera
-- Corporation. Altera products, marketed under trademarks, are
-- protected under numerous US and foreign patents and pending
-- applications, maskwork rights, and copyrights. Altera warrants
-- performance of its semiconductor products to current specifications
-- in accordance with Altera's standard warranty, but reserves the
-- right to make changes to any products and services at any time
-- without notice. Altera assumes no responsibility or liability
-- arising out of the application or use of any information, product,
-- or service described herein except as expressly agreed to in
-- writing by Altera Corporation. Altera customers are advised to
-- obtain the latest version of device specifications before relying
-- on any published information and before placing orders for products
-- or services.
--
-- *********************************************************************
-- * ENTITY DEFINITION WITH PORTS *
-- *********************************************************************
entity EPM7064SL84 is
generic (PHYSICAL_PIN_MAP : string := "PLCC84");
port (
--I/O Pins
IO4 , IO5 , IO6 , IO8 , IO9 , IO10 , IO11 ,
IO12 , IO15 , IO16 , IO17 , IO18 , IO20 , IO21 ,
IO22 , IO24 , IO25 , IO27 , IO28 , IO29 , IO30 ,
IO31 , IO33 , IO34 , IO35 , IO36 , IO37 , IO39 ,
IO40 , IO41 , IO44 , IO45 , IO46 , IO48 , IO49 ,
IO50 , IO51 , IO52 , IO54 , IO55 , IO56 , IO57 ,
IO58 , IO60 , IO61 , IO63 , IO64 , IO65 , IO67 ,
IO68 , IO69 , IO70 , IO73 , IO74 , IO75 , IO76 ,
IO77 , IO79 , IO80 , IO81 : linkage bit;
--Dedicated Input Pins
IN1 , IN2 , IN83 , IN84 : linkage bit;
--JTAG Ports
TCK , TMS , TDI : in bit;
TDO : out bit;
--Power Pins
VCC : linkage bit_vector (1 to 8);
--Ground Pins
GND : linkage bit_vector (1 to 8)
);
use STD_1149_1_1994.all;
attribute COMPONENT_CONFORMANCE of EPM7064SL84 :
entity is "STD_1149_1_1993";
-- *********************************************************************
-- * PIN MAPPING *
-- *********************************************************************
attribute PIN_MAP of EPM7064SL84 : entity is PHYSICAL_PIN_MAP;
constant PLCC84 : PIN_MAP_STRING :=
--I/O Pins
"IO4 : 4 , IO5 : 5 , IO6 : 6 , IO8 : 8 , "&
"IO9 : 9 , IO10 : 10 , IO11 : 11 , IO12 : 12 , "&
"IO15 : 15 , IO16 : 16 , IO17 : 17 , IO18 : 18 , "&
"IO20 : 20 , IO21 : 21 , IO22 : 22 , IO24 : 24 , "&
"IO25 : 25 , IO27 : 27 , IO28 : 28 , IO29 : 29 , "&
"IO30 : 30 , IO31 : 31 , IO33 : 33 , IO34 : 34 , "&
"IO35 : 35 , IO36 : 36 , IO37 : 37 , IO39 : 39 , "&
"IO40 : 40 , IO41 : 41 , IO44 : 44 , IO45 : 45 , "&
"IO46 : 46 , IO48 : 48 , IO49 : 49 , IO50 : 50 , "&
"IO51 : 51 , IO52 : 52 , IO54 : 54 , IO55 : 55 , "&
"IO56 : 56 , IO57 : 57 , IO58 : 58 , IO60 : 60 , "&
"IO61 : 61 , IO63 : 63 , IO64 : 64 , IO65 : 65 , "&
"IO67 : 67 , IO68 : 68 , IO69 : 69 , IO70 : 70 , "&
"IO73 : 73 , IO74 : 74 , IO75 : 75 , IO76 : 76 , "&
"IO77 : 77 , IO79 : 79 , IO80 : 80 , IO81 : 81 , "&
--Dedicated Input Pins
"IN1 : 1 , IN2 : 2 , IN83 : 83 , IN84 : 84 , "&
--JTAG ports
"TCK : 62 , TMS : 23 , TDI : 14 , TDO : 71 , "&
--Power Pins
"VCC : (3 , 13 , 26 , 38 , 43 , 53 , 66 , 78 ), "&
--Ground Pins
"GND : (7 , 19 , 32 , 42 , 47 , 59 , 72 , 82 )";
-- *********************************************************************
-- * IEEE 1149.1 TAP PORTS *
-- *********************************************************************
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_CLOCK of TCK : signal is (10.00e6,BOTH);
-- *********************************************************************
-- * INSTRUCTIONS AND REGISTER ACCESS *
-- *********************************************************************
attribute INSTRUCTION_LENGTH of EPM7064SL84 : entity is 10;
attribute INSTRUCTION_OPCODE of EPM7064SL84 : entity is
"BYPASS (1111111111), "&
"EXTEST (0000000011), "&
"SAMPLE (0001010111), "&
"IDCODE (0001011001)";
attribute INSTRUCTION_CAPTURE of EPM7064SL84 : entity is "0101010101";
attribute IDCODE_REGISTER of EPM7064SL84 : entity is
"0000"& --4-bit Version
"0111000001100100"& --16-bit Part Number (hex 7064)
"00001101110"& --11-bit Manufacturer's Identity
"1"; --Mandatory LSB
attribute REGISTER_ACCESS of EPM7064SL84 : entity is
"DEVICE_ID (IDCODE)";
-- *********************************************************************
-- * BOUNDARY SCAN CELL INFORMATION *
-- *********************************************************************
attribute BOUNDARY_LENGTH of EPM7064SL84 : entity is 1;
attribute BOUNDARY_REGISTER of EPM7064SL84 : entity is
"0 (BC_4, *, internal, 1)";
-- *********************************************************************
-- * DESIGN WARNING *
-- *********************************************************************
attribute DESIGN_WARNING of EPM7064SL84 : entity is
"Although the EPM7064S device contains circuitry to support the"&
"TAP controller, this device does not offer Boundary Scan Cells to"&
"support the EXTEST and SAMPLE/PRELOAD instructions. When the"&
"instruction register is updated with these instructions, the"&
"bypass register is selected.";
end EPM7064SL84;
