-- ***************************************************************
-- Company: Integrated Device Technology, Inc.
--
-- Document number: 35B8020_BS001_04
--
-- Title: BSDL file of Tsi564
-- Generated by : Andi Sugandi
--
-- Release status: formal issue
-- Security level: client use
-- BSDL Version 2001
-- Group ownership: DFT Revision Date:
-- Released by :
-- Revision History:
-- Jan 24, 2005: initial release
-- Sep 14, 2005: changed JTAG ID revision fr 0001 to 0010 for vA2
-- Jul 23, 2009: updated with IDT formatting
--
-- Agilent BSDL Syntax Checker -> Feb 11, 2005
-- Note: Serdes pins are not on boundary scan chain.
--
--
-- ***************************************************************
-- Generated by boundaryScanGenerate 4.1-Build20031130.014 on 01/11/05 16:27:57
-- BSDL Version 2001
entity Tsi564 is
generic (PHYSICAL_PIN_MAP : string := "BGA_399_21");
port (
-- Port List
SP0_TA_P : linkage bit;
SP0_TA_N : linkage bit;
SP0_RA_P : linkage bit;
SP0_RA_N : linkage bit;
SP0_TB_P : linkage bit;
SP0_TB_N : linkage bit;
SP0_RB_P : linkage bit;
SP0_RB_N : linkage bit;
SP0_TC_P : linkage bit;
SP0_TC_N : linkage bit;
SP0_RC_P : linkage bit;
SP0_RC_N : linkage bit;
SP0_TD_P : linkage bit;
SP0_TD_N : linkage bit;
SP0_RD_P : linkage bit;
SP0_RD_N : linkage bit;
SP0_RREF : linkage bit;
SP0_AVDD : linkage bit;
SP0_VTT : linkage bit;
SP2_TA_P : linkage bit;
SP2_TA_N : linkage bit;
SP2_RA_P : linkage bit;
SP2_RA_N : linkage bit;
SP2_TB_P : linkage bit;
SP2_TB_N : linkage bit;
SP2_RB_P : linkage bit;
SP2_RB_N : linkage bit;
SP2_TC_P : linkage bit;
SP2_TC_N : linkage bit;
SP2_RC_P : linkage bit;
SP2_RC_N : linkage bit;
SP2_TD_P : linkage bit;
SP2_TD_N : linkage bit;
SP2_RD_P : linkage bit;
SP2_RD_N : linkage bit;
SP2_RREF : linkage bit;
SP2_AVDD : linkage bit;
SP2_VTT : linkage bit;
SP4_TA_P : linkage bit;
SP4_TA_N : linkage bit;
SP4_RA_P : linkage bit;
SP4_RA_N : linkage bit;
SP4_TB_P : linkage bit;
SP4_TB_N : linkage bit;
SP4_RB_P : linkage bit;
SP4_RB_N : linkage bit;
SP4_TC_P : linkage bit;
SP4_TC_N : linkage bit;
SP4_RC_P : linkage bit;
SP4_RC_N : linkage bit;
SP4_TD_P : linkage bit;
SP4_TD_N : linkage bit;
SP4_RD_P : linkage bit;
SP4_RD_N : linkage bit;
SP4_RREF : linkage bit;
SP4_AVDD : linkage bit;
SP4_VTT : linkage bit;
SP6_TA_P : linkage bit;
SP6_TA_N : linkage bit;
SP6_RA_P : linkage bit;
SP6_RA_N : linkage bit;
SP6_TB_P : linkage bit;
SP6_TB_N : linkage bit;
SP6_RB_P : linkage bit;
SP6_RB_N : linkage bit;
SP6_TC_P : linkage bit;
SP6_TC_N : linkage bit;
SP6_RC_P : linkage bit;
SP6_RC_N : linkage bit;
SP6_TD_P : linkage bit;
SP6_TD_N : linkage bit;
SP6_RD_P : linkage bit;
SP6_RD_N : linkage bit;
SP6_RREF : linkage bit;
SP6_AVDD : linkage bit;
SP6_VTT : linkage bit;
P_CLK : in bit;
S_CLK_1_P : linkage bit;
S_CLK_1_N : linkage bit;
S_CLK_2_P : linkage bit;
S_CLK_2_N : linkage bit;
I2C_SCLK : inout bit;
I2C_SD : inout bit;
I2C_DISABLE : inout bit;
HARD_RST_B : linkage bit;
INT_B : inout bit;
SW_RST_B : inout bit;
TCK : in bit;
TMS : in bit;
TDI : in bit;
TDO : out bit;
TRST_B : in bit;
DI : in bit;
DO : out bit;
SP_IO_SPEED : inout bit_vector( 1 downto 0 );
SP0_PWRDN : inout bit;
SP1_PWRDN : inout bit;
SP2_PWRDN : inout bit;
SP3_PWRDN : inout bit;
SP4_PWRDN : inout bit;
SP5_PWRDN : inout bit;
SP6_PWRDN : inout bit;
SP7_PWRDN : inout bit;
TEST8_PWRDN : inout bit;
TEST9_PWRDN : inout bit;
TEST10_PWRDN : inout bit;
TEST11_PWRDN : inout bit;
TEST12_PWRDN : inout bit;
TEST13_PWRDN : inout bit;
TEST14_PWRDN : inout bit;
TEST15_PWRDN : inout bit;
SP0_MODESEL : inout bit;
SP2_MODESEL : inout bit;
SP4_MODESEL : inout bit;
SP6_MODESEL : inout bit;
TEST8_MODESEL : inout bit;
TEST10_MODESEL : inout bit;
TEST12_MODESEL : inout bit;
TEST14_MODESEL : inout bit;
DEV_ID_SEL : linkage bit;
SP_RX_SWAP : inout bit;
SP_TX_SWAP : inout bit;
SPY_CLK_0 : linkage bit;
SPY_CLK_1 : linkage bit;
VDD_IO : linkage bit_vector( 11 downto 0 );
VSS_IO : linkage bit_vector( 11 downto 0 );
VDD : linkage bit_vector( 31 downto 0 );
VSS : linkage bit_vector( 30 downto 0 ) );
use STD_1149_1_2001.all;
use LVS_BSCAN_CELLS.all;
attribute COMPONENT_CONFORMANCE of Tsi564: entity is "STD_1149_1_2001";
--Pin mappings
attribute PIN_MAP of Tsi564: entity is PHYSICAL_PIN_MAP;
constant DEFAULT_PACKAGE_NAME: PIN_MAP_STRING :=
"SP0_TA_P : e2 , " &
"SP0_TA_N : e1 , " &
"SP0_RA_P : e4 , " &
"SP0_RA_N : e5 , " &
"SP0_TB_P : g1 , " &
"SP0_TB_N : g2 , " &
"SP0_RB_P : g5 , " &
"SP0_RB_N : g4 , " &
"SP0_TC_P : j2 , " &
"SP0_TC_N : j1 , " &
"SP0_RC_P : j4 , " &
"SP0_RC_N : j5 , " &
"SP0_TD_P : l1 , " &
"SP0_TD_N : l2 , " &
"SP0_RD_P : l5 , " &
"SP0_RD_N : l4 , " &
"SP0_RREF : h4 , " &
"SP0_AVDD : h5 , " &
"SP0_VTT : k5 , " &
"SP2_TA_P : w8 , " &
"SP2_TA_N : y8 , " &
"SP2_RA_P : u8 , " &
"SP2_RA_N : t8 , " &
"SP2_TB_P : y10 , " &
"SP2_TB_N : w10 , " &
"SP2_RB_P : t10 , " &
"SP2_RB_N : u10 , " &
"SP2_TC_P : w12 , " &
"SP2_TC_N : y12 , " &
"SP2_RC_P : u12 , " &
"SP2_RC_N : t12 , " &
"SP2_TD_P : y14 , " &
"SP2_TD_N : w14 , " &
"SP2_RD_P : t14 , " &
"SP2_RD_N : u14 , " &
"SP2_RREF : u11 , " &
"SP2_AVDD : t11 , " &
"SP2_VTT : t13 , " &
"SP4_TA_P : n19 , " &
"SP4_TA_N : n20 , " &
"SP4_RA_P : n17 , " &
"SP4_RA_N : n16 , " &
"SP4_TB_P : l20 , " &
"SP4_TB_N : l19 , " &
"SP4_RB_P : l16 , " &
"SP4_RB_N : l17 , " &
"SP4_TC_P : j19 , " &
"SP4_TC_N : j20 , " &
"SP4_RC_P : j17 , " &
"SP4_RC_N : j16 , " &
"SP4_TD_P : g20 , " &
"SP4_TD_N : g19 , " &
"SP4_RD_P : g16 , " &
"SP4_RD_N : g17 , " &
"SP4_RREF : k17 , " &
"SP4_AVDD : k16 , " &
"SP4_VTT : h16 , " &
"SP6_TA_P : b14 , " &
"SP6_TA_N : a14 , " &
"SP6_RA_P : d14 , " &
"SP6_RA_N : e14 , " &
"SP6_TB_P : a12 , " &
"SP6_TB_N : b12 , " &
"SP6_RB_P : e12 , " &
"SP6_RB_N : d12 , " &
"SP6_TC_P : b10 , " &
"SP6_TC_N : a10 , " &
"SP6_RC_P : d10 , " &
"SP6_RC_N : e10 , " &
"SP6_TD_P : a8 , " &
"SP6_TD_N : b8 , " &
"SP6_RD_P : e8 , " &
"SP6_RD_N : d8 , " &
"SP6_RREF : d11 , " &
"SP6_AVDD : e11 , " &
"SP6_VTT : e9 , " &
"P_CLK : y1 , " &
"S_CLK_1_P : b18 , " &
"S_CLK_1_N : b19 , " &
"S_CLK_2_P : d18 , " &
"S_CLK_2_N : d19 , " &
"I2C_SCLK : y19 , " &
"I2C_SD : w18 , " &
"I2C_DISABLE : u18 , " &
"HARD_RST_B : y3 , " &
"INT_B : u2 , " &
"SW_RST_B : v3 , " &
"TCK : y20 , " &
"TMS : u20 , " &
"TDI : v20 , " &
"TDO : v19 , " &
"TRST_B : w20 , " &
"DI : w3 , " &
"DO : w2 , " &
"SP_IO_SPEED :(u16 , " & -- SP_IO_SPEED[1]
"t16 ), " & -- SP_IO_SPEED[0]
"SP0_PWRDN : w16 , " &
"SP1_PWRDN : y16 , " &
"SP2_PWRDN : w17 , " &
"SP3_PWRDN : y17 , " &
"SP4_PWRDN : n2 , " &
"SP5_PWRDN : n3 , " &
"SP6_PWRDN : p1 , " &
"SP7_PWRDN : p3 , " &
"TEST8_PWRDN : n5 , " &
"TEST9_PWRDN : p4 , " &
"TEST10_PWRDN : r2 , " &
"TEST11_PWRDN : r3 , " &
"TEST12_PWRDN : r5 , " &
"TEST13_PWRDN : t1 , " &
"TEST14_PWRDN : t3 , " &
"TEST15_PWRDN : t4 , " &
"SP0_MODESEL : v16 , " &
"SP2_MODESEL : v17 , " &
"SP4_MODESEL : u3 , " &
"SP6_MODESEL : u5 , " &
"TEST8_MODESEL : w5 , " &
"TEST10_MODESEL : y4 , " &
"TEST12_MODESEL : t6 , " &
"TEST14_MODESEL : v6 , " &
"DEV_ID_SEL : t17 , " &
"SP_RX_SWAP : t19 , " &
"SP_TX_SWAP : t20 , " &
"SPY_CLK_0 : v1 , " &
"SPY_CLK_1 : v4 , " &
"VDD_IO :(v2 , " & -- VDD_IO[11]
"y2 , " & -- VDD_IO[10]
"w4 , " & -- VDD_IO[9]
"t2 , " & -- VDD_IO[8]
"n4 , " & -- VDD_IO[7]
"m2 , " & -- VDD_IO[6]
"r4 , " & -- VDD_IO[5]
"p2 , " & -- VDD_IO[4]
"u4 , " & -- VDD_IO[3]
"u19 , " & -- VDD_IO[2]
"w19 , " & -- VDD_IO[1]
"u17 ), " & -- VDD_IO[0]
"VSS_IO :(y18 , " & -- VSS_IO[11]
"v18 , " & -- VSS_IO[10]
"t18 , " & -- VSS_IO[9]
"y5 , " & -- VSS_IO[8]
"v5 , " & -- VSS_IO[7]
"t5 , " & -- VSS_IO[6]
"p5 , " & -- VSS_IO[5]
"m3 , " & -- VSS_IO[4]
"w1 , " & -- VSS_IO[3]
"u1 , " & -- VSS_IO[2]
"r1 , " & -- VSS_IO[1]
"n1 ), " & -- VSS_IO[0]
"VDD : (g8 , " & -- VDD[31]
"g10 , " & -- VDD[30]
"g12 , " & -- VDD[29]
"g14 , " & -- VDD[28]
"h7 , " & -- VDD[27]
"h9 , " & -- VDD[26]
"h11 , " & -- VDD[25]
"h13 , " & -- VDD[24]
"j8 , " & -- VDD[23]
"j10 , " & -- VDD[22]
"j12 , " & -- VDD[21]
"j14 , " & -- VDD[20]
"k7 , " & -- VDD[19]
"k9 , " & -- VDD[18]
"k11 , " & -- VDD[17]
"k13 , " & -- VDD[16]
"l8 , " & -- VDD[15]
"l10 , " & -- VDD[14]
"l12 , " & -- VDD[13]
"l14 , " & -- VDD[12]
"m7 , " & -- VDD[11]
"m9 , " & -- VDD[10]
"m11 , " & -- VDD[9]
"m13 , " & -- VDD[8]
"n8 , " & -- VDD[7]
"n10 , " & -- VDD[6]
"n12 , " & -- VDD[5]
"n14 , " & -- VDD[4]
"p7 , " & -- VDD[3]
"p9 , " & -- VDD[2]
"p11 , " & -- VDD[1]
"p13 ), " & -- VDD[0]
"VSS : (g7 , " & -- VSS[30]
"g9 , " & -- VSS[29]
"g11 , " & -- VSS[28]
"g13 , " & -- VSS[27]
"h8 , " & -- VSS[26]
"h10 , " & -- VSS[25]
"h12 , " & -- VSS[24]
"h14 , " & -- VSS[23]
"j7 , " & -- VSS[22]
"j9 , " & -- VSS[21]
"j11 , " & -- VSS[20]
"j13 , " & -- VSS[19]
"k8 , " & -- VSS[18]
"k10 , " & -- VSS[17]
"k12 , " & -- VSS[16]
"k14 , " & -- VSS[15]
"l7 , " & -- VSS[14]
"l9 , " & -- VSS[13]
"l11 , " & -- VSS[12]
"l13 , " & -- VSS[11]
"m8 , " & -- VSS[10]
"m10 , " & -- VSS[9]
"m14 , " & -- VSS[8]
"n7 , " & -- VSS[7]
"n9 , " & -- VSS[6]
"n11 , " & -- VSS[5]
"n13 , " & -- VSS[4]
"p8 , " & -- VSS[3]
"p10 , " & -- VSS[2]
"p12 , " & -- VSS[1]
"p14 ) " ; -- VSS[0]
attribute TAP_SCAN_RESET of TRST_B : signal is true;
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_CLOCK of TCK : signal is (1.0000000000000000000e+07, BOTH);
attribute INSTRUCTION_LENGTH of Tsi564: entity is 55;
attribute INSTRUCTION_OPCODE of Tsi564: entity is
"IDCODE (1111111111111111111111111111111111111111111111111111110)," &
"BYPASS (0000000000000000000000000000000000000000000000000000000," &
"1111111111111111111111111111111111111111111111111111111)," &
"EXTEST (1111111111111111111111111111111111111111111111111101000)," &
"SAMPLE (1111111111111111111111111111111111111111111111111111000)," &
"PRELOAD (1111111111111111111111111111111111111111111111111111000)," &
"HIGHZ (1111111111111111111111111111111111111111111111111001111)," &
"CLAMP (1111111111111111111111111111111111111111111111111101111) " ;
attribute INSTRUCTION_CAPTURE of Tsi564: entity is
"xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx01";
attribute IDCODE_REGISTER of Tsi564: entity is
"0010" & -- version
"0000010101100100" & -- part number
"00010110011" & -- manufacturer's identity
"1"; -- required by 1149.1
attribute REGISTER_ACCESS of Tsi564: entity is
"BOUNDARY ( SAMPLE, PRELOAD )," &
"BYPASS ( HIGHZ, CLAMP, BYPASS ) " ;
--Boundary scan definition
attribute BOUNDARY_LENGTH of Tsi564: entity is 49;
attribute BOUNDARY_REGISTER of Tsi564: entity is
-- num cell port function safe [ccell disval rslt]
" 48 (BC_4 , P_CLK , clock , X ) ,"&
" 47 (BC_2 , * , control , 0 ) ,"&
" 46 (LV_BC_7 , I2C_SCLK , bidir , X , 47 , 0 , Z ),"&
" 45 (BC_2 , * , control , 0 ) ,"&
" 44 (LV_BC_7 , I2C_SD , bidir , X , 45 , 0 , Z ),"&
" 43 (BC_2 , * , control , 0 ) ,"&
" 42 (LV_BC_7 , I2C_DISABLE , bidir , X , 43 , 0 , Z ),"&
" 41 (BC_2 , * , control , 0 ) ,"&
" 40 (LV_BC_7 , INT_B , bidir , X , 41 , 0 , Z ),"&
" 39 (BC_2 , * , control , 0 ) ,"&
" 38 (LV_BC_7 , SW_RST_B , bidir , X , 39 , 0 , Z ),"&
" 37 (BC_2 , DI , input , X ) ,"&
" 36 (BC_2 , * , control , 0 ) ,"&
" 35 (BC_2 , DO , output3 , X , 36 , 0 , Z ),"&
" 34 (BC_2 , * , control , 0 ) ,"&
" 33 (LV_BC_7 , SP_IO_SPEED(1) , bidir , X , 34 , 0 , Z ),"&
" 32 (LV_BC_7 , SP_IO_SPEED(0) , bidir , X , 34 , 0 , Z ),"&
" 31 (LV_BC_7 , SP0_PWRDN , bidir , X , 34 , 0 , Z ),"&
" 30 (LV_BC_7 , SP1_PWRDN , bidir , X , 34 , 0 , Z ),"&
" 29 (BC_2 , * , control , 0 ) ,"&
" 28 (LV_BC_7 , SP2_PWRDN , bidir , X , 29 , 0 , Z ),"&
" 27 (LV_BC_7 , SP3_PWRDN , bidir , X , 29 , 0 , Z ),"&
" 26 (BC_2 , * , control , 0 ) ,"&
" 25 (LV_BC_7 , SP4_PWRDN , bidir , X , 26 , 0 , Z ),"&
" 24 (LV_BC_7 , SP5_PWRDN , bidir , X , 26 , 0 , Z ),"&
" 23 (LV_BC_7 , SP6_PWRDN , bidir , X , 26 , 0 , Z ),"&
" 22 (LV_BC_7 , SP7_PWRDN , bidir , X , 26 , 0 , Z ),"&
" 21 (BC_2 , * , control , 0 ) ,"&
" 20 (LV_BC_7 , TEST8_PWRDN , bidir , X , 21 , 0 , Z ),"&
" 19 (LV_BC_7 , TEST9_PWRDN , bidir , X , 21 , 0 , Z ),"&
" 18 (LV_BC_7 , TEST10_PWRDN , bidir , X , 21 , 0 , Z ),"&
" 17 (LV_BC_7 , TEST11_PWRDN , bidir , X , 21 , 0 , Z ),"&
" 16 (BC_2 , * , control , 0 ) ,"&
" 15 (LV_BC_7 , TEST12_PWRDN , bidir , X , 16 , 0 , Z ),"&
" 14 (LV_BC_7 , TEST13_PWRDN , bidir , X , 16 , 0 , Z ),"&
" 13 (LV_BC_7 , TEST14_PWRDN , bidir , X , 16 , 0 , Z ),"&
" 12 (LV_BC_7 , TEST15_PWRDN , bidir , X , 16 , 0 , Z ),"&
" 11 (LV_BC_7 , SP0_MODESEL , bidir , X , 29 , 0 , Z ),"&
" 10 (LV_BC_7 , SP2_MODESEL , bidir , X , 29 , 0 , Z ),"&
" 9 (BC_2 , * , control , 0 ) ,"&
" 8 (LV_BC_7 , SP4_MODESEL , bidir , X , 9 , 0 , Z ),"&
" 7 (LV_BC_7 , SP6_MODESEL , bidir , X , 9 , 0 , Z ),"&
" 6 (LV_BC_7 , TEST8_MODESEL , bidir , X , 9 , 0 , Z ),"&
" 5 (LV_BC_7 , TEST10_MODESEL , bidir , X , 9 , 0 , Z ),"&
" 4 (BC_2 , * , control , 0 ) ,"&
" 3 (LV_BC_7 , TEST12_MODESEL , bidir , X , 4 , 0 , Z ),"&
" 2 (LV_BC_7 , TEST14_MODESEL , bidir , X , 4 , 0 , Z ),"&
" 1 (LV_BC_7 , SP_RX_SWAP , bidir , X , 4 , 0 , Z ),"&
" 0 (LV_BC_7 , SP_TX_SWAP , bidir , X , 4 , 0 , Z ) ";
end Tsi564;
--
-- package LVS_BSCAN_CELLS is
-- use STD_1149_1_2001.all;
-- constant LV_BC_7: CELL_INFO;
--
-- end LVS_BSCAN_CELLS;
-- package body LVS_BSCAN_CELLS is
-- use STD_1149_1_2001.all;
-- constant LV_BC_7: CELL_INFO :=
-- ((BIDIR_IN, EXTEST, PI), (BIDIR_OUT, EXTEST, PO),
-- (BIDIR_IN, SAMPLE, PI), (BIDIR_OUT, SAMPLE, PI),
-- (BIDIR_IN, INTEST, X), (BIDIR_OUT, INTEST, PI));
--
-- end LVS_BSCAN_CELLS;
--