--$ XILINX$RCSfile$
--$ XILINX$Revision$
--
-- BSDL file for device XC4002XL, package VQ100
-- Xilinx, Inc. $State$ $Date$
-- Generated by createBSDL 2.10
--
-- For technical support, contact Xilinx as follows:
-- North America 1-800-255-7778 hotline@xilinx.com
-- United Kingdom (44) 1932 820821 ukhelp@xilinx.com
-- France (33) 1 3463 0100 frhelp@xilinx.com
-- Germany (49) 89 991 54930 dlhelp@xilinx.com
-- Japan (81) 3-3297-9163 jhotline@xilinx.com
--
-- This BSDL file reflects the pre-configuration JTAG behavior. To reflect
-- the post-configuration JTAG behavior (if any), edit this file as described
-- below. Many of these changes are demonstrated by commented-out template
-- lines preceeding the lines they would replace:
--
-- 1. Enable USER instructions as appropriate (see below).
-- 2. For inputs using uncontrolled paths (e.g. PGCK, SGCK), change
-- boundary cell function from 'input' to 'clock' or 'observe_only'.
-- 3. Set disable result of all pads as configured.
-- 4. Set safe state of boundary cells as necessary.
-- 5. Set safe state of INIT output to X, or as necessary (see below).
-- 6. Rename entity if necessary to avoid name collisions.
-- 7. Change INIT port direction from "in" to "inout" (see below).
-- 8. Change COMPLIANCE_PATTERNS to "(PROGRAM) (1)" (see below).
-- 9. Change INIT boundary cells from internal to controlr, output3,
-- and input, respectively (see below).
-- 10. Remove the design warning regarding keeping INIT low.
--
-- NOTE: Post-configuration JTAG is available only if the BSCAN symbol
-- is instantiated in the FPGA design.
-- NOTE: PULLUP symbols must be instantiated on the TMS and TDI pins
-- in the FPGA design to comply with IEEE Std. 1149.1-1993.
entity XC4002XL_VQ100 is
generic (PHYSICAL_PIN_MAP : string := "VQ100" );
port (
CCLK: linkage bit;
DONE: linkage bit;
GND: linkage bit_vector (1 to 8);
-- INIT is not a compliance enable after configuration. For post-configuration
-- operation un-comment the next line and comment out the following line so
-- that INIT is of type inout.
-- INIT: inout bit;
INIT: in bit;
IO2: inout bit;
IO3: inout bit;
IO4: inout bit;
IO5: inout bit;
IO6: inout bit;
IO7: inout bit;
IO8: inout bit;
IO9: inout bit;
IO13: inout bit;
IO14: inout bit;
IO18: inout bit;
IO19: inout bit;
IO20: inout bit;
IO23: inout bit;
IO24: inout bit;
IO25: inout bit;
IO26: inout bit;
IO27: inout bit;
IO28: inout bit;
IO29: inout bit;
IO30: inout bit;
IO37: inout bit;
IO38: inout bit;
IO39: inout bit;
IO40: inout bit;
IO41: inout bit;
IO42: inout bit;
IO43: inout bit;
IO47: inout bit;
IO48: inout bit;
IO49: inout bit;
IO50: inout bit;
IO51: inout bit;
IO52: inout bit;
IO53: inout bit;
IO54: inout bit;
IO60: inout bit;
IO61: inout bit;
IO62: inout bit;
IO63: inout bit;
IO64: inout bit;
IO65: inout bit;
IO66: inout bit;
IO67: inout bit;
IO70: inout bit;
IO71: inout bit;
IO72: inout bit;
IO73: inout bit;
IO74: inout bit;
IO75: inout bit;
IO76: inout bit;
IO77: inout bit;
IO83: inout bit;
IO84: inout bit;
IO85: inout bit;
IO86: inout bit;
IO87: inout bit;
IO88: inout bit;
IO89: inout bit;
IO90: inout bit;
M0: in bit;
M1: inout bit;
M2: in bit;
PROGRAM: in bit;
TCK: in bit;
TDI: in bit;
TDO: out bit;
TMS: in bit;
VDD: linkage bit_vector (1 to 8)
); --end port list
use STD_1149_1_1994.all;
attribute COMPONENT_CONFORMANCE of XC4002XL_VQ100 : entity is
"STD_1149_1_1993";
attribute PIN_MAP of XC4002XL_VQ100 : entity is PHYSICAL_PIN_MAP;
constant VQ100: PIN_MAP_STRING:=
"CCLK:P74," &
"DONE:P50," &
"GND:(P1,P11,P23,P38,P49,P64,P77,P88)," &
"INIT:P36," &
"IO2:P90," &
"IO3:P91," &
"IO4:P94," &
"IO5:P95," &
"IO6:P96," &
"IO7:P97," &
"IO8:P98," &
"IO9:P99," &
"IO13:P2," &
"IO14:P3," &
"IO18:P7," &
"IO19:P9," &
"IO20:P10," &
"IO23:P13," &
"IO24:P14," &
"IO25:P16," &
"IO26:P17," &
"IO27:P18," &
"IO28:P19," &
"IO29:P20," &
"IO30:P21," &
"IO37:P27," &
"IO38:P28," &
"IO39:P29," &
"IO40:P30," &
"IO41:P31," &
"IO42:P32," &
"IO43:P35," &
"IO47:P39," &
"IO48:P40," &
"IO49:P43," &
"IO50:P44," &
"IO51:P45," &
"IO52:P46," &
"IO53:P47," &
"IO54:P48," &
"IO60:P53," &
"IO61:P54," &
"IO62:P55," &
"IO63:P56," &
"IO64:P57," &
"IO65:P58," &
"IO66:P61," &
"IO67:P62," &
"IO70:P65," &
"IO71:P66," &
"IO72:P68," &
"IO73:P69," &
"IO74:P70," &
"IO75:P71," &
"IO76:P72," &
"IO77:P73," &
"IO83:P78," &
"IO84:P79," &
"IO85:P80," &
"IO86:P81," &
"IO87:P82," &
"IO88:P83," &
"IO89:P86," &
"IO90:P87," &
"M0:P24," &
"M1:P22," &
"M2:P26," &
"PROGRAM:P52," &
"TCK:P5," &
"TDI:P4," &
"TDO:P76," &
"TMS:P6," &
"VDD:(P89,P100,P12,P25,P37,P51,P63,P75)";
--end pin map
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_CLOCK of TCK : signal is (2.0e6, LOW);
-- This is conservative. Real max is expected to be (~5MHz, BOTH).
attribute COMPLIANCE_PATTERNS of XC4002XL_VQ100 : entity is
-- INIT is not a compliance enable after configuration. For post-configuration
-- operation un-comment the next line and comment out the corresponding line
-- below.
-- "(PROGRAM) (1)";
--
-- NOTE: If INIT has been high or floating since the later of power-on
-- and the last rising transition of PROGRAM, then the device may
-- be in configuration mode in which case some JTAG instructions
-- will not be available.
"(INIT,PROGRAM) (01)";
attribute INSTRUCTION_LENGTH of XC4002XL_VQ100 : entity is 3;
attribute INSTRUCTION_OPCODE of XC4002XL_VQ100 : entity is
"SAMPLE (001)," & -- Internal capture not valid until after config
"RESERVED (110)," &
"READBACK (100)," & -- Not available during configuration
"CONFIGURE (101)," & -- Not available during configuration
"USER2 (011)," & -- Not available until after configuration
"USER1 (010)," & -- Not available until after configuration
"EXTEST (000)," & -- Not available during configuration
"BYPASS (111)";
attribute INSTRUCTION_CAPTURE of XC4002XL_VQ100 : entity is "X01";
-- MSB of instruction capture is low during configuration.
-- If the device is configured, and a USER instruction is implemented
-- and not private to the FPGA designer, then it should be removed
-- from INSTRUCTION_PRIVATE, and the target register should be defined
-- in REGISTER_ACCESS.
attribute INSTRUCTION_PRIVATE of XC4002XL_VQ100 : entity is
"USER1," &
"USER2," &
"READBACK," &
"RESERVED," &
"CONFIGURE";
attribute REGISTER_ACCESS of XC4002XL_VQ100 : entity is
-- "<reg_name>[<length>] (USER1)," &
-- "<reg_name>[<length>] (USER2)," &
"BYPASS (BYPASS)," &
"BOUNDARY (SAMPLE,EXTEST)";
attribute BOUNDARY_LENGTH of XC4002XL_VQ100 : entity is 200;
attribute BOUNDARY_REGISTER of XC4002XL_VQ100 : entity is
-- cellnum (type, port, function, safe[, ccell, disval, disrslt])
" 0 (BC_1, *, internal, X)," &
" 1 (BC_1, *, internal, X)," &
" 2 (BC_1, *, controlr, 1)," &
" 3 (BC_1, IO83, output3, X, 2, 1, PULL1)," &
" 4 (BC_1, IO83, input, X)," &
" 5 (BC_1, *, controlr, 1)," &
" 6 (BC_1, IO84, output3, X, 5, 1, PULL1)," &
" 7 (BC_1, IO84, input, X)," &
" 8 (BC_1, *, controlr, 1)," &
" 9 (BC_1, IO85, output3, X, 8, 1, PULL1)," &
" 10 (BC_1, IO85, input, X)," &
" 11 (BC_1, *, controlr, 1)," &
" 12 (BC_1, IO86, output3, X, 11, 1, PULL1)," &
" 13 (BC_1, IO86, input, X)," &
" 14 (BC_1, *, controlr, 1)," &
" 15 (BC_1, IO87, output3, X, 14, 1, PULL1)," &
" 16 (BC_1, IO87, input, X)," &
" 17 (BC_1, *, controlr, 1)," &
" 18 (BC_1, IO88, output3, X, 17, 1, PULL1)," &
" 19 (BC_1, IO88, input, X)," &
" 20 (BC_1, *, controlr, 1)," &
" 21 (BC_1, IO89, output3, X, 20, 1, PULL1)," &
" 22 (BC_1, IO89, input, X)," &
" 23 (BC_1, *, controlr, 1)," &
" 24 (BC_1, IO90, output3, X, 23, 1, PULL1)," &
" 25 (BC_1, IO90, input, X)," &
" 26 (BC_1, *, controlr, 1)," &
" 27 (BC_1, IO2, output3, X, 26, 1, PULL1)," &
" 28 (BC_1, IO2, input, X)," &
" 29 (BC_1, *, controlr, 1)," &
" 30 (BC_1, IO3, output3, X, 29, 1, PULL1)," &
" 31 (BC_1, IO3, input, X)," &
" 32 (BC_1, *, controlr, 1)," &
" 33 (BC_1, IO4, output3, X, 32, 1, PULL1)," &
" 34 (BC_1, IO4, input, X)," &
" 35 (BC_1, *, controlr, 1)," &
" 36 (BC_1, IO5, output3, X, 35, 1, PULL1)," &
" 37 (BC_1, IO5, input, X)," &
" 38 (BC_1, *, controlr, 1)," &
" 39 (BC_1, IO6, output3, X, 38, 1, PULL1)," &
" 40 (BC_1, IO6, input, X)," &
" 41 (BC_1, *, controlr, 1)," &
" 42 (BC_1, IO7, output3, X, 41, 1, PULL1)," &
" 43 (BC_1, IO7, input, X)," &
" 44 (BC_1, *, controlr, 1)," &
" 45 (BC_1, IO8, output3, X, 44, 1, PULL1)," &
" 46 (BC_1, IO8, input, X)," &
" 47 (BC_1, *, controlr, 1)," &
" 48 (BC_1, IO9, output3, X, 47, 1, PULL1)," &
" 49 (BC_1, IO9, input, X)," &
" 50 (BC_1, *, controlr, 1)," &
" 51 (BC_1, IO13, output3, X, 50, 1, PULL1)," &
" 52 (BC_1, IO13, input, X)," &
" 53 (BC_1, *, controlr, 1)," &
" 54 (BC_1, IO14, output3, X, 53, 1, PULL1)," &
" 55 (BC_1, IO14, input, X)," &
" 56 (BC_1, *, internal, X)," &
" 57 (BC_1, *, internal, X)," &
" 58 (BC_1, *, internal, X)," &
" 59 (BC_1, *, internal, X)," &
" 60 (BC_1, *, internal, X)," &
" 61 (BC_1, *, internal, X)," &
" 62 (BC_1, *, internal, X)," &
" 63 (BC_1, *, internal, X)," &
" 64 (BC_1, *, internal, X)," &
" 65 (BC_1, *, controlr, 1)," &
" 66 (BC_1, IO18, output3, X, 65, 1, PULL1)," &
" 67 (BC_1, IO18, input, X)," &
" 68 (BC_1, *, controlr, 1)," &
" 69 (BC_1, IO19, output3, X, 68, 1, PULL1)," &
" 70 (BC_1, IO19, input, X)," &
" 71 (BC_1, *, controlr, 1)," &
" 72 (BC_1, IO20, output3, X, 71, 1, PULL1)," &
" 73 (BC_1, IO20, input, X)," &
" 74 (BC_1, *, controlr, 1)," &
" 75 (BC_1, IO23, output3, X, 74, 1, PULL1)," &
" 76 (BC_1, IO23, input, X)," &
" 77 (BC_1, *, controlr, 1)," &
" 78 (BC_1, IO24, output3, X, 77, 1, PULL1)," &
" 79 (BC_1, IO24, input, X)," &
" 80 (BC_1, *, controlr, 1)," &
" 81 (BC_1, IO25, output3, X, 80, 1, PULL1)," &
" 82 (BC_1, IO25, input, X)," &
" 83 (BC_1, *, controlr, 1)," &
" 84 (BC_1, IO26, output3, X, 83, 1, PULL1)," &
" 85 (BC_1, IO26, input, X)," &
" 86 (BC_1, *, controlr, 1)," &
" 87 (BC_1, IO27, output3, X, 86, 1, PULL1)," &
" 88 (BC_1, IO27, input, X)," &
" 89 (BC_1, *, controlr, 1)," &
" 90 (BC_1, IO28, output3, X, 89, 1, PULL1)," &
" 91 (BC_1, IO28, input, X)," &
" 92 (BC_1, *, controlr, 1)," &
" 93 (BC_1, IO29, output3, X, 92, 1, PULL1)," &
" 94 (BC_1, IO29, input, X)," &
" 95 (BC_1, *, controlr, 1)," &
" 96 (BC_1, IO30, output3, X, 95, 1, PULL1)," &
" 97 (BC_1, IO30, input, X)," &
" 98 (BC_1, *, controlr, 1)," &
" 99 (BC_1, M1, output3, X, 98, 1, PULL1)," &
" 100 (BC_1, M1, input, X)," &
" 101 (BC_1, M0, input, X)," &
" 102 (BC_1, M2, input, X)," &
" 103 (BC_1, *, controlr, 1)," &
" 104 (BC_1, IO37, output3, X, 103, 1, PULL1)," &
" 105 (BC_1, IO37, input, X)," &
" 106 (BC_1, *, controlr, 1)," &
" 107 (BC_1, IO38, output3, X, 106, 1, PULL1)," &
" 108 (BC_1, IO38, input, X)," &
" 109 (BC_1, *, controlr, 1)," &
" 110 (BC_1, IO39, output3, X, 109, 1, PULL1)," &
" 111 (BC_1, IO39, input, X)," &
" 112 (BC_1, *, controlr, 1)," &
" 113 (BC_1, IO40, output3, X, 112, 1, PULL1)," &
" 114 (BC_1, IO40, input, X)," &
" 115 (BC_1, *, controlr, 1)," &
" 116 (BC_1, IO41, output3, X, 115, 1, PULL1)," &
" 117 (BC_1, IO41, input, X)," &
" 118 (BC_1, *, controlr, 1)," &
" 119 (BC_1, IO42, output3, X, 118, 1, PULL1)," &
" 120 (BC_1, IO42, input, X)," &
" 121 (BC_1, *, controlr, 1)," &
" 122 (BC_1, IO43, output3, X, 121, 1, PULL1)," &
" 123 (BC_1, IO43, input, X)," &
-- INIT is not a compliance enable after configuration. For post-configuration
-- operation un-comment the next line and comment out the following line.
-- Repeat for registers 124 through 126.
-- " 124 (BC_1, *, controlr, 1)," &
" 124 (BC_1, *, internal, 1)," &
-- " 125 (BC_1, INIT, output3, X, 124, 1, PULL1)," &
" 125 (BC_1, *, internal, 0)," &
-- " 126 (BC_1, INIT, input, X)," &
" 126 (BC_1, *, internal, X)," &
" 127 (BC_1, *, controlr, 1)," &
" 128 (BC_1, IO47, output3, X, 127, 1, PULL1)," &
" 129 (BC_1, IO47, input, X)," &
" 130 (BC_1, *, controlr, 1)," &
" 131 (BC_1, IO48, output3, X, 130, 1, PULL1)," &
" 132 (BC_1, IO48, input, X)," &
" 133 (BC_1, *, controlr, 1)," &
" 134 (BC_1, IO49, output3, X, 133, 1, PULL1)," &
" 135 (BC_1, IO49, input, X)," &
" 136 (BC_1, *, controlr, 1)," &
" 137 (BC_1, IO50, output3, X, 136, 1, PULL1)," &
" 138 (BC_1, IO50, input, X)," &
" 139 (BC_1, *, controlr, 1)," &
" 140 (BC_1, IO51, output3, X, 139, 1, PULL1)," &
" 141 (BC_1, IO51, input, X)," &
" 142 (BC_1, *, controlr, 1)," &
" 143 (BC_1, IO52, output3, X, 142, 1, PULL1)," &
" 144 (BC_1, IO52, input, X)," &
" 145 (BC_1, *, controlr, 1)," &
" 146 (BC_1, IO53, output3, X, 145, 1, PULL1)," &
" 147 (BC_1, IO53, input, X)," &
" 148 (BC_1, *, controlr, 1)," &
" 149 (BC_1, IO54, output3, X, 148, 1, PULL1)," &
" 150 (BC_1, IO54, input, X)," &
" 151 (BC_1, *, controlr, 1)," &
" 152 (BC_1, IO60, output3, X, 151, 1, PULL1)," &
" 153 (BC_1, IO60, input, X)," &
" 154 (BC_1, *, controlr, 1)," &
" 155 (BC_1, IO61, output3, X, 154, 1, PULL1)," &
" 156 (BC_1, IO61, input, X)," &
" 157 (BC_1, *, controlr, 1)," &
" 158 (BC_1, IO62, output3, X, 157, 1, PULL1)," &
" 159 (BC_1, IO62, input, X)," &
" 160 (BC_1, *, controlr, 1)," &
" 161 (BC_1, IO63, output3, X, 160, 1, PULL1)," &
" 162 (BC_1, IO63, input, X)," &
" 163 (BC_1, *, controlr, 1)," &
" 164 (BC_1, IO64, output3, X, 163, 1, PULL1)," &
" 165 (BC_1, IO64, input, X)," &
" 166 (BC_1, *, controlr, 1)," &
" 167 (BC_1, IO65, output3, X, 166, 1, PULL1)," &
" 168 (BC_1, IO65, input, X)," &
" 169 (BC_1, *, controlr, 1)," &
" 170 (BC_1, IO66, output3, X, 169, 1, PULL1)," &
" 171 (BC_1, IO66, input, X)," &
" 172 (BC_1, *, controlr, 1)," &
" 173 (BC_1, IO67, output3, X, 172, 1, PULL1)," &
" 174 (BC_1, IO67, input, X)," &
" 175 (BC_1, *, controlr, 1)," &
" 176 (BC_1, IO70, output3, X, 175, 1, PULL1)," &
" 177 (BC_1, IO70, input, X)," &
" 178 (BC_1, *, controlr, 1)," &
" 179 (BC_1, IO71, output3, X, 178, 1, PULL1)," &
" 180 (BC_1, IO71, input, X)," &
" 181 (BC_1, *, controlr, 1)," &
" 182 (BC_1, IO72, output3, X, 181, 1, PULL1)," &
" 183 (BC_1, IO72, input, X)," &
" 184 (BC_1, *, controlr, 1)," &
" 185 (BC_1, IO73, output3, X, 184, 1, PULL1)," &
" 186 (BC_1, IO73, input, X)," &
" 187 (BC_1, *, controlr, 1)," &
" 188 (BC_1, IO74, output3, X, 187, 1, PULL1)," &
" 189 (BC_1, IO74, input, X)," &
" 190 (BC_1, *, controlr, 1)," &
" 191 (BC_1, IO75, output3, X, 190, 1, PULL1)," &
" 192 (BC_1, IO75, input, X)," &
" 193 (BC_1, *, controlr, 1)," &
" 194 (BC_1, IO76, output3, X, 193, 1, PULL1)," &
" 195 (BC_1, IO76, input, X)," &
" 196 (BC_1, *, controlr, 1)," &
" 197 (BC_1, IO77, output3, X, 196, 1, PULL1)," &
" 198 (BC_1, IO77, input, X)," &
" 199 (BC_1, *, internal, X)";
--end boundary register
attribute DESIGN_WARNING of XC4002XL_VQ100 : entity is
"This is a preliminary BSDL file which has not been verified." &
"CCLK and DONE are not represented in BOUNDARY_REGISTER." &
"This BSDL file must be modified by the FPGA designer in order to" &
"reflect post-configuration behavior (if any)." &
"If INIT has been high or floating since power-on or the last" &
"rising edge of PROGRAM, then the device may be in" &
"configuration mode in which case this file is not valid." &
"The output and tristate capture values are not valid until after" &
"the device is configured." &
"The fast output mux (where used) is not captured properly." &
"The tristate control is not captured properly when GTS is activated." &
"Some pins have both controlled and uncontrolled input paths.";
end XC4002XL_VQ100;