-- File Name :DS21448.BSD
-- Created by :Dallas Semiconductor (Synopsys Version 2000.11 (Nov 27, 2000))
-- Documentation :DS21448 data sheets
--
--
--
-- BSDL Revision :1.0
--
-- Date created :10/25/2003
-- Date modified :10/25/2003
-- Device :DS21448
-- Package :144-pin BGA
--
-- IMPORTANT NOTICE
-- Dallas Semiconductor customers are advised to obtain the latest version of
-- device specifications before relying on any published information contained
-- herein. Dallas Semiconductor assumes no responsibility or liability arising
-- out of the application of any information described herein.
--
--
--
-- IMPORTANT NOTICE ABOUT THE REVISION
--
-- Dallas Semiconductor customers are advised to check the revision of the
-- device they will be using. All the codes for the device revisions are
-- herein this BSDL file.
--
-- The characters "/", "(", ")" and "*" have been removed from signal names for
-- compatibility with BSDL file format.
--
--
entity DS21448_top is
-- This section identifies the default device package selected.
generic (PHYSICAL_PIN_MAP: string:= "CSBGA_144");
-- This section declares all the ports in the design.
port (
TTIP3 :buffer bit;
TRING3 :buffer bit;
AD7 :inout bit;
AD6 :inout bit;
AD5 :inout bit;
AD4 :inout bit;
AD3 :inout bit;
AD2 :inout bit;
AD1 :inout bit;
AD0 :inout bit;
TCLK3 :in bit;
CS3 :in bit;
RDDS :in bit;
WRRW :in bit;
RTIP4 :in bit;
RRING4 :in bit;
ALEAS :in bit;
RCLK4 :out bit;
INT :inout bit;
TEST :in bit;
TTIP4 :buffer bit;
TRING4 :buffer bit;
HRST :in bit;
BIS0 :in bit;
PBTS :in bit;
MCLK :in bit;
PBEO1 :out bit;
PBEO2 :out bit;
BPCLK4 :out bit;
TCLK4 :in bit;
CS4 :in bit;
PBEO3 :out bit;
BPCLK1 :out bit;
PBEO4 :out bit;
RTIP1 :in bit;
RRING1 :in bit;
RCL1LOTC1 :out bit;
RCLK1 :out bit;
RCL2LOTC2 :out bit;
RCL3LOTC3 :out bit;
RCL4LOTC4 :out bit;
TTIP1 :buffer bit;
TRING1 :buffer bit;
RPOS1 :out bit;
RNEG1 :out bit;
RPOS2 :out bit;
RNEG2 :out bit;
RPOS3 :out bit;
RNEG3 :out bit;
RPOS4 :out bit;
TCLK1 :in bit;
CS1 :in bit;
RNEG4 :out bit;
TPOS1 :in bit;
TNEG1 :in bit;
RTIP2 :in bit;
RRING2 :in bit;
TPOS2 :in bit;
RCLK2 :out bit;
TNEG2 :in bit;
TPOS3 :in bit;
TNEG3 :in bit;
SCLK :in bit;
SDI :in bit;
TTIP2 :buffer bit;
TRING2 :buffer bit;
JTRST :in bit;
TCLK2 :in bit;
JTCLK :in bit;
JTDI :in bit;
JTDO :out bit;
BPCLK2 :out bit;
JTMS :in bit;
TPOS4 :in bit;
BPCLK3 :out bit;
CS2 :in bit;
RCLK3 :out bit;
TNEG4 :in bit;
RTIP3 :in bit;
RRING3 :in bit;
A4 :inout bit;
A3 :in bit;
A2 :in bit;
A1 :in bit;
A0 :in bit;
BIS1 :in bit;
TVDD1 :linkage bit;
TVSS1 :linkage bit;
TVDD2 :linkage bit;
TVSS2 :linkage bit;
TVDD3 :linkage bit;
TVSS3 :linkage bit;
TVDD4 :linkage bit;
TVSS4 :linkage bit;
VDD :linkage bit_vector(1 to 4);
VSS :linkage bit_vector(1 to 4);
NoConnect :linkage bit_vector(1 to 42)
);
use STD_1149_1_1994.all;
attribute COMPONENT_CONFORMANCE of DS21448_top: entity is "STD_1149_1_1993";
attribute PIN_MAP of DS21448_top: entity is PHYSICAL_PIN_MAP;
-- This section specifies the pin map for each port. This information
-- is extracted from the port-to-pin map file that was read in using
-- the "read_pin_map" command.
constant CSBGA_144: PIN_MAP_STRING :=
" TTIP3 : A8 ,"&
" TRING3 : B9 ,"&
" AD7 : J10 ,"&
" AD6 : H10 ,"&
" AD5 : G11 ,"&
" AD4 : J9 ,"&
" AD3 : E3 ,"&
" AD2 : D4 ,"&
" AD1 : F3 ,"&
" AD0 : D5 ,"&
" TCLK3 : F12 ,"&
" CS3 : D10 ,"&
" RDDS : J2 ,"&
" WRRW : H1 ,"&
" RTIP4 : A10 ,"&
" RRING4 : B11 ,"&
" ALEAS : K2 ,"&
" RCLK4 : L11 ,"&
" INT : K9 ,"&
" TEST : K7 ,"&
" TTIP4 : A11 ,"&
" TRING4 : B12 ,"&
" HRST : L9 ,"&
" BIS0 : L7 ,"&
" PBTS : M12 ,"&
" MCLK : J6 ,"&
" PBEO1 : K5 ,"&
" PBEO2 : G3 ,"&
" BPCLK4 : L8 ,"&
" TCLK4 : L12 ,"&
" CS4 : K10 ,"&
" PBEO3 : E10 ,"&
" BPCLK1 : H4 ,"&
" PBEO4 : K8 ,"&
" RTIP1 : A1 ,"&
" RRING1 : B2 ,"&
" RCL1LOTC1 : L6 ,"&
" RCLK1 : H3 ,"&
" RCL2LOTC2 : D7 ,"&
" RCL3LOTC3 : F9 ,"&
" RCL4LOTC4 : J7 ,"&
" TTIP1 : A2 ,"&
" TRING1 : B3 ,"&
" RPOS1 : K4 ,"&
" RNEG1 : G2 ,"&
" RPOS2 : E1 ,"&
" RNEG2 : E2 ,"&
" RPOS3 : D11 ,"&
" RNEG3 : F11 ,"&
" RPOS4 : K11 ,"&
" TCLK1 : M2 ,"&
" CS1 : J3 ,"&
" RNEG4 : M10 ,"&
" TPOS1 : G1 ,"&
" TNEG1 : H2 ,"&
" RTIP2 : A4 ,"&
" RRING2 : B5 ,"&
" TPOS2 : F2 ,"&
" RCLK2 : F1 ,"&
" TNEG2 : M1 ,"&
" TPOS3 : E12 ,"&
" TNEG3 : D12 ,"&
" SCLK : J1 ,"&
" SDI : K3 ,"&
" TTIP2 : A5 ,"&
" TRING2 : B6 ,"&
" JTRST : L3 ,"&
" TCLK2 : L2 ,"&
" JTCLK : M5 ,"&
" JTDI : M6 ,"&
" JTDO : M7 ,"&
" BPCLK2 : D6 ,"&
" JTMS : M3 ,"&
" TPOS4 : M11 ,"&
" BPCLK3 : F10 ,"&
" CS2 : D3 ,"&
" RCLK3 : E11 ,"&
" TNEG4 : K12 ,"&
" RTIP3 : A7 ,"&
" RRING3 : B8 ,"&
" A4 : K1 ,"&
" A3 : L1 ,"&
" A2 : H11 ,"&
" A1 : H12 ,"&
" A0 : G12 ,"&
" BIS1 : M8 ,"&
" TVDD1 : J5 ,"&
" TVSS1 : J4 ,"&
" TVDD2 : D2 ,"&
" TVSS2 : D1 ,"&
" TVDD3 : G9 ,"&
" TVSS3 : E9 ,"&
" TVDD4 : M9 ,"&
" TVSS4 : L10 ,"&
" VDD : (L5, E4, D8, J8) ,"&
" VSS : (M4, F4, D9, H9) ,"&
" NoConnect : (A3, A6, A9, A12, B1, B4, B7, B10, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, E5, E6, E7, E8, F5, F6, F7, F8, G4, G5, G6, G7, G8, G10, H5, H6, H7, H8, J11, J12, K6, L4)";
-- MAKE SURE THAT ALL THESE NO CONNECTS ARE ON ONE LINE. OTHERWISE
-- THIS BSDL FILE WILL SHOW SOME ERROR.
-- This section specifies the TAP ports.
-- For the TAP TCK port, the parameters in the brackets are:
-- First Field : Maximum TCK frequency.
-- Second Field: Allowable states TCK may be stopped in.
attribute TAP_SCAN_CLOCK of JTCLK : signal is (10.0e6, BOTH);
attribute TAP_SCAN_IN of JTDI : signal is true;
attribute TAP_SCAN_MODE of JTMS : signal is true;
attribute TAP_SCAN_OUT of JTDO : signal is true;
attribute TAP_SCAN_RESET of JTRST : signal is true;
-- Specifies the number of bits in the instruction register.
attribute INSTRUCTION_LENGTH of DS21448_top: entity is 3;
-- Specifies the boundary-scan instructions implemented in the
-- design and their opcodes.
attribute INSTRUCTION_OPCODE of DS21448_top: entity is
"BYPASS (111)," &
"EXTEST (000)," &
"SAMPLE (010)," &
"CLAMP (011)," &
"HIGHZ (100)," &
-- "USER1 (101)," &
-- "USER2 (110)," &
"IDCODE (001)";
-- Specifies the bit pattern that is loaded into the instruction
-- register when the TAP controller passes through the Capture-IR
-- state. The standard mandates that the two LSBs must be "01".
-- The remaining bits are design specific.
attribute INSTRUCTION_CAPTURE of DS21448_top: entity is "001";
-- Specifies the bit pattern that is loaded into the DEVICE_ID
-- register during the IDCODE instruction when the TAP controller
-- passes through the Capture-DR state.
-- 10018143 (HEX)
attribute IDCODE_REGISTER of DS21448_top: entity is
-- "0000" & -- 4-bit version number for A1
"0001" & -- 4-bit version number for A2
"0000000000011000" & -- 16-bit part number
"00010100001" & -- 11-bit identity of the manufacturer
"1"; -- Required by IEEE Std 1149.1
-- This section specifies the test data register placed between TDI
-- and TDO for each implemented instruction.
-- attribute REGISTER_ACCESS of DS21448_top: entity is
-- "BYPASS (BYPASS, CLAMP, HIGHZ, USER1, USER2)," &
-- "BOUNDARY (EXTEST, SAMPLE)," &
-- "DEVICE_ID (IDCODE)";
-- Specifies the length of the boundary scan register.
attribute BOUNDARY_LENGTH of DS21448_top: entity is 68;
attribute BOUNDARY_REGISTER of DS21448_top: entity is
--
-- num cell port function safe [ccell disval rslt]
--
" 0 (BC_1, TCLK2 , input, X) ,"&
" 1 (BC_1, SDI , input, X) ,"&
" 2 (BC_1, SCLK , input, X) ,"&
" 3 (BC_1, TNEG3 , input, X) ,"&
" 4 (BC_1, TPOS3 , input, X) ,"&
" 5 (BC_1, TNEG2 , input, X) ,"&
" 6 (BC_1, RCLK2 , output2, X) ,"&
" 7 (BC_1, TPOS2 , input, X) ,"&
" 8 (BC_1, TNEG1 , input, X) ,"&
" 9 (BC_1, TPOS1 , input, X) ,"&
" 10 (BC_1, RNEG4 , output2, X) ,"&
" 11 (BC_1, CS1 , input, X) ,"&
" 12 (BC_1, TCLK1 , input, X) ,"&
" 13 (BC_1, RPOS4 , output2, X) ,"&
" 14 (BC_1, RNEG3 , output2, X) ,"&
" 15 (BC_1, RPOS3 , output2, X) ,"&
" 16 (BC_1, RNEG2 , output2, X) ,"&
" 17 (BC_1, RPOS2 , output2, X) ,"&
" 18 (BC_1, RNEG1 , output2, X) ,"&
" 19 (BC_1, RPOS1 , output2, X) ,"&
" 20 (BC_1, RCL4LOTC4 , output2, X) ,"&
" 21 (BC_1, RCL3LOTC3 , output2, X) ,"&
" 22 (BC_1, RCL2LOTC2 , output2, X) ,"&
" 23 (BC_1, RCLK1 , output2, X) ,"&
" 24 (BC_1, RCL1LOTC1 , output2, X) ,"&
" 25 (BC_1, PBEO4 , output2, X) ,"&
" 26 (BC_1, BPCLK1 , output2, X) ,"&
" 27 (BC_1, PBEO3 , output2, X) ,"&
" 28 (BC_1, CS4 , input, X) ,"&
" 29 (BC_1, TCLK4 , input, X) ,"&
" 30 (BC_1, BPCLK4 , output2, X) ,"&
" 31 (BC_1, PBEO2 , output2, X) ,"&
" 32 (BC_1, PBEO1 , output2, X) ,"&
" 33 (BC_1, MCLK , input, X) ,"&
" 34 (BC_1, PBTS , input, X) ,"&
" 35 (BC_1, BIS0 , input, X) ,"&
" 36 (BC_1, HRST , input, X) ,"&
" 37 (BC_1, TEST , input, X) ,"&
" 38 (BC_7, INT , bidir, 0, 39, 0, Z) ,"&
" 39 (BC_2, *, control, 0) ,"&
" 40 (BC_1, RCLK4 , output2, X) ,"&
" 41 (BC_1, ALEAS , input, X) ,"&
" 42 (BC_1, WRRW , input, X) ,"&
" 43 (BC_1, RDDS , input, X) ,"&
" 44 (BC_1, CS3 , input, X) ,"&
" 45 (BC_1, TCLK3 , input, X) ,"&
" 46 (BC_7, AD0 , bidir, 0, 54, 0, Z) ,"&
" 47 (BC_7, AD1 , bidir, 0, 54, 0, Z) ,"&
" 48 (BC_7, AD2 , bidir, 0, 54, 0, Z) ,"&
" 49 (BC_7, AD3 , bidir, 0, 54, 0, Z) ,"&
" 50 (BC_7, AD4 , bidir, 0, 54, 0, Z) ,"&
" 51 (BC_7, AD5 , bidir, 0, 54, 0, Z) ,"&
" 52 (BC_7, AD6 , bidir, 0, 54, 0, Z) ,"&
" 53 (BC_7, AD7 , bidir, 0, 54, 0, Z) ,"&
" 54 (BC_2, *, control, 0) ,"&
" 55 (BC_1, BIS1 , input, X) ,"&
" 56 (BC_1, A0 , input, X) ,"&
" 57 (BC_1, A1 , input, X) ,"&
" 58 (BC_1, A2 , input, X) ,"&
" 59 (BC_1, A3 , input, X) ,"&
" 60 (BC_7, A4 , bidir, 0, 61, 0, Z) ,"&
" 61 (BC_2, *, control, 0) ,"&
" 62 (BC_1, TNEG4 , input, X) ,"&
" 63 (BC_1, RCLK3 , output2, X) ,"&
" 64 (BC_1, CS2 , input, X) ,"&
" 65 (BC_1, BPCLK3 , output2, X) ,"&
" 66 (BC_1, TPOS4 , input, X) ,"&
" 67 (BC_1, BPCLK2 , output2, X) ";
end DS21448_top;