BSDL Files Library for JTAG

The only free public library that contains thousands of BSDL (Boundary Scan Description Language) models to use with BScan/JTAG tools

BSDL model: idt82v3910

-- *****************************************************************************

--   BSDL file for design idt82v3910

--   Created by Synopsys Version D-2010.03-SP5 (Oct 18, 2010)

--   Designer: 
--   Company:  

--   Date: Wed Nov 14 14:15:27 2012

--   Updated linkage bits for APLL pins (May 15, 2013)

-- *****************************************************************************


 entity idt82v3910 is
   
-- This section identifies the default device package selected.
   
   generic (PHYSICAL_PIN_MAP: string:= "IDT82V3910");
   
-- This section declares all the ports in the design.
   
   port ( 
          ex_sync1        : in       bit;
          ex_sync2        : in       bit;
          ff_srcsw        : in       bit;
          i2c_ad1         : in       bit;
          i2c_ad2         : in       bit;
          i2c_scl         : in       bit;
          ic1             : in       bit;
          in10            : in       bit;
          in11            : in       bit;
          in12            : in       bit;
          in13            : in       bit;
          in14            : in       bit;
          in3             : in       bit;
          in4             : in       bit;
          in7             : in       bit;
          in8             : in       bit;
          in9             : in       bit;
          ms_sl           : in       bit;
          osci            : in       bit;
          rst             : in       bit;
          sonet_sdh       : in       bit;
          tck             : in       bit;
          tdi             : in       bit;
          tms             : in       bit;
          trst            : in       bit;
          i2c_sda         : inout    bit;
          int_req         : out      bit;
          tdo             : out      bit;
          frsync_8k_1pps  : buffer   bit;
          ic2             : buffer   bit;
          ic3             : buffer   bit;
          mfrsync_2k_1pps : buffer   bit;
          out1            : buffer   bit;
          out2            : buffer   bit;
          out3            : buffer   bit;
          out4            : buffer   bit;
          out5            : buffer   bit;
          out9            : buffer   bit;
          t0_lock         : buffer   bit;
          t4_lock         : buffer   bit;
          caps            : linkage  bit_vector (1 to 6);
          ic              : linkage  bit_vector (4 to 11);
          in_apll1_neg    : linkage  bit;
          in_apll1_pos    : linkage  bit;
          in_apll2_neg    : linkage  bit;
          in_apll2_pos    : linkage  bit;
          in1             : linkage  bit;
          in2             : linkage  bit;
          in5_neg         : linkage  bit;
          in5_pos         : linkage  bit;
          in6_neg         : linkage  bit;
          in6_pos         : linkage  bit;
          nc              : linkage  bit_vector (1 to 2);
          out10_neg       : linkage  bit;
          out10_pos       : linkage  bit;
          out11_neg       : linkage  bit;
          out11_pos       : linkage  bit;
          out6_neg        : linkage  bit;
          out6_pos        : linkage  bit;
          out7_neg        : linkage  bit;
          out7_pos        : linkage  bit;
          out8_neg        : linkage  bit;
          out8_pos        : linkage  bit;
          vdda            : linkage  bit_vector (1 to 14);
          vddao           : linkage  bit_vector (1 to 13);
          vddd            : linkage  bit_vector (1 to 11);
          vdddo           : linkage  bit_vector (1 to 3);
          vssa            : linkage  bit_vector (1 to 18);
          vssao           : linkage  bit_vector (1 to 39);
          vssd            : linkage  bit_vector (1 to 11);
          vssdo           : linkage  bit_vector (1 to 3);
          xtal1_in        : linkage  bit;
          xtal1_out       : linkage  bit;
          xtal2_in        : linkage  bit;
          xtal2_out       : linkage  bit;
          xtal3_in        : linkage  bit;
          xtal3_out       : linkage  bit;
          xtal4_in        : linkage  bit;
          xtal4_out       : linkage  bit
   );
   
   use STD_1149_1_2001.all;
   
   attribute COMPONENT_CONFORMANCE of idt82v3910: entity is "STD_1149_1_2001";
   
   attribute PIN_MAP of idt82v3910: entity is PHYSICAL_PIN_MAP;
   
-- This section specifies the pin map for each port. This information is 
-- extracted from the port-to-pin map file that was read in using the 
-- "read_pin_map" command.
   
     constant IDT82V3910: PIN_MAP_STRING := 
        "ex_sync1        : F11," &
        "ex_sync2        : G11," &
        "ff_srcsw        : A10," &
        "i2c_ad1         : L8," &
        "i2c_ad2         : L9," &
        "i2c_scl         : K13," &
        "ic1             : E9," &
        "in10            : H11," &
        "in11            : G13," &
        "in12            : G12," &
        "in13            : G14," &
        "in14            : H12," &
        "in3             : H14," &
        "in4             : J13," &
        "in7             : J14," &
        "in8             : K12," &
        "in9             : J12," &
        "ms_sl           : D6," &
        "osci            : A11," &
        "rst             : H13," &
        "sonet_sdh       : E6," &
        "tck             : B10," &
        "tdi             : A8," &
        "tms             : A12," &
        "trst            : A14," &
        "i2c_sda         : K14," &
        "int_req         : C13," &
        "tdo             : B8," &
        "frsync_8k_1pps  : C6," &
        "ic2             : D9," &
        "ic3             : G8," &
        "mfrsync_2k_1pps : C5," &
        "out1            : F13," &
        "out2            : E13," &
        "out3            : E14," &
        "out4            : D13," &
        "out5            : D14," &
        "out9            : C14," &
        "t0_lock         : J11," &
        "t4_lock         : K11," &
        "caps            : (A4, C4, D3, L10, L12, L14)," &
        "ic              : (C1, P13, A13, A9, P12, N12, A1, B1)," &
        "in_apll1_neg    : A5," &
        "in_apll1_pos    : B5," &
        "in_apll2_neg    : P6," &
        "in_apll2_pos    : N6," &
        "in1             : A7," &
        "in2             : B7," &
        "in5_neg         : P7," &
        "in5_pos         : N7," &
        "in6_neg         : P8," &
        "in6_pos         : N8," &
        "nc              : (C3, M12)," &
        "out10_neg       : P2," &
        "out10_pos       : N2," &
        "out11_neg       : P4," &
        "out11_pos       : N4," &
        "out6_neg        : J1," &
        "out6_pos        : J2," &
        "out7_neg        : L1," &
        "out7_pos        : L2," &
        "out8_neg        : A6," &
        "out8_pos        : B6," &
        "vdda            : (A2, C2, C9, C11, C12, D5, D10, D12, E11, F5, J10," &
        "                   P9, P11, P14)," &
        "vddao           : (H1, H3, J3, J5, J7, K4, K6, L3, M1, M5, M7, P1," &
        "                   P5)," &
        "vddd            : (D8, E8, F1, F8, F10, G2, G7, G9, H8, H10, K9)," &
        "vdddo           : (B14, C7, F12)," &
        "vssa            : (B2, B11, B12, C10, D1, D4, D11, E3, E5, E10, E12," &
        "                   F4, J9, L11, L13, N9, N11, N14)," &
        "vssao           : (B4, B9, D2, E4, F3, F6, G3, G4, G5, H2, H4, H5," &
        "                   H6, J4, J6, J8, K1, K2, K3, K5, K7, K10, L4, L5," &
        "                   L6, L7, M2, M3, M4, M6, M8, M9, M10, M11, N1, N3," &
        "                   N5, N13, P3)," &
        "vssd            : (D7, E7, F2, F7, F9, G1, G6, G10, H7, H9, K8)," &
        "vssdo           : (B13, C8, F14)," &
        "xtal1_in        : A3," &
        "xtal1_out       : B3," &
        "xtal2_in        : P10," &
        "xtal2_out       : N10," &
        "xtal3_in        : E1," &
        "xtal3_out       : E2," &
        "xtal4_in        : M14," &
        "xtal4_out       : M13";
   
-- This section specifies the TAP ports. For the TAP TCK port, the parameters in 
-- the brackets are:
--        First Field : Maximum  TCK frequency.
--        Second Field: Allowable states TCK may be stopped in.
   
   attribute TAP_SCAN_CLOCK of tck : signal is (10.0e6, BOTH);
   attribute TAP_SCAN_IN    of tdi : signal is true;
   attribute TAP_SCAN_MODE  of tms : signal is true;
   attribute TAP_SCAN_OUT   of tdo : signal is true;
   attribute TAP_SCAN_RESET of trst: signal is true;
   
-- Specifies the number of bits in the instruction register.
   
   attribute INSTRUCTION_LENGTH of idt82v3910: entity is 3;
   
-- Specifies the boundary-scan instructions implemented in the design and their 
-- opcodes.
   
   attribute INSTRUCTION_OPCODE of idt82v3910: entity is 
     "BYPASS  (111)," &
     "EXTEST  (000)," &
     "SAMPLE  (010)," &
     "PRELOAD (010)," &
     "IDCODE  (001)";
   
-- Specifies the bit pattern that is loaded into the instruction register when 
-- the TAP controller passes through the Capture-IR state. The standard mandates 
-- that the two LSBs must be "01". The remaining bits are design specific.
   
   attribute INSTRUCTION_CAPTURE of idt82v3910: entity is "001";
   
-- Specifies the bit pattern that is loaded into the DEVICE_ID register during 
-- the IDCODE instruction when the TAP controller passes through the Capture-DR 
-- state.
   
   attribute IDCODE_REGISTER of idt82v3910: entity is 
     "0000" &                  
 -- 4-bit version number
     "0000010001001000" &      
 -- 16-bit part number
     "00010110011" &           
 -- 11-bit identity of the manufacturer
     "1";                      
 -- Required by IEEE Std 1149.1
   
-- This section specifies the test data register placed between TDI and TDO for 
-- each implemented instruction.
   
   attribute REGISTER_ACCESS of idt82v3910: entity is 
        "BYPASS    (BYPASS)," &
        "BOUNDARY  (EXTEST, SAMPLE, PRELOAD)," &
        "DEVICE_ID (IDCODE)";
   
-- Specifies the length of the boundary scan register.
   
   attribute BOUNDARY_LENGTH of idt82v3910: entity is 75;
   
-- The following list specifies the characteristics of each cell in the boundary 
-- scan register from TDI to TDO. The following is a description of the label 
-- fields:
--      num     : Is the cell number.
--      cell    : Is the cell type as defined by the standard.
--      port    : Is the design port name. Control cells do not have a port 
--                name.
--      function: Is the function of the cell as defined by the standard. Is one 
--                of input, output2, output3, bidir, control or controlr.
--      safe    : Specifies the value that the BSR cell should be loaded with 
--                for safe operation when the software might otherwise choose a 
--                random value.
--      ccell   : The control cell number. Specifies the control cell that 
--                drives the output enable for this port.
--      disval  : Specifies the value that is loaded into the control cell to 
--                disable the output enable for the corresponding port.
--      rslt    : Resulting state. Shows the state of the driver when it is 
--                disabled.
   
   attribute BOUNDARY_REGISTER of idt82v3910: entity is 
--     
--    num   cell   port             function      safe  [ccell  disval  rslt]
--     
     "74   (BC_0,  *,               internal,     " &
     "X),                        " &
     "73   (BC_3,  sonet_sdh,       input,        " &
     "X),                        " &
     "72   (BC_3,  ms_sl,           input,        " &
     "X),                        " &
     "71   (BC_1,  ic3,             output2,      " &
     "X),                        " &
     "70   (BC_1,  ic2,             output2,      " &
     "X),                        " &
     "69   (BC_3,  ic1,             input,        " &
     "X),                        " &
     "68   (BC_1,  out9,            output2,      " &
     "X),                        " &
     "67   (BC_1,  out5,            output2,      " &
     "X),                        " &
     "66   (BC_1,  out4,            output2,      " &
     "X),                        " &
     "65   (BC_1,  out3,            output2,      " &
     "X),                        " &
     "64   (BC_1,  out2,            output2,      " &
     "X),                        " &
     "63   (BC_1,  out1,            output2,      " &
     "X),                        " &
     "62   (BC_7,  i2c_sda,         bidir,        X,    61,     1,      " &
     "PULL0)," &
     "61   (BC_1,  *,               control,      " &
     "1),                        " &
     "60   (BC_0,  *,               internal,     " &
     "X),                        " &
     "59   (BC_0,  *,               internal,     " &
     "X),                        " &
     "58   (BC_0,  *,               internal,     " &
     "X),                        " &
     "57   (BC_0,  *,               internal,     " &
     "X),                        " &
     "56   (BC_0,  *,               internal,     " &
     "X),                        " &
     "55   (BC_0,  *,               internal,     " &
     "X),                        " &
     "54   (BC_0,  *,               internal,     " &
     "X),                        " &
     "53   (BC_0,  *,               internal,     " &
     "X),                        " &
     "52   (BC_0,  *,               internal,     " &
     "X),                        " &
     "51   (BC_0,  *,               internal,     " &
     "X),                        " &
     "50   (BC_3,  rst,             input,        " &
     "X),                        " &
     "49   (BC_3,  i2c_scl,         input,        " &
     "X),                        " &
     "48   (BC_3,  i2c_ad2,         input,        " &
     "X),                        " &
     "47   (BC_3,  i2c_ad1,         input,        " &
     "X),                        " &
     "46   (BC_0,  *,               internal,     " &
     "X),                        " &
     "45   (BC_0,  *,               internal,     " &
     "X),                        " &
     "44   (BC_0,  *,               internal,     " &
     "X),                        " &
     "43   (BC_0,  *,               internal,     " &
     "X),                        " &
     "42   (BC_0,  *,               internal,     " &
     "X),                        " &
     "41   (BC_0,  *,               internal,     " &
     "X),                        " &
     "40   (BC_0,  *,               internal,     " &
     "X),                        " &
     "39   (BC_0,  *,               internal,     " &
     "X),                        " &
     "38   (BC_0,  *,               internal,     " &
     "X),                        " &
     "37   (BC_0,  *,               internal,     " &
     "X),                        " &
     "36   (BC_0,  *,               internal,     " &
     "X),                        " &
     "35   (BC_0,  *,               internal,     " &
     "X),                        " &
     "34   (BC_0,  *,               internal,     " &
     "X),                        " &
     "33   (BC_1,  t0_lock,         output2,      " &
     "X),                        " &
     "32   (BC_1,  t4_lock,         output2,      " &
     "X),                        " &
     "31   (BC_3,  in14,            input,        " &
     "X),                        " &
     "30   (BC_3,  in13,            input,        " &
     "X),                        " &
     "29   (BC_3,  in12,            input,        " &
     "X),                        " &
     "28   (BC_3,  in11,            input,        " &
     "X),                        " &
     "27   (BC_0,  *,               internal,     " &
     "X),                        " &
     "26   (BC_3,  in10,            input,        " &
     "X),                        " &
     "25   (BC_3,  in9,             input,        " &
     "X),                        " &
     "24   (BC_3,  ex_sync2,        input,        " &
     "X),                        " &
     "23   (BC_3,  in8,             input,        " &
     "X),                        " &
     "22   (BC_0,  *,               internal,     " &
     "X),                        " &
     "21   (BC_3,  in7,             input,        " &
     "X),                        " &
     "20   (BC_3,  in4,             input,        " &
     "X),                        " &
     "19   (BC_3,  in3,             input,        " &
     "X),                        " &
     "18   (BC_3,  ex_sync1,        input,        " &
     "X),                        " &
     "17   (BC_0,  *,               internal,     " &
     "X),                        " &
     "16   (BC_0,  *,               internal,     " &
     "X),                        " &
     "15   (BC_0,  *,               internal,     " &
     "X),                        " &
     "14   (BC_0,  *,               internal,     " &
     "X),                        " &
     "13   (BC_0,  *,               internal,     " &
     "X),                        " &
     "12   (BC_1,  mfrsync_2k_1pps, output2,      " &
     "X),                        " &
     "11   (BC_1,  frsync_8k_1pps,  output2,      " &
     "X),                        " &
     "10   (BC_0,  *,               internal,     " &
     "X),                        " &
     "9    (BC_0,  *,               internal,     " &
     "X),                        " &
     "8    (BC_0,  *,               internal,     " &
     "X),                        " &
     "7    (BC_0,  *,               internal,     " &
     "X),                        " &
     "6    (BC_0,  *,               internal,     " &
     "X),                        " &
     "5    (BC_0,  *,               internal,     " &
     "X),                        " &
     "4    (BC_0,  *,               internal,     " &
     "X),                        " &
     "3    (BC_3,  ff_srcsw,        input,        " &
     "X),                        " &
     "2    (BC_3,  osci,            input,        " &
     "X),                        " &
     "1    (BC_1,  int_req,         output3,      X,    0,      1,      " &
     "Z),  " &
     "0    (BC_1,  *,               control,      " &
     "1)                         ";
 
 end idt82v3910;