-- BSDL listing from io_top_create.pl, Mon Oct 21 14:09:17 2013
--
-- pins not part of boundary scan are listed as type 'linkage'
entity LPC11U6x is
generic (PHYSICAL_PIN_MAP : string := "LQFP48U");
port (
RTCXIN : linkage bit; -- RTCX1
RTCXOUT : linkage bit; -- RTCX2
VSS1 : linkage bit; -- gnd1
RESETn_PIO0_0 : in bit; -- PIO0_0
PIO0_1_CLKOUT_CT32B0_MAT2_USB_FTOGGLE : inout bit; -- PIO0_1
VSS2 : linkage bit; -- VSSIO_EXT_11
PIO2_0_XTALIN : inout bit; -- PIO2_0
PIO2_1_XTALOUT : inout bit; -- PIO2_1
VDD1 : linkage bit; -- VDDIO_EXT_11
PIO2_5_U3_CTSn_SCT0_IN1 : inout bit; -- PIO2_5
PIO0_20_CT16B1_CAP0_U2_RXD : inout bit; -- PIO0_20
PIO0_2_SSP0_SSEL_CT16B0_CAP0_EZH_0 : inout bit; -- PIO0_2
PIO2_2_U3_RTSn_U3_SCLK_SCT0_OUT1 : inout bit; -- PIO2_2
PIO1_20_U0_DSRn_SSP1_SCK_CT16B0_MAT0 : inout bit; -- PIO1_20
PIO0_3_USB_VBUS_EZH_1 : inout bit; -- PIO0_3
PIO0_4_I2C0_SCL_EZH_2 : inout bit; -- PIO0_4
PIO0_5_I2C0_SDA_EZH_3 : inout bit; -- PIO0_5
PIO0_21_CT16B1_MAT0_SSP1_MOSI : inout bit; -- PIO0_21
PIO1_23_CT16B1_MAT1_SSP1_SSEL_U2_TXD : inout bit; -- PIO1_23
USB_DM : linkage bit; -- USB_DM
USB_DP : linkage bit; -- USB_DP
PIO2_7_SSP0_SCK_SCT0_OUT2 : inout bit; -- PIO2_7
PIO1_24_CT32B0_MAT0_I2C1_SDA : inout bit; -- PIO1_24
PIO0_6_USB_CONNECTn_SSP0_SCK_EZH_4 : inout bit; -- PIO0_6
PIO0_7_U0_CTSn_EZH_5_I2C1_SCL : inout bit; -- PIO0_7
PIO1_21_U0_DCDn_SSP1_MISO_CT16B0_CAP1 : inout bit; -- PIO1_21
PIO0_8_SSP0_MISO_CT16B0_MAT0_EZH_6 : inout bit; -- PIO0_8
PIO0_9_SSP0_MOSI_CT16B0_MAT1_EZH_7 : inout bit; -- PIO0_9
SWCLK_PIO0_10_SSP0_SCK_CT16B0_MAT2 : in bit; -- PIO0_10
PIO0_22_ADC_11_CT16B1_CAP1_SSP1_MISO : inout bit; -- PIO0_22
TDI_PIO0_11_ADC_9_CT32B0_MAT3_U1_RTSn_U1_SCLK : in bit; -- PIO0_11
TMS_PIO0_12_ADC_8_CT32B1_CAP0_U1_CTSn : in bit; -- PIO0_12
TDO_PIO0_13_ADC_7_CT32B1_MAT0_U1_RXD : out bit; -- PIO0_13
TRSTn_PIO0_14_ADC_6_CT32B1_MAT1_U1_TXD : in bit; -- PIO0_14
VREFP : linkage bit; -- VREFP1
VREFN : linkage bit; -- VREFN1
PIO1_13_U1_CTSn_SCT0_OUT3_EZH_22 : inout bit; -- PIO1_13
SWDIO_PIO0_15_ADC_3_CT32B1_MAT2 : inout bit; -- PIO0_15
PIO0_16_ADC_2_CT32B1_MAT3_EZH_8_WAKEUP : inout bit; -- PIO0_16
PIO0_23_ADC_1_EZH_9_UART0_nRI_SSP1_SSEL : inout bit; -- PIO0_23
VDDA : linkage bit; -- VDDA_EXT1
VSSA : linkage bit; -- VSSA_EXT1
PIO0_17_U0_RTSn_CT32B0_CAP0_U0_SCLK : inout bit; -- PIO0_17
VSS3 : linkage bit; -- gnd2
VDD2 : linkage bit; -- VDDMAIN_EXT1
PIO0_18_U0_RXD_CT32B0_MAT0 : inout bit; -- PIO0_18
PIO0_19_U0_TXD_CT32B0_MAT1 : inout bit; -- PIO0_19
VBAT : linkage bit -- VBAT1
);
use STD_1149_1_2001.all;
attribute COMPONENT_CONFORMANCE of LPC11U6x : entity is "std_1149_1_2001";
attribute PIN_MAP of LPC11U6x : entity is PHYSICAL_PIN_MAP;
constant LQFP48U : PIN_MAP_STRING :=
"RTCXIN : 48," &
"RTCXOUT : 1," &
"VSS1 : 2," &
"RESETn_PIO0_0 : 3," &
"PIO0_1_CLKOUT_CT32B0_MAT2_USB_FTOGGLE : 4," &
"VSS2 : 5," &
"PIO2_0_XTALIN : 6," &
"PIO2_1_XTALOUT : 7," &
"VDD1 : 8," &
"PIO2_5_U3_CTSn_SCT0_IN1 : 9," &
"PIO0_20_CT16B1_CAP0_U2_RXD : 10," &
"PIO0_2_SSP0_SSEL_CT16B0_CAP0_EZH_0 : 11," &
"PIO2_2_U3_RTSn_U3_SCLK_SCT0_OUT1 : 12," &
"PIO1_20_U0_DSRn_SSP1_SCK_CT16B0_MAT0 : 13," &
"PIO0_3_USB_VBUS_EZH_1 : 14," &
"PIO0_4_I2C0_SCL_EZH_2 : 15," &
"PIO0_5_I2C0_SDA_EZH_3 : 16," &
"PIO0_21_CT16B1_MAT0_SSP1_MOSI : 17," &
"PIO1_23_CT16B1_MAT1_SSP1_SSEL_U2_TXD : 18," &
"USB_DM : 19," &
"USB_DP : 20," &
"PIO2_7_SSP0_SCK_SCT0_OUT2 : 21," &
"PIO1_24_CT32B0_MAT0_I2C1_SDA : 22," &
"PIO0_6_USB_CONNECTn_SSP0_SCK_EZH_4 : 23," &
"PIO0_7_U0_CTSn_EZH_5_I2C1_SCL : 24," &
"PIO1_21_U0_DCDn_SSP1_MISO_CT16B0_CAP1 : 25," &
"PIO0_8_SSP0_MISO_CT16B0_MAT0_EZH_6 : 26," &
"PIO0_9_SSP0_MOSI_CT16B0_MAT1_EZH_7 : 27," &
"SWCLK_PIO0_10_SSP0_SCK_CT16B0_MAT2 : 28," &
"PIO0_22_ADC_11_CT16B1_CAP1_SSP1_MISO : 29," &
"TDI_PIO0_11_ADC_9_CT32B0_MAT3_U1_RTSn_U1_SCLK : 30," &
"TMS_PIO0_12_ADC_8_CT32B1_CAP0_U1_CTSn : 31," &
"TDO_PIO0_13_ADC_7_CT32B1_MAT0_U1_RXD : 32," &
"TRSTn_PIO0_14_ADC_6_CT32B1_MAT1_U1_TXD : 33," &
"VREFP : 34," &
"VREFN : 35," &
"PIO1_13_U1_CTSn_SCT0_OUT3_EZH_22 : 36," &
"SWDIO_PIO0_15_ADC_3_CT32B1_MAT2 : 37," &
"PIO0_16_ADC_2_CT32B1_MAT3_EZH_8_WAKEUP : 38," &
"PIO0_23_ADC_1_EZH_9_UART0_nRI_SSP1_SSEL : 39," &
"VDDA : 40," &
"VSSA : 41," &
"PIO0_17_U0_RTSn_CT32B0_CAP0_U0_SCLK : 42," &
"VSS3 : 43," &
"VDD2 : 44," &
"PIO0_18_U0_RXD_CT32B0_MAT0 : 45," &
"PIO0_19_U0_TXD_CT32B0_MAT1 : 46," &
"VBAT : 47";
-- *********************************************************************
-- * IEEE 1149.1 TAP PORTS *
-- *********************************************************************
-- This section specifies the TAP ports. For the TAP TCK port, the
-- parameters in the brackets are:
-- First Field : Maximum TCK frequency.
-- Second Field: Allowable states where TCK may be stopped.
attribute TAP_SCAN_CLOCK of SWCLK_PIO0_10_SSP0_SCK_CT16B0_MAT2 : signal is (10.00e+06,BOTH);
attribute TAP_SCAN_IN of TDI_PIO0_11_ADC_9_CT32B0_MAT3_U1_RTSn_U1_SCLK : signal is true;
attribute TAP_SCAN_MODE of TMS_PIO0_12_ADC_8_CT32B1_CAP0_U1_CTSn : signal is true;
attribute TAP_SCAN_OUT of TDO_PIO0_13_ADC_7_CT32B1_MAT0_U1_RXD : signal is true;
attribute TAP_SCAN_RESET of TRSTn_PIO0_14_ADC_6_CT32B1_MAT1_U1_TXD : signal is true;
-- Specifies the compliance enable patterns for the design. It lists a set of
-- design ports and the values that they should be set to, in order to enable
-- compliance to IEEE Std 1149.1
attribute COMPLIANCE_PATTERNS of LPC11U6x: entity is
"(RESETn_PIO0_0) (0)";
-- *********************************************************************
-- * INSTRUCTIONS AND REGISTER ACCESS *
-- *********************************************************************
attribute INSTRUCTION_LENGTH of LPC11U6x : entity is 5;
attribute INSTRUCTION_OPCODE of LPC11U6x : entity is
"extest (00000)," &
"sample (00001)," &
"preload (00001)," &
"highz (00010)," &
"clamp (00011)," &
"idcode (00100)," &
"resrvd (00101, 00110, 00111, 01000, 01001, 01010, 01011, 01100)," &
"bypass (11111)";
attribute INSTRUCTION_CAPTURE of LPC11U6x : entity is "00001";
attribute INSTRUCTION_PRIVATE of LPC11U6x : entity is "resrvd";
attribute IDCODE_REGISTER of LPC11U6x : entity is
"xxxx" & -- Version Number
"0000000000000000" & -- Part Number LPC11U67JBD48
"00000010101" & -- Manufacturer ID
"1"; -- Required by IEEE
attribute REGISTER_ACCESS of LPC11U6x : entity is
"BOUNDARY (extest, sample, preload), " &
"DEVICE_ID (idcode), " &
"BYPASS (highz, clamp, bypass)";
-- *********************************************************************
-- * BOUNDARY SCAN CELL INFORMATION *
-- *********************************************************************
attribute BOUNDARY_LENGTH of LPC11U6x : entity is 225;
attribute BOUNDARY_REGISTER of LPC11U6x : entity is
-- # cell name function safe control disable disable
-- type bit signal value result
"224 (BC_0, * , INTERNAL, X ),"&
"223 (BC_0, * , INTERNAL, X ),"&
"222 (BC_0, * , INTERNAL, X ),"&
"221 (BC_0, * , INTERNAL, X ),"&
"220 (BC_0, * , INTERNAL, X ),"&
"219 (BC_0, * , INTERNAL, X ),"&
"218 (BC_0, * , INTERNAL, X ),"&
"217 (BC_0, * , INTERNAL, X ),"&
"216 (BC_0, * , INTERNAL, X ),"&
"215 (BC_0, * , INTERNAL, X ),"&
"214 (BC_0, * , INTERNAL, X ),"&
"213 (BC_0, * , INTERNAL, X ),"&
"212 (BC_0, * , INTERNAL, X ),"&
"211 (BC_0, * , INTERNAL, X ),"&
"210 (BC_0, * , INTERNAL, X ),"&
"209 (BC_0, * , INTERNAL, X ),"&
"208 (BC_0, * , INTERNAL, X ),"&
"207 (BC_0, * , INTERNAL, X ),"&
"206 (BC_4, PIO1_13_U1_CTSn_SCT0_OUT3_EZH_22 , INPUT, X ),"&
"205 (BC_1, PIO1_13_U1_CTSn_SCT0_OUT3_EZH_22 , OUTPUT3, X, 204, 0, Z ),"&
"204 (BC_1, * , CONTROL, 0 ),"&
"203 (BC_0, * , INTERNAL, X ),"&
"202 (BC_0, * , INTERNAL, X ),"&
"201 (BC_0, * , INTERNAL, X ),"&
"200 (BC_0, * , INTERNAL, X ),"&
"199 (BC_0, * , INTERNAL, X ),"&
"198 (BC_0, * , INTERNAL, X ),"&
"197 (BC_4, SWDIO_PIO0_15_ADC_3_CT32B1_MAT2 , INPUT, X ),"&
"196 (BC_1, SWDIO_PIO0_15_ADC_3_CT32B1_MAT2 , OUTPUT3, X, 195, 0, Z ),"&
"195 (BC_1, * , CONTROL, 0 ),"&
"194 (BC_4, PIO0_16_ADC_2_CT32B1_MAT3_EZH_8_WAKEUP , INPUT, X ),"&
"193 (BC_1, PIO0_16_ADC_2_CT32B1_MAT3_EZH_8_WAKEUP , OUTPUT3, X, 192, 0, Z ),"&
"192 (BC_1, * , CONTROL, 0 ),"&
"191 (BC_4, PIO0_23_ADC_1_EZH_9_UART0_nRI_SSP1_SSEL , INPUT, X ),"&
"190 (BC_1, PIO0_23_ADC_1_EZH_9_UART0_nRI_SSP1_SSEL , OUTPUT3, X, 189, 0, Z ),"&
"189 (BC_1, * , CONTROL, 0 ),"&
"188 (BC_0, * , INTERNAL, X ),"&
"187 (BC_0, * , INTERNAL, X ),"&
"186 (BC_0, * , INTERNAL, X ),"&
"185 (BC_0, * , INTERNAL, X ),"&
"184 (BC_0, * , INTERNAL, X ),"&
"183 (BC_0, * , INTERNAL, X ),"&
"182 (BC_0, * , INTERNAL, X ),"&
"181 (BC_0, * , INTERNAL, X ),"&
"180 (BC_0, * , INTERNAL, X ),"&
"179 (BC_0, * , INTERNAL, X ),"&
"178 (BC_0, * , INTERNAL, X ),"&
"177 (BC_0, * , INTERNAL, X ),"&
"176 (BC_4, PIO0_17_U0_RTSn_CT32B0_CAP0_U0_SCLK , INPUT, X ),"&
"175 (BC_1, PIO0_17_U0_RTSn_CT32B0_CAP0_U0_SCLK , OUTPUT3, X, 174, 0, Z ),"&
"174 (BC_1, * , CONTROL, 0 ),"&
"173 (BC_4, PIO0_18_U0_RXD_CT32B0_MAT0 , INPUT, X ),"&
"172 (BC_1, PIO0_18_U0_RXD_CT32B0_MAT0 , OUTPUT3, X, 171, 0, Z ),"&
"171 (BC_1, * , CONTROL, 0 ),"&
"170 (BC_4, PIO0_19_U0_TXD_CT32B0_MAT1 , INPUT, X ),"&
"169 (BC_1, PIO0_19_U0_TXD_CT32B0_MAT1 , OUTPUT3, X, 168, 0, Z ),"&
"168 (BC_1, * , CONTROL, 0 ),"&
"167 (BC_0, * , INTERNAL, X ),"&
"166 (BC_0, * , INTERNAL, X ),"&
"165 (BC_0, * , INTERNAL, X ),"&
"164 (BC_0, * , INTERNAL, X ),"&
"163 (BC_0, * , INTERNAL, X ),"&
"162 (BC_0, * , INTERNAL, X ),"&
"161 (BC_0, * , INTERNAL, X ),"&
"160 (BC_0, * , INTERNAL, X ),"&
"159 (BC_0, * , INTERNAL, X ),"&
"158 (BC_0, * , INTERNAL, X ),"&
"157 (BC_0, * , INTERNAL, X ),"&
"156 (BC_0, * , INTERNAL, X ),"&
"155 (BC_0, * , INTERNAL, X ),"&
"154 (BC_0, * , INTERNAL, X ),"&
"153 (BC_0, * , INTERNAL, X ),"&
"152 (BC_0, * , INTERNAL, X ),"&
"151 (BC_0, * , INTERNAL, X ),"&
"150 (BC_0, * , INTERNAL, X ),"&
"149 (BC_0, * , INTERNAL, X ),"&
"148 (BC_0, * , INTERNAL, X ),"&
"147 (BC_0, * , INTERNAL, X ),"&
"146 (BC_0, * , INTERNAL, X ),"&
"145 (BC_0, * , INTERNAL, X ),"&
"144 (BC_0, * , INTERNAL, X ),"&
"143 (BC_4, PIO0_1_CLKOUT_CT32B0_MAT2_USB_FTOGGLE , INPUT, X ),"&
"142 (BC_1, PIO0_1_CLKOUT_CT32B0_MAT2_USB_FTOGGLE , OUTPUT3, X, 141, 0, Z ),"&
"141 (BC_1, * , CONTROL, 0 ),"&
"140 (BC_0, * , INTERNAL, X ),"&
"139 (BC_0, * , INTERNAL, X ),"&
"138 (BC_0, * , INTERNAL, X ),"&
"137 (BC_4, PIO2_0_XTALIN , INPUT, X ),"&
"136 (BC_1, PIO2_0_XTALIN , OUTPUT3, X, 135, 0, Z ),"&
"135 (BC_1, * , CONTROL, 0 ),"&
"134 (BC_4, PIO2_1_XTALOUT , INPUT, X ),"&
"133 (BC_1, PIO2_1_XTALOUT , OUTPUT3, X, 132, 0, Z ),"&
"132 (BC_1, * , CONTROL, 0 ),"&
"131 (BC_4, PIO2_5_U3_CTSn_SCT0_IN1 , INPUT, X ),"&
"130 (BC_1, PIO2_5_U3_CTSn_SCT0_IN1 , OUTPUT3, X, 129, 0, Z ),"&
"129 (BC_1, * , CONTROL, 0 ),"&
"128 (BC_0, * , INTERNAL, X ),"&
"127 (BC_0, * , INTERNAL, X ),"&
"126 (BC_0, * , INTERNAL, X ),"&
"125 (BC_4, PIO0_20_CT16B1_CAP0_U2_RXD , INPUT, X ),"&
"124 (BC_1, PIO0_20_CT16B1_CAP0_U2_RXD , OUTPUT3, X, 123, 0, Z ),"&
"123 (BC_1, * , CONTROL, 0 ),"&
"122 (BC_0, * , INTERNAL, X ),"&
"121 (BC_0, * , INTERNAL, X ),"&
"120 (BC_0, * , INTERNAL, X ),"&
"119 (BC_4, PIO0_2_SSP0_SSEL_CT16B0_CAP0_EZH_0 , INPUT, X ),"&
"118 (BC_1, PIO0_2_SSP0_SSEL_CT16B0_CAP0_EZH_0 , OUTPUT3, X, 117, 0, Z ),"&
"117 (BC_1, * , CONTROL, 0 ),"&
"116 (BC_0, * , INTERNAL, X ),"&
"115 (BC_0, * , INTERNAL, X ),"&
"114 (BC_0, * , INTERNAL, X ),"&
"113 (BC_4, PIO2_2_U3_RTSn_U3_SCLK_SCT0_OUT1 , INPUT, X ),"&
"112 (BC_1, PIO2_2_U3_RTSn_U3_SCLK_SCT0_OUT1 , OUTPUT3, X, 111, 0, Z ),"&
"111 (BC_1, * , CONTROL, 0 ),"&
"110 (BC_0, * , INTERNAL, X ),"&
"109 (BC_0, * , INTERNAL, X ),"&
"108 (BC_0, * , INTERNAL, X ),"&
"107 (BC_0, * , INTERNAL, X ),"&
"106 (BC_0, * , INTERNAL, X ),"&
"105 (BC_0, * , INTERNAL, X ),"&
"104 (BC_0, * , INTERNAL, X ),"&
"103 (BC_0, * , INTERNAL, X ),"&
"102 (BC_0, * , INTERNAL, X ),"&
"101 (BC_0, * , INTERNAL, X ),"&
"100 (BC_0, * , INTERNAL, X ),"&
" 99 (BC_0, * , INTERNAL, X ),"&
" 98 (BC_0, * , INTERNAL, X ),"&
" 97 (BC_0, * , INTERNAL, X ),"&
" 96 (BC_0, * , INTERNAL, X ),"&
" 95 (BC_0, * , INTERNAL, X ),"&
" 94 (BC_0, * , INTERNAL, X ),"&
" 93 (BC_0, * , INTERNAL, X ),"&
" 92 (BC_0, * , INTERNAL, X ),"&
" 91 (BC_0, * , INTERNAL, X ),"&
" 90 (BC_0, * , INTERNAL, X ),"&
" 89 (BC_4, PIO1_20_U0_DSRn_SSP1_SCK_CT16B0_MAT0 , INPUT, X ),"&
" 88 (BC_1, PIO1_20_U0_DSRn_SSP1_SCK_CT16B0_MAT0 , OUTPUT3, X, 87, 0, Z ),"&
" 87 (BC_1, * , CONTROL, 0 ),"&
" 86 (BC_4, PIO0_3_USB_VBUS_EZH_1 , INPUT, X ),"&
" 85 (BC_1, PIO0_3_USB_VBUS_EZH_1 , OUTPUT3, X, 84, 0, Z ),"&
" 84 (BC_1, * , CONTROL, 0 ),"&
" 83 (BC_4, PIO0_4_I2C0_SCL_EZH_2 , INPUT, X ),"&
" 82 (BC_1, PIO0_4_I2C0_SCL_EZH_2 , OUTPUT3, X, 81, 0, WEAK1 ),"&
" 81 (BC_1, * , CONTROL, 0 ),"&
" 80 (BC_4, PIO0_5_I2C0_SDA_EZH_3 , INPUT, X ),"&
" 79 (BC_1, PIO0_5_I2C0_SDA_EZH_3 , OUTPUT3, X, 78, 0, WEAK1 ),"&
" 78 (BC_1, * , CONTROL, 0 ),"&
" 77 (BC_4, PIO0_21_CT16B1_MAT0_SSP1_MOSI , INPUT, X ),"&
" 76 (BC_1, PIO0_21_CT16B1_MAT0_SSP1_MOSI , OUTPUT3, X, 75, 0, Z ),"&
" 75 (BC_1, * , CONTROL, 0 ),"&
" 74 (BC_0, * , INTERNAL, X ),"&
" 73 (BC_0, * , INTERNAL, X ),"&
" 72 (BC_0, * , INTERNAL, X ),"&
" 71 (BC_4, PIO1_23_CT16B1_MAT1_SSP1_SSEL_U2_TXD , INPUT, X ),"&
" 70 (BC_1, PIO1_23_CT16B1_MAT1_SSP1_SSEL_U2_TXD , OUTPUT3, X, 69, 0, Z ),"&
" 69 (BC_1, * , CONTROL, 0 ),"&
" 68 (BC_0, * , INTERNAL, X ),"&
" 67 (BC_0, * , INTERNAL, X ),"&
" 66 (BC_0, * , INTERNAL, X ),"&
" 65 (BC_0, * , INTERNAL, X ),"&
" 64 (BC_0, * , INTERNAL, X ),"&
" 63 (BC_0, * , INTERNAL, X ),"&
" 62 (BC_4, PIO2_7_SSP0_SCK_SCT0_OUT2 , INPUT, X ),"&
" 61 (BC_1, PIO2_7_SSP0_SCK_SCT0_OUT2 , OUTPUT3, X, 60, 0, Z ),"&
" 60 (BC_1, * , CONTROL, 0 ),"&
" 59 (BC_0, * , INTERNAL, X ),"&
" 58 (BC_0, * , INTERNAL, X ),"&
" 57 (BC_0, * , INTERNAL, X ),"&
" 56 (BC_4, PIO1_24_CT32B0_MAT0_I2C1_SDA , INPUT, X ),"&
" 55 (BC_1, PIO1_24_CT32B0_MAT0_I2C1_SDA , OUTPUT3, X, 54, 0, Z ),"&
" 54 (BC_1, * , CONTROL, 0 ),"&
" 53 (BC_0, * , INTERNAL, X ),"&
" 52 (BC_0, * , INTERNAL, X ),"&
" 51 (BC_0, * , INTERNAL, X ),"&
" 50 (BC_4, PIO0_6_USB_CONNECTn_SSP0_SCK_EZH_4 , INPUT, X ),"&
" 49 (BC_1, PIO0_6_USB_CONNECTn_SSP0_SCK_EZH_4 , OUTPUT3, X, 48, 0, Z ),"&
" 48 (BC_1, * , CONTROL, 0 ),"&
" 47 (BC_4, PIO0_7_U0_CTSn_EZH_5_I2C1_SCL , INPUT, X ),"&
" 46 (BC_1, PIO0_7_U0_CTSn_EZH_5_I2C1_SCL , OUTPUT3, X, 45, 0, Z ),"&
" 45 (BC_1, * , CONTROL, 0 ),"&
" 44 (BC_0, * , INTERNAL, X ),"&
" 43 (BC_0, * , INTERNAL, X ),"&
" 42 (BC_0, * , INTERNAL, X ),"&
" 41 (BC_0, * , INTERNAL, X ),"&
" 40 (BC_0, * , INTERNAL, X ),"&
" 39 (BC_0, * , INTERNAL, X ),"&
" 38 (BC_0, * , INTERNAL, X ),"&
" 37 (BC_0, * , INTERNAL, X ),"&
" 36 (BC_0, * , INTERNAL, X ),"&
" 35 (BC_0, * , INTERNAL, X ),"&
" 34 (BC_0, * , INTERNAL, X ),"&
" 33 (BC_0, * , INTERNAL, X ),"&
" 32 (BC_0, * , INTERNAL, X ),"&
" 31 (BC_0, * , INTERNAL, X ),"&
" 30 (BC_0, * , INTERNAL, X ),"&
" 29 (BC_0, * , INTERNAL, X ),"&
" 28 (BC_0, * , INTERNAL, X ),"&
" 27 (BC_0, * , INTERNAL, X ),"&
" 26 (BC_0, * , INTERNAL, X ),"&
" 25 (BC_0, * , INTERNAL, X ),"&
" 24 (BC_0, * , INTERNAL, X ),"&
" 23 (BC_0, * , INTERNAL, X ),"&
" 22 (BC_0, * , INTERNAL, X ),"&
" 21 (BC_0, * , INTERNAL, X ),"&
" 20 (BC_4, PIO1_21_U0_DCDn_SSP1_MISO_CT16B0_CAP1 , INPUT, X ),"&
" 19 (BC_1, PIO1_21_U0_DCDn_SSP1_MISO_CT16B0_CAP1 , OUTPUT3, X, 18, 0, Z ),"&
" 18 (BC_1, * , CONTROL, 0 ),"&
" 17 (BC_0, * , INTERNAL, X ),"&
" 16 (BC_0, * , INTERNAL, X ),"&
" 15 (BC_0, * , INTERNAL, X ),"&
" 14 (BC_4, PIO0_8_SSP0_MISO_CT16B0_MAT0_EZH_6 , INPUT, X ),"&
" 13 (BC_1, PIO0_8_SSP0_MISO_CT16B0_MAT0_EZH_6 , OUTPUT3, X, 12, 0, Z ),"&
" 12 (BC_1, * , CONTROL, 0 ),"&
" 11 (BC_4, PIO0_9_SSP0_MOSI_CT16B0_MAT1_EZH_7 , INPUT, X ),"&
" 10 (BC_1, PIO0_9_SSP0_MOSI_CT16B0_MAT1_EZH_7 , OUTPUT3, X, 9, 0, Z ),"&
" 9 (BC_1, * , CONTROL, 0 ),"&
" 8 (BC_0, * , INTERNAL, X ),"&
" 7 (BC_0, * , INTERNAL, X ),"&
" 6 (BC_0, * , INTERNAL, X ),"&
" 5 (BC_4, PIO0_22_ADC_11_CT16B1_CAP1_SSP1_MISO , INPUT, X ),"&
" 4 (BC_1, PIO0_22_ADC_11_CT16B1_CAP1_SSP1_MISO , OUTPUT3, X, 3, 0, Z ),"&
" 3 (BC_1, * , CONTROL, 0 ),"&
" 2 (BC_0, * , INTERNAL, X ),"&
" 1 (BC_0, * , INTERNAL, X ),"&
" 0 (BC_0, * , INTERNAL, X )";
end LPC11U6x;