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BSDL model: IDT82P2917A

-- *****************************************************************************

--   BSDL file for design IDT82P2917A

--   Created by Synopsys Version W-2004.12-SP2-2 (Apr 12, 2005)

--   Designer: 
--   Company:  IDT-Newave Tech

--   Date: Mon Jun 20 16:16:43 2005

-- *****************************************************************************


 entity IDT82P2917A is
   
-- This section identifies the default device package selected.
   
   generic (PHYSICAL_PIN_MAP: string:= "IDT82P2917ABH");
   
-- This section declares all the ports in the design.
   
   port ( 
          ALE_AS       : in       bit;
          CLKA         : in       bit;
          CLKB         : in       bit;
          CSB          : in       bit;
          IM           : in       bit;
          INT_MOTB     : in       bit;
          MCLK         : in       bit;
          OE           : in       bit;
          P_SB         : in       bit;
          RIM          : in       bit;
          RSTB         : in       bit;
          SCLK_DS_RDB  : in       bit;
          SDI_WRB_RWB  : in       bit;
          TCK          : in       bit;
          TDI          : in       bit;
          TEHW         : in       bit;
          TEHWE        : in       bit;
          TMS          : in       bit;
          TRSTB        : in       bit;
          A            : in       bit_vector (0 to 10);
          MCKSEL       : in       bit_vector (0 to 3);
          TCLK         : in       bit_vector (0 to 16);
          TDP          : in       bit_vector (0 to 16);
          D            : inout    bit_vector (0 to 7);
          GPIO         : inout    bit_vector (0 to 1);
          TDN          : inout    bit_vector (0 to 16);
          CLKE1        : out      bit;
          CLKT1        : out      bit;
          INTB         : out      bit;
          LLOS         : out      bit;
          LLOS0        : out      bit;
          REFA         : out      bit;
          REFB         : out      bit;
          SDO_RDY_ACKB : out      bit;
          TDO          : out      bit;
          RCLK         : out      bit_vector (0 to 16);
          RDN          : out      bit_vector (0 to 16);
          RDP          : out      bit_vector (0 to 16);
          NC           : linkage  bit;
          REF          : linkage  bit;
          RRING0      : linkage  bit;
          RRING10    : linkage  bit;
          RRING11    : linkage  bit;
          RRING12    : linkage  bit;
          RRING13    : linkage  bit;
          RRING14    : linkage  bit;
          RRING15    : linkage  bit;
          RRING16    : linkage  bit;
          RRING1     : linkage  bit;
          RRING2     : linkage  bit;
          RRING3     : linkage  bit;
          RRING4     : linkage  bit;
          RRING5     : linkage  bit;
          RRING6     : linkage  bit;
          RRING7     : linkage  bit;
          RRING8     : linkage  bit;
          RRING9     : linkage  bit;
          RTIP0      : linkage  bit;
          RTIP10     : linkage  bit;
          RTIP11     : linkage  bit;
          RTIP12     : linkage  bit;
          RTIP13     : linkage  bit;
          RTIP14     : linkage  bit;
          RTIP15     : linkage  bit;
          RTIP16     : linkage  bit;
          RTIP1      : linkage  bit;
          RTIP2      : linkage  bit;
          RTIP3      : linkage  bit;
          RTIP4      : linkage  bit;
          RTIP5      : linkage  bit;
          RTIP6      : linkage  bit;
          RTIP7      : linkage  bit;
          RTIP8      : linkage  bit;
          RTIP9      : linkage  bit;
          TESTSE       : linkage  bit;
          TRING0     : linkage  bit;
          TRING10    : linkage  bit;
          TRING11    : linkage  bit;
          TRING12    : linkage  bit;
          TRING13    : linkage  bit;
          TRING14    : linkage  bit;
          TRING15    : linkage  bit;
          TRING16    : linkage  bit;
          TRING1     : linkage  bit;
          TRING2     : linkage  bit;
          TRING3     : linkage  bit;
          TRING4     : linkage  bit;
          TRING5     : linkage  bit;
          TRING6     : linkage  bit;
          TRING7     : linkage  bit;
          TRING8     : linkage  bit;
          TRING9     : linkage  bit;
          TTIP0      : linkage  bit;
          TTIP10     : linkage  bit;
          TTIP11     : linkage  bit;
          TTIP12     : linkage  bit;
          TTIP13     : linkage  bit;
          TTIP14     : linkage  bit;
          TTIP15     : linkage  bit;
          TTIP16     : linkage  bit;
          TTIP1      : linkage  bit;
          TTIP2      : linkage  bit;
          TTIP3      : linkage  bit;
          TTIP4      : linkage  bit;
          TTIP5      : linkage  bit;
          TTIP6      : linkage  bit;
          TTIP7      : linkage  bit;
          TTIP8      : linkage  bit;
          TTIP9      : linkage  bit;
          VCOMEN       : linkage  bit;
          VCOM0      : linkage  bit;
          VCOM1      : linkage  bit;
          VDDR0        : linkage  bit;
          VDDR1        : linkage  bit;
          VDDR10       : linkage  bit;
          VDDR11       : linkage  bit;
          VDDR12       : linkage  bit;
          VDDR13       : linkage  bit;
          VDDR14       : linkage  bit;
          VDDR15       : linkage  bit;
          VDDR16       : linkage  bit;
          VDDR2        : linkage  bit;
          VDDR3        : linkage  bit;
          VDDR4        : linkage  bit;
          VDDR5        : linkage  bit;
          VDDR6        : linkage  bit;
          VDDR7        : linkage  bit;
          VDDR8        : linkage  bit;
          VDDR9        : linkage  bit;
          VDDT0        : linkage  bit;
          VDDT1        : linkage  bit;
          VDDT10       : linkage  bit;
          VDDT11       : linkage  bit;
          VDDT12       : linkage  bit;
          VDDT13       : linkage  bit;
          VDDT14       : linkage  bit;
          VDDT15       : linkage  bit;
          VDDT16       : linkage  bit;
          VDDT2        : linkage  bit;
          VDDT3        : linkage  bit;
          VDDT4        : linkage  bit;
          VDDT5        : linkage  bit;
          VDDT6        : linkage  bit;
          VDDT7        : linkage  bit;
          VDDT8        : linkage  bit;
          VDDT9        : linkage  bit;
          GNDA         : linkage  bit_vector (1 to 33);
          GNDD         : linkage  bit_vector (1 to 64);
          GNDT         : linkage  bit_vector (1 to 17);
          VDDA         : linkage  bit_vector (1 to 12);
          VDDD         : linkage  bit_vector (1 to 11);
          VDDIO        : linkage  bit_vector (1 to 16)
   );
   
   use STD_1149_1_2001.all;
   
   attribute COMPONENT_CONFORMANCE of IDT82P2917A: entity is "STD_1149_1_2001";
   
   attribute PIN_MAP of IDT82P2917A: entity is PHYSICAL_PIN_MAP;
   
-- This section specifies the pin map for each port. This information is 
-- extracted from the port-to-pin map file that was read in using the 
-- "read_pin_map" command.
   
     constant IDT82P2917ABH: PIN_MAP_STRING := 
        "ALE_AS       : AD17," &
        "CLKA         : AE20," &
        "CLKB         : AF20," &
        "CSB          : AD18," &
        "IM           : AC17," &
        "INT_MOTB     : AD16," &
        "MCLK         : AF21," &
        "OE           : AF9," &
        "P_SB         : AC16," &
        "RIM          : AE9," &
        "RSTB         : AF10," &
        "SCLK_DS_RDB  : AE18," &
        "SDI_WRB_RWB  : AF17," &
        "TCK          : AE8," &
        "TDI          : AF8," &
        "TEHW         : AC10," &
        "TEHWE        : AD10," &
        "TMS          : AD7," &
        "TRSTB        : AE7," &
        "A            : (AE16, AF16, AD15, AE15, AF15, AC14, AD14, AE14, " &
        "AF14, AD13, AE13)," &
        "MCKSEL       : (AE21, AD21, AD22, AC22)," &
        "TCLK         : (AE6, Y3, AB2, AD1, AE4, AF23, AD25, AB25, Y26, C21" &
        ", B19, A17, D16, C14, B12, B10, A8)," &
        "TDP          : (AD5, Y1, AA3, AC2, AD3, AF22, AE24, AC24, AA25, B20" &
        ", A18, C17, B15, A13, D12, D10, C8)," &
        "D            : (AF13, AC12, AD12, AE12, AF12, AD11, AE11, AF11)," &
        "GPIO         : (AD9, AC8)," &
        "TDN          : (AF6, Y2, AB1, AC3, AF4, AE22, AD26, AB26, AA24, A20" &
        ", C19, B17, A15, D14, C12, C10, B8)," &
        "CLKE1        : AD20," &
        "CLKT1        : AC21," &
        "INTB         : AF18," &
        "LLOS         : AD19," &
        "LLOS0        : AC19," &
        "REFA         : AE19," &
        "REFB         : AF19," &
        "SDO_RDY_ACKB : AE17," &
        "TDO          : AD8," &
        "RCLK         : (AF7, AA2, AC1, AE3, AE5, AF24, AC25, AA26, Y23, B22" &
        ", C20, B18, A16, C15, B13, A11, A9)," &
        "RDN          : (AC6, AA1, AB4, AF3, AF5, AD23, AC26, AB23, Y24, A21" &
        ", D20, C18, B16, A14, C13, B11, B9)," &
        "RDP          : (AD6, Y4, AB3, AD2, AD4, AE23, AD24, AB24, Y25, B21" &
        ", A19, D18, C16, B14, A12, A10, C9)," &
        "NC           : C22," &
        "REF          : A22," &
        "RRING0     : J4," &
        "RRING10    : G23," &
        "RRING11    : E24," &
        "RRING12    : C23," &
        "RRING13    : D6," &
        "RRING14    : C4," &
        "RRING15    : E4," &
        "RRING16    : G3," &
        "RRING1     : L3," &
        "RRING2     : N4," &
        "RRING3     : R3," &
        "RRING4     : U4," &
        "RRING5     : U24," &
        "RRING6     : R23," &
        "RRING7     : N24," &
        "RRING8     : L23," &
        "RRING9     : J24," &
        "RTIP0      : K4," &
        "RTIP10     : H23," &
        "RTIP11     : F24," &
        "RTIP12     : C24," &
        "RTIP13     : D5," &
        "RTIP14     : C3," &
        "RTIP15     : F4," &
        "RTIP16     : H3," &
        "RTIP1      : M3," &
        "RTIP2      : P4," &
        "RTIP3      : T3," &
        "RTIP4      : V4," &
        "RTIP5      : V24," &
        "RTIP6      : T23," &
        "RTIP7      : P24," &
        "RTIP8      : M23," &
        "RTIP9      : K24," &
        "TESTSE       : AE10," &
        "TRING0     : J1," &
        "TRING10    : G26," &
        "TRING11    : E26," &
        "TRING12    : A23," &
        "TRING13    : A6," &
        "TRING14    : A4," &
        "TRING15    : E1," &
        "TRING16    : G1," &
        "TRING1     : L1," &
        "TRING2     : N1," &
        "TRING3     : R1," &
        "TRING4     : U1," &
        "TRING5     : U26," &
        "TRING6     : R26," &
        "TRING7     : N26," &
        "TRING8     : L26," &
        "TRING9     : J26," &
        "TTIP0      : K1," &
        "TTIP10     : H26," &
        "TTIP11     : F26," &
        "TTIP12     : A24," &
        "TTIP13     : A5," &
        "TTIP14     : A3," &
        "TTIP15     : F1," &
        "TTIP16     : H1," &
        "TTIP1      : M1," &
        "TTIP2      : P1," &
        "TTIP3      : T1," &
        "TTIP4      : V1," &
        "TTIP5      : V26," &
        "TTIP6      : T26," &
        "TTIP7      : P26," &
        "TTIP8      : M26," &
        "TTIP9      : K26," &
        "VCOMEN       : W4," &
        "VCOM0      : W3," &
        "VCOM1      : W24," &
        "VDDR0        : J3," &
        "VDDR1        : K3," &
        "VDDR10       : G24," &
        "VDDR11       : D24," &
        "VDDR12       : D23," &
        "VDDR13       : C6," &
        "VDDR14       : C5," &
        "VDDR15       : E3," &
        "VDDR16       : F3," &
        "VDDR2        : N3," &
        "VDDR3        : P3," &
        "VDDR4        : U3," &
        "VDDR5        : T24," &
        "VDDR6        : R24," &
        "VDDR7        : M24," &
        "VDDR8        : L24," &
        "VDDR9        : H24," &
        "VDDT0        : J2," &
        "VDDT1        : K2," &
        "VDDT10       : G25," &
        "VDDT11       : B24," &
        "VDDT12       : B23," &
        "VDDT13       : B6," &
        "VDDT14       : B5," &
        "VDDT15       : E2," &
        "VDDT16       : F2," &
        "VDDT2        : N2," &
        "VDDT3        : P2," &
        "VDDT4        : U2," &
        "VDDT5        : T25," &
        "VDDT6        : R25," &
        "VDDT7        : M25," &
        "VDDT8        : L25," &
        "VDDT9        : H25," &
        "GNDA         : (A1, A2, A25, A26, B1, B2, B25, B26, D4, E23, F23, " &
        "G4, H4, J23, K23, L4, M4, N23, P23, R4, T4, U23, V23, V2, V3, AE1, " &
        "AE2, AE25, AE26, AF1, AF2, AF25, AF26)," &
        "GNDD         : (K10, K11, K12, K13, K14, K15, K16, K17, L10, L11, " &
        "L12, L13, L14, L15, L16, L17, M10, M11, M12, M13, M14, M15, M16, " &
        "M17, N10, N11, N12, N13, N14, N15, N16, N17, P10, P11, P12, P13, " &
        "P14, P15, P16, P17, R10, R11, R12, R13, R14, R15, R16, R17, T10, " &
        "T11, T12, T13, T14, T15, T16, T17, U10, U11, U12, U13, U14, U15, " &
        "U16, U17)," &
        "GNDT         : (B3, B4, D3, E25, F25, G2, H2, J25, K25, L2, M2, N25" &
        ", P25, R2, T2, U25, V25)," &
        "VDDA         : (C1, C2, C25, C26, D1, D2, D25, D26, W1, W2, W25, " &
        "W26)," &
        "VDDD         : (C11, D11, D13, D15, D17, AC5, AC7, AC9, AC18, AC20" &
        ", AC23)," &
        "VDDIO        : (A7, B7, C7, D7, D8, D9, D19, D21, D22, W23, AA4, " &
        "AA23, AC4, AC11, AC13, AC15)";
   
-- This section specifies the TAP ports. For the TAP TCK port, the parameters in 
-- the brackets are:
--        First Field : Maximum  TCK frequency.
--        Second Field: Allowable states TCK may be stopped in.
   
   attribute TAP_SCAN_CLOCK of TCK  : signal is (10.0e6, BOTH);
   attribute TAP_SCAN_IN    of TDI  : signal is true;
   attribute TAP_SCAN_MODE  of TMS  : signal is true;
   attribute TAP_SCAN_OUT   of TDO  : signal is true;
   attribute TAP_SCAN_RESET of TRSTB: signal is true;
   
-- Specifies the number of bits in the instruction register.
   
   attribute INSTRUCTION_LENGTH of IDT82P2917A: entity is 3;
   
-- Specifies the boundary-scan instructions implemented in the design and their 
-- opcodes.
   
   attribute INSTRUCTION_OPCODE of IDT82P2917A: entity is 
     "BYPASS  (111)," &
     "EXTEST  (000)," &
     "SAMPLE  (010)," &
     "PRELOAD (010)," &
     "HIGHZ   (100)," &
     "CLAMP   (011)," &
     "IDCODE  (001)";
   
-- Specifies the bit pattern that is loaded into the instruction register when 
-- the TAP controller passes through the Capture-IR state. The standard mandates 
-- that the two LSBs must be "01". The remaining bits are design specific.
   
   attribute INSTRUCTION_CAPTURE of IDT82P2917A: entity is "001";
   
-- Specifies the bit pattern that is loaded into the DEVICE_ID register during 
-- the IDCODE instruction when the TAP controller passes through the Capture-DR 
-- state.
   
   attribute IDCODE_REGISTER of IDT82P2917A: entity is 
     "0000" &                  
 -- 4-bit version number
     "0000010011011101" &      
 -- 16-bit part number
     "00010110011" &           
 -- 11-bit identity of the manufacturer
     "1";                      
 -- Required by IEEE Std 1149.1
   
-- This section specifies the test data register placed between TDI and TDO for 
-- each implemented instruction.
   
   attribute REGISTER_ACCESS of IDT82P2917A: entity is 
        "BYPASS    (BYPASS, HIGHZ, CLAMP)," &
        "BOUNDARY  (EXTEST, SAMPLE, PRELOAD)," &
        "DEVICE_ID (IDCODE)";
   
-- Specifies the length of the boundary scan register.
   
   attribute BOUNDARY_LENGTH of IDT82P2917A: entity is 195;
   
-- The following list specifies the characteristics of each cell in the boundary 
-- scan register from TDI to TDO. The following is a description of the label 
-- fields:
--      num     : Is the cell number.
--      cell    : Is the cell type as defined by the standard.
--      port    : Is the design port name. Control cells do not have a port 
--                name.
--      function: Is the function of the cell as defined by the standard. Is one 
--                of input, output2, output3, bidir, control or controlr.
--      safe    : Specifies the value that the BSR cell should be loaded with 
--                for safe operation when the software might otherwise choose a 
--                random value.
--      ccell   : The control cell number. Specifies the control cell that 
--                drives the output enable for this port.
--      disval  : Specifies the value that is loaded into the control cell to 
--                disable the output enable for the corresponding port.
--      rslt    : Resulting state. Shows the state of the driver when it is 
--                disabled.
   
   attribute BOUNDARY_REGISTER of IDT82P2917A: entity is 
--     
--    num   cell   port          function      safe  (ccell  disval  rslt)
--     
     "194  (BC_1,  RDP(9),       output3,      X,    191,    1,      Z),  " &
     "193  (BC_1,  RDN(9),       output3,      X,    191,    1,      Z),  " &
     "192  (BC_1,  RCLK(9),      output3,      X,    191,    1,      Z),  " &
     "191  (BC_1,  *,            control,      1),                        " &
     "190  (BC_3,  TDP(9),       input,        X),                        " &
     "189  (BC_7,  TDN(9),       bidir,        X,    188,    1,      Z),  " &
     "188  (BC_1,  *,            control,      1),                        " &
     "187  (BC_3,  TCLK(9),      input,        X),                        " &
     "186  (BC_1,  RDP(10),      output3,      X,    183,    1,      Z),  " &
     "185  (BC_1,  RDN(10),      output3,      X,    183,    1,      Z),  " &
     "184  (BC_1,  RCLK(10),     output3,      X,    183,    1,      Z),  " &
     "183  (BC_1,  *,            control,      1),                        " &
     "182  (BC_3,  TDP(10),      input,        X),                        " &
     "181  (BC_7,  TDN(10),      bidir,        X,    180,    1,      Z),  " &
     "180  (BC_1,  *,            control,      1),                        " &
     "179  (BC_3,  TCLK(10),     input,        X),                        " &
     "178  (BC_1,  RDP(11),      output3,      X,    175,    1,      Z),  " &
     "177  (BC_1,  RDN(11),      output3,      X,    175,    1,      Z),  " &
     "176  (BC_1,  RCLK(11),     output3,      X,    175,    1,      Z),  " &
     "175  (BC_1,  *,            control,      1),                        " &
     "174  (BC_3,  TDP(11),      input,        X),                        " &
     "173  (BC_7,  TDN(11),      bidir,        X,    172,    1,      Z),  " &
     "172  (BC_1,  *,            control,      1),                        " &
     "171  (BC_3,  TCLK(11),     input,        X),                        " &
     "170  (BC_1,  RDP(12),      output3,      X,    167,    1,      Z),  " &
     "169  (BC_1,  RDN(12),      output3,      X,    167,    1,      Z),  " &
     "168  (BC_1,  RCLK(12),     output3,      X,    167,    1,      Z),  " &
     "167  (BC_1,  *,            control,      1),                        " &
     "166  (BC_3,  TDP(12),      input,        X),                        " &
     "165  (BC_7,  TDN(12),      bidir,        X,    164,    1,      Z),  " &
     "164  (BC_1,  *,            control,      1),                        " &
     "163  (BC_3,  TCLK(12),     input,        X),                        " &
     "162  (BC_1,  RDP(13),      output3,      X,    159,    1,      Z),  " &
     "161  (BC_1,  RDN(13),      output3,      X,    159,    1,      Z),  " &
     "160  (BC_1,  RCLK(13),     output3,      X,    159,    1,      Z),  " &
     "159  (BC_1,  *,            control,      1),                        " &
     "158  (BC_3,  TDP(13),      input,        X),                        " &
     "157  (BC_7,  TDN(13),      bidir,        X,    156,    1,      Z),  " &
     "156  (BC_1,  *,            control,      1),                        " &
     "155  (BC_3,  TCLK(13),     input,        X),                        " &
     "154  (BC_1,  RDP(14),      output3,      X,    151,    1,      Z),  " &
     "153  (BC_1,  RDN(14),      output3,      X,    151,    1,      Z),  " &
     "152  (BC_1,  RCLK(14),     output3,      X,    151,    1,      Z),  " &
     "151  (BC_1,  *,            control,      1),                        " &
     "150  (BC_3,  TDP(14),      input,        X),                        " &
     "149  (BC_7,  TDN(14),      bidir,        X,    148,    1,      Z),  " &
     "148  (BC_1,  *,            control,      1),                        " &
     "147  (BC_3,  TCLK(14),     input,        X),                        " &
     "146  (BC_1,  RDP(15),      output3,      X,    143,    1,      Z),  " &
     "145  (BC_1,  RDN(15),      output3,      X,    143,    1,      Z),  " &
     "144  (BC_1,  RCLK(15),     output3,      X,    143,    1,      Z),  " &
     "143  (BC_1,  *,            control,      1),                        " &
     "142  (BC_3,  TDP(15),      input,        X),                        " &
     "141  (BC_7,  TDN(15),      bidir,        X,    140,    1,      Z),  " &
     "140  (BC_1,  *,            control,      1),                        " &
     "139  (BC_3,  TCLK(15),     input,        X),                        " &
     "138  (BC_1,  RDP(16),      output3,      X,    135,    1,      Z),  " &
     "137  (BC_1,  RDN(16),      output3,      X,    135,    1,      Z),  " &
     "136  (BC_1,  RCLK(16),     output3,      X,    135,    1,      Z),  " &
     "135  (BC_1,  *,            control,      1),                        " &
     "134  (BC_3,  TDP(16),      input,        X),                        " &
     "133  (BC_7,  TDN(16),      bidir,        X,    132,    1,      Z),  " &
     "132  (BC_1,  *,            control,      1),                        " &
     "131  (BC_3,  TCLK(16),     input,        X),                        " &
     "130  (BC_1,  RDP(0),       output3,      X,    127,    1,      Z),  " &
     "129  (BC_1,  RDN(0),       output3,      X,    127,    1,      Z),  " &
     "128  (BC_1,  RCLK(0),      output3,      X,    127,    1,      Z),  " &
     "127  (BC_1,  *,            control,      1),                        " &
     "126  (BC_3,  TDP(0),       input,        X),                        " &
     "125  (BC_7,  TDN(0),       bidir,        X,    124,    1,      Z),  " &
     "124  (BC_1,  *,            control,      1),                        " &
     "123  (BC_3,  TCLK(0),      input,        X),                        " &
     "122  (BC_1,  RDP(1),       output3,      X,    119,    1,      Z),  " &
     "121  (BC_1,  RDN(1),       output3,      X,    119,    1,      Z),  " &
     "120  (BC_1,  RCLK(1),      output3,      X,    119,    1,      Z),  " &
     "119  (BC_1,  *,            control,      1),                        " &
     "118  (BC_3,  TDP(1),       input,        X),                        " &
     "117  (BC_7,  TDN(1),       bidir,        X,    116,    1,      Z),  " &
     "116  (BC_1,  *,            control,      1),                        " &
     "115  (BC_3,  TCLK(1),      input,        X),                        " &
     "114  (BC_1,  RDP(2),       output3,      X,    111,    1,      Z),  " &
     "113  (BC_1,  RDN(2),       output3,      X,    111,    1,      Z),  " &
     "112  (BC_1,  RCLK(2),      output3,      X,    111,    1,      Z),  " &
     "111  (BC_1,  *,            control,      1),                        " &
     "110  (BC_3,  TDP(2),       input,        X),                        " &
     "109  (BC_7,  TDN(2),       bidir,        X,    108,    1,      Z),  " &
     "108  (BC_1,  *,            control,      1),                        " &
     "107  (BC_3,  TCLK(2),      input,        X),                        " &
     "106  (BC_1,  RDP(3),       output3,      X,    103,    1,      Z),  " &
     "105  (BC_1,  RDN(3),       output3,      X,    103,    1,      Z),  " &
     "104  (BC_1,  RCLK(3),      output3,      X,    103,    1,      Z),  " &
     "103  (BC_1,  *,            control,      1),                        " &
     "102  (BC_3,  TDP(3),       input,        X),                        " &
     "101  (BC_7,  TDN(3),       bidir,        X,    100,    1,      Z),  " &
     "100  (BC_1,  *,            control,      1),                        " &
     "99   (BC_3,  TCLK(3),      input,        X),                        " &
     "98   (BC_1,  RDP(4),       output3,      X,    95,     1,      Z),  " &
     "97   (BC_1,  RDN(4),       output3,      X,    95,     1,      Z),  " &
     "96   (BC_1,  RCLK(4),      output3,      X,    95,     1,      Z),  " &
     "95   (BC_1,  *,            control,      1),                        " &
     "94   (BC_3,  TDP(4),       input,        X),                        " &
     "93   (BC_7,  TDN(4),       bidir,        X,    92,     1,      Z),  " &
     "92   (BC_1,  *,            control,      1),                        " &
     "91   (BC_3,  TCLK(4),      input,        X),                        " &
     "90   (BC_1,  RDP(5),       output3,      X,    87,     1,      Z),  " &
     "89   (BC_1,  RDN(5),       output3,      X,    87,     1,      Z),  " &
     "88   (BC_1,  RCLK(5),      output3,      X,    87,     1,      Z),  " &
     "87   (BC_1,  *,            control,      1),                        " &
     "86   (BC_3,  TDP(5),       input,        X),                        " &
     "85   (BC_7,  TDN(5),       bidir,        X,    84,     1,      Z),  " &
     "84   (BC_1,  *,            control,      1),                        " &
     "83   (BC_3,  TCLK(5),      input,        X),                        " &
     "82   (BC_1,  RDP(6),       output3,      X,    79,     1,      Z),  " &
     "81   (BC_1,  RDN(6),       output3,      X,    79,     1,      Z),  " &
     "80   (BC_1,  RCLK(6),      output3,      X,    79,     1,      Z),  " &
     "79   (BC_1,  *,            control,      1),                        " &
     "78   (BC_3,  TDP(6),       input,        X),                        " &
     "77   (BC_7,  TDN(6),       bidir,        X,    76,     1,      Z),  " &
     "76   (BC_1,  *,            control,      1),                        " &
     "75   (BC_3,  TCLK(6),      input,        X),                        " &
     "74   (BC_1,  RDP(7),       output3,      X,    71,     1,      Z),  " &
     "73   (BC_1,  RDN(7),       output3,      X,    71,     1,      Z),  " &
     "72   (BC_1,  RCLK(7),      output3,      X,    71,     1,      Z),  " &
     "71   (BC_1,  *,            control,      1),                        " &
     "70   (BC_3,  TDP(7),       input,        X),                        " &
     "69   (BC_7,  TDN(7),       bidir,        X,    68,     1,      Z),  " &
     "68   (BC_1,  *,            control,      1),                        " &
     "67   (BC_3,  TCLK(7),      input,        X),                        " &
     "66   (BC_1,  RDP(8),       output3,      X,    63,     1,      Z),  " &
     "65   (BC_1,  RDN(8),       output3,      X,    63,     1,      Z),  " &
     "64   (BC_1,  RCLK(8),      output3,      X,    63,     1,      Z),  " &
     "63   (BC_1,  *,            control,      1),                        " &
     "62   (BC_3,  TDP(8),       input,        X),                        " &
     "61   (BC_7,  TDN(8),       bidir,        X,    60,     1,      Z),  " &
     "60   (BC_1,  *,            control,      1),                        " &
     "59   (BC_3,  TCLK(8),      input,        X),                        " &
     "58   (BC_1,  LLOS0,        output3,      X,    57,     1,      Z),  " &
     "57   (BC_1,  *,            control,      1),                        " &
     "56   (BC_1,  LLOS,         output3,      X,    55,     1,      Z),  " &
     "55   (BC_1,  *,            control,      1),                        " &
     "54   (BC_3,  RIM,          input,        X),                        " &
     "53   (BC_3,  OE,           input,        X),                        " &
     "52   (BC_3,  TEHW,         input,        X),                        " &
     "51   (BC_3,  TEHWE,        input,        X),                        " &
     "50   (BC_3,  RSTB,         input,        X),                        " &
     "49   (BC_7,  GPIO(1),      bidir,        X,    48,     1,      Z),  " &
     "48   (BC_1,  *,            control,      1),                        " &
     "47   (BC_7,  GPIO(0),      bidir,        X,    46,     1,      Z),  " &
     "46   (BC_1,  *,            control,      1),                        " &
     "45   (BC_1,  CLKE1,        output3,      X,    44,     1,      Z),  " &
     "44   (BC_1,  *,            control,      1),                        " &
     "43   (BC_1,  CLKT1,        output3,      X,    42,     1,      Z),  " &
     "42   (BC_1,  *,            control,      1),                        " &
     "41   (BC_1,  REFB,         output3,      X,    40,     1,      Z),  " &
     "40   (BC_1,  *,            control,      1),                        " &
     "39   (BC_1,  REFA,         output3,      X,    38,     1,      Z),  " &
     "38   (BC_1,  *,            control,      1),                        " &
     "37   (BC_3,  CLKB,         input,        X),                        " &
     "36   (BC_3,  CLKA,         input,        X),                        " &
     "35   (BC_3,  MCKSEL(0),    input,        X),                        " &
     "34   (BC_3,  MCKSEL(1),    input,        X),                        " &
     "33   (BC_3,  MCKSEL(2),    input,        X),                        " &
     "32   (BC_3,  MCKSEL(3),    input,        X),                        " &
     "31   (BC_3,  MCLK,         input,        X),                        " &
     "30   (BC_3,  A(0),         input,        X),                        " &
     "29   (BC_3,  A(1),         input,        X),                        " &
     "28   (BC_3,  A(2),         input,        X),                        " &
     "27   (BC_3,  A(3),         input,        X),                        " &
     "26   (BC_3,  A(4),         input,        X),                        " &
     "25   (BC_3,  A(5),         input,        X),                        " &
     "24   (BC_3,  A(6),         input,        X),                        " &
     "23   (BC_3,  A(7),         input,        X),                        " &
     "22   (BC_3,  A(8),         input,        X),                        " &
     "21   (BC_3,  A(9),         input,        X),                        " &
     "20   (BC_3,  A(10),        input,        X),                        " &
     "19   (BC_1,  *,            control,      1),                        " &
     "18   (BC_7,  D(0),         bidir,        X,    19,     1,      Z),  " &
     "17   (BC_7,  D(1),         bidir,        X,    19,     1,      Z),  " &
     "16   (BC_7,  D(2),         bidir,        X,    19,     1,      Z),  " &
     "15   (BC_7,  D(3),         bidir,        X,    19,     1,      Z),  " &
     "14   (BC_7,  D(4),         bidir,        X,    19,     1,      Z),  " &
     "13   (BC_7,  D(5),         bidir,        X,    19,     1,      Z),  " &
     "12   (BC_7,  D(6),         bidir,        X,    19,     1,      Z),  " &
     "11   (BC_7,  D(7),         bidir,        X,    19,     1,      Z),  " &
     "10   (BC_3,  ALE_AS,       input,        X),                        " &
     "9    (BC_1,  SDO_RDY_ACKB, output3,      X,    8,      1,      Z),  " &
     "8    (BC_1,  *,            control,      1),                        " &
     "7    (BC_3,  CSB,          input,        X),                        " &
     "6    (BC_3,  SDI_WRB_RWB,  input,        X),                        " &
     "5    (BC_3,  SCLK_DS_RDB,  input,        X),                        " &
     "4    (BC_3,  INT_MOTB,     input,        X),                        " &
     "3    (BC_3,  P_SB,         input,        X),                        " &
     "2    (BC_3,  IM,           input,        X),                        " &
     "1    (BC_1,  INTB,         output3,      X,    0,      1,      Z),  " &
     "0    (BC_1,  *,            control,      1)                         ";
 
 end IDT82P2917A;