BSDL Files Library for JTAG

The only free public library that contains thousands of BSDL (Boundary Scan Description Language) models to use with BScan/JTAG tools

BSDL model: Tsi382

-- ***************************************************************
--      Company:  Integrated Device Technology, Inc.
--
--      Document number: 35E2010_BS001_02 
--
--      Title: BSDL file of Tsi382
--      Generated by : Anjaneya Reddy
--
--      Release status: formal issue
--      Security level: client use
--      BSDL Version 2001
--      Group ownership: DFT         Revision Date: 
--      Released by  : Anjaneya Reddy      
--      Revision History:
--              September 20, 2007      :   initial release
--              November  19, 2007      :   Update ID version to '1' for A1
--              February  26, 2008      :   Update ID version A2 '2' for A2
--              September 2,  2009      :   Updated with IDT formatting
--              
--      BSDL Syntax Checker ->  Passed on February 26, 2008
--           
--           
-- ***************************************************************
--
-- Generated by boundaryScanGenerate 4.2b-Build20051027.004 on 03/13/07 11:47:24
-- BSDL Version 2001

-- In Instruction Register the bits [63:19] are termed as userBits[44:0].
-- The default acjt_lvl[4:0] which is userBits[11:7] is set to 5'h0A, and tx_lvl[4:0] which is userbits[17:13] is
-- set to 5'h00 and userbits[43] set to 1'b1.


entity Tsi382 is 
    generic (PHYSICAL_PIN_MAP : string := "PBGA_144_10");

    port (
        -- Port List
        PCIE_REXT            : linkage  bit;
        VDD                  : linkage  bit;
        PCI_AD               : inout    bit_vector( 31 downto 0 );
        VDD_PCI              : linkage  bit;
        VIO_PCI              : linkage  bit;
        PCI_CBEn             : inout    bit_vector( 3 downto 0 );
        VSS                  : linkage  bit;
        PCI_PMEn             : inout    bit;
        PCI_GNTn             : inout    bit_vector( 3 downto 0 );
        PCI_REQn             : inout    bit_vector( 3 downto 0 );
        PCI_RSTn             : inout    bit;
        PCI_CLK              : in       bit;
        PCI_CLKO             : out      bit_vector( 4 downto 0 );
        PCI_INTCn            : in       bit;
        PCI_INTBn            : in       bit;
        PCI_INTAn            : in       bit;
        PCI_INTDn            : in       bit;
        JTAG_TDO             : out      bit;
        VDDA_PLL             : linkage  bit;
        JTAG_TDI             : in       bit;
        VSSA_PLL             : linkage  bit;
        JTAG_TCK             : in       bit;
        PWRUP_EN_ARB         : linkage  bit;
        JTAG_TMS             : in       bit;
        JTAG_TRSTn           : in       bit;
        TEST_BCE             : in  bit;
        PWRUP_PLL_BYPASS     : linkage  bit;
        TEST_ON              : in  bit;
        PCIE_PERSTn          : in       bit;
        PCIE_REFCLK_n        : linkage  bit;
        PCIE_REFCLK_p        : linkage  bit;
        VDDA_PCIE            : linkage  bit;
        VDD_PCIE             : linkage  bit;
        PCIE_TXD_p           : out      bit;
        PCIE_TXD_n           : out      bit;
        PCIE_RXD_p           : in       bit;
        PCIE_RXD_n           : in       bit;
        TEST_BIDR_CTL        : in  bit;
        SR_CSn               : out      bit;
        SR_CLK               : out      bit;
        SR_DOUT              : in       bit;
        SR_DIN               : inout    bit;
        PCI_M66EN            : in       bit;
        PCI_SERRn            : inout    bit;
        PCI_PAR              : inout    bit;
        PCI_PERRn            : inout    bit;
        PCI_LOCKn            : inout    bit;
        PCI_STOPn            : inout    bit;
        PCI_TRDYn            : inout    bit;
        PCI_DEVSELn          : inout    bit;
        PCI_IRDYn            : inout    bit;
        PCI_FRAMEn           : inout    bit;
        GPIO                 : inout    bit_vector( 3 downto 0 ));

    use STD_1149_1_2001.all;
    use STD_1149_6_2003.all;
    use LVS_BSCAN_CELLS.all;

    attribute COMPONENT_CONFORMANCE of Tsi382: entity is "STD_1149_1_2001";

    --Pin mappings

    attribute PIN_MAP of Tsi382: entity is PHYSICAL_PIN_MAP;

    constant PBGA_144_10: PIN_MAP_STRING := 
    "PCIE_REXT            : A11    , " &
    "VDD                  : E5    , " &
    "PCI_AD               :(L12    , " &  -- PCI_AD[31]
                           "J12    , " &  -- PCI_AD[30]
                           "K12    , " &  -- PCI_AD[29]
                           "H9    , " &  -- PCI_AD[28]
                           "M11    , " &  -- PCI_AD[27]
                           "L8    , " &  -- PCI_AD[26]
                           "L10    , " &  -- PCI_AD[25]
                           "M10   , " &  -- PCI_AD[24]
                           "K8   , " &  -- PCI_AD[23]
                           "M8   , " &  -- PCI_AD[22]
                           "K7   , " &  -- PCI_AD[21]
                           "K6   , " &  -- PCI_AD[20]
                           "M6   , " &  -- PCI_AD[19]
                           "L6   , " &  -- PCI_AD[18]
                           "J7   , " &  -- PCI_AD[17]
                           "J5   , " &  -- PCI_AD[16]
                           "J1   , " &  -- PCI_AD[15]
                           "H4   , " &  -- PCI_AD[14]
                           "H1   , " &  -- PCI_AD[13]
                           "H3   , " &  -- PCI_AD[12]
                           "G1   , " &  -- PCI_AD[11]
                           "E1   , " &  -- PCI_AD[10]
                           "G4   , " &  -- PCI_AD[9]
                           "F1   , " &  -- PCI_AD[8]
                           "D3   , " &  -- PCI_AD[7]
                           "D1   , " &  -- PCI_AD[6]
                           "F2   , " &  -- PCI_AD[5]
                           "E2   , " &  -- PCI_AD[4]
                           "E3   , " &  -- PCI_AD[3]
                           "F4   , " &  -- PCI_AD[2]
                           "C2   , " &  -- PCI_AD[1]
                           "B1  ), " &  -- PCI_AD[0]
    "VDD_PCI              : D2   , " &
    "VIO_PCI              : C11   , " &
    "PCI_CBEn             :(L9   , " &  -- PCI_CBEn[3]
                           "M4   , " &  -- PCI_CBEn[2]
                           "J3   , " &  -- PCI_CBEn[1]
                           "F3  ), " &  -- PCI_CBEn[0]
    "VSS                  : A1   , " &
    "PCI_PMEn             : H12   , " &
    "PCI_GNTn             :(E10   , " &  -- PCI_GNTn[3]
                           "F11   , " &  -- PCI_GNTn[2]
                           "F12   , " &  -- PCI_GNTn[1]
                           "G9  ), " &  -- PCI_GNTn[0]
    "PCI_REQn             :(H11   , " &  -- PCI_REQn[3]
                           "G10   , " &  -- PCI_REQn[2]
                           "J10   , " &  -- PCI_REQn[1]
                           "F10  ), " &  -- PCI_REQn[0]
    "PCI_RSTn             : E12   , " &
    "PCI_CLK              : B12   , " &
    "PCI_CLKO             :(A12   , " &  -- PCI_CLKO[4]
                           "J8   , " &  -- PCI_CLKO[3]
                           "J9   , " &  -- PCI_CLKO[2]
                           "B2   , " &  -- PCI_CLKO[1]
                           "H10  ), " &  -- PCI_CLKO[0]
    "PCI_INTCn            : C10   , " &
    "PCI_INTBn            : F9   , " &
    "PCI_INTAn            : D12   , " &
    "PCI_INTDn            : C12   , " &
    "JTAG_TDO             : K3   , " &
    "VDDA_PLL             : B10   , " &
    "JTAG_TDI             : M3   , " &
    "VSSA_PLL             : A10   , " &
    "JTAG_TCK             : K4   , " &
    "PWRUP_EN_ARB         : K11   , " &
    "JTAG_TMS             : M12   , " &
    "JTAG_TRSTn           : K9   , " &
    "TEST_BCE             : D7   , " &
    "PWRUP_PLL_BYPASS     : L1   , " &
    "TEST_ON              : B3   , " &
    "PCIE_PERSTn          : B9   , " &
    "PCIE_REFCLK_n        : A8   , " &
    "PCIE_REFCLK_p        : B8   , " &
    "VDDA_PCIE            : C6   , " &
    "VDD_PCIE             : B5   , " &
    "PCIE_TXD_p           : A4   , " &
    "PCIE_TXD_n           : B4   , " &
    "PCIE_RXD_p           : A6   , " &
    "PCIE_RXD_n           : B6   , " &
    "TEST_BIDR_CTL        : C3   , " &
    "SR_CSn               : D4   , " &
    "SR_CLK               : A2   , " &
    "SR_DOUT              : E4  , " &
    "SR_DIN               : A3  , " &
    "PCI_M66EN            : B11  , " &
    "PCI_SERRn            : J2  , " &
    "PCI_PAR              : K1  , " &
    "PCI_PERRn            : J4  , " &
    "PCI_LOCKn            : L3  , " &
    "PCI_STOPn            : J6  , " &
    "PCI_TRDYn            : K5  , " &
    "PCI_DEVSELn          : M2  , " &
    "PCI_IRDYn            : L5  , " &
    "GPIO                 :(D9  , " &  -- GPIO[3]
                           "C9  , " &  -- GPIO[2]
                           "D8  , " &  -- GPIO[1]
                           "E9 ), " &  -- GPIO[0]
    "PCI_FRAMEn           : M5    " ;

    attribute PORT_GROUPING of Tsi382 : entity is 
        "Differential_Current ( (PCIE_TXD_p, PCIE_TXD_n), " &
                                "(PCIE_RXD_p, PCIE_RXD_n)) " ;
 
 
 
   attribute TAP_SCAN_RESET of JTAG_TRSTn                   : signal is true;
   attribute TAP_SCAN_IN    of JTAG_TDI                     : signal is true;
   attribute TAP_SCAN_MODE  of JTAG_TMS                     : signal is true;
   attribute TAP_SCAN_OUT   of JTAG_TDO                     : signal is true;
   attribute TAP_SCAN_CLOCK of JTAG_TCK                     : signal is (1.0000000000000000000e+07, BOTH);

   attribute COMPLIANCE_PATTERNS of Tsi382 : entity is
        "(TEST_BIDR_CTL, TEST_ON, TEST_BCE) (000)";
 
 
 
   attribute INSTRUCTION_LENGTH of Tsi382: entity is 64;
 
   attribute INSTRUCTION_OPCODE of Tsi382: entity is
      "IDCODE       (1111111111111111111111111111111111111111111111111111111111111110)," &
      "BYPASS       (0000000000000000000000000000000000000000000000000000000000000000, 1111111111111111111111111111111111111111111111111111111111111111)," &
      "EXTEST       (1011111111111111111111111111111111010111111111111111111111101000)," &
      "EXTEST_PULSE (1011111111111111111111111111111111010111111111101111111111101000)," &
      "EXTEST_TRAIN (1011111111111111111111111111111111010111111111011111111111101000)," &
      "SAMPLE       (1011111111111111111111111111111111010111111111111111111111111000)," &
      "PRELOAD      (1011111111111111111111111111111111010111111111111111111111111000)," &
      "CLAMP        (1011111111111111111111111111111111010111111111111111111111101111) " ;

   attribute INSTRUCTION_CAPTURE of Tsi382: entity is "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx01";
 
   attribute IDCODE_REGISTER of Tsi382: entity is
      "0010"             & -- version
      "0000001110000001" & -- part number
      "00010110011"      & -- manufacturer's identity
      "1";                   -- required by 1149.1
 
   attribute REGISTER_ACCESS of Tsi382: entity is
      "BOUNDARY     ( EXTEST_PULSE, EXTEST_TRAIN )," &
      "BOUNDARY     ( SAMPLE, PRELOAD )," &
      "BYPASS       ( CLAMP, BYPASS ) " ;


    --Boundary scan definition
    attribute BOUNDARY_LENGTH of Tsi382: entity is 149;

    attribute BOUNDARY_REGISTER of Tsi382: entity is 
    -- num  cell         port               function       safe     [ccell disval  rslt]
    "  148  (BC_2       , *                , control      , 0   )                          ,"&
    "  147  (LV_BC_7    , PCI_AD(31)       , bidir        , X    ,   148    , 0     , Z   ),"&
    "  146  (BC_2       , *                , control      , 0   )                          ,"&
    "  145  (LV_BC_7    , PCI_AD(30)       , bidir        , X    ,   146    , 0     , Z   ),"&
    "  144  (BC_2       , *                , control      , 0   )                          ,"&
    "  143  (LV_BC_7    , PCI_AD(29)       , bidir        , X    ,   144    , 0     , Z   ),"&
    "  142  (BC_2       , *                , control      , 0   )                          ,"&
    "  141  (LV_BC_7    , PCI_AD(28)       , bidir        , X    ,   142    , 0     , Z   ),"&
    "  140  (BC_2       , *                , control      , 0   )                          ,"&
    "  139  (LV_BC_7    , PCI_AD(27)       , bidir        , X    ,   140    , 0     , Z   ),"&
    "  138  (BC_2       , *                , control      , 0   )                          ,"&
    "  137  (LV_BC_7    , PCI_AD(26)       , bidir        , X    ,   138    , 0     , Z   ),"&
    "  136  (BC_2       , *                , control      , 0   )                          ,"&
    "  135  (LV_BC_7    , PCI_AD(25)       , bidir        , X    ,   136    , 0     , Z   ),"&
    "  134  (BC_2       , *                , control      , 0   )                          ,"&
    "  133  (LV_BC_7    , PCI_AD(24)       , bidir        , X    ,   134    , 0     , Z   ),"&
    "  132  (BC_2       , *                , control      , 0   )                          ,"&
    "  131  (LV_BC_7    , PCI_AD(23)       , bidir        , X    ,   132    , 0     , Z   ),"&
    "  130  (BC_2       , *                , control      , 0   )                          ,"&
    "  129  (LV_BC_7    , PCI_AD(22)       , bidir        , X    ,   130    , 0     , Z   ),"&
    "  128  (BC_2       , *                , control      , 0   )                          ,"&
    "  127  (LV_BC_7    , PCI_AD(21)       , bidir        , X    ,   128    , 0     , Z   ),"&
    "  126  (BC_2       , *                , control      , 0   )                          ,"&
    "  125  (LV_BC_7    , PCI_AD(20)       , bidir        , X    ,   126    , 0     , Z   ),"&
    "  124  (BC_2       , *                , control      , 0   )                          ,"&
    "  123  (LV_BC_7    , PCI_AD(19)       , bidir        , X    ,   124    , 0     , Z   ),"&
    "  122  (BC_2       , *                , control      , 0   )                          ,"&
    "  121  (LV_BC_7    , PCI_AD(18)       , bidir        , X    ,   122    , 0     , Z   ),"&
    "  120  (BC_2       , *                , control      , 0   )                          ,"&
    "  119  (LV_BC_7    , PCI_AD(17)       , bidir        , X    ,   120    , 0     , Z   ),"&
    "  118  (BC_2       , *                , control      , 0   )                          ,"&
    "  117  (LV_BC_7    , PCI_AD(16)       , bidir        , X    ,   118    , 0     , Z   ),"&
    "  116  (BC_2       , *                , control      , 0   )                          ,"&
    "  115  (LV_BC_7    , PCI_AD(15)       , bidir        , X    ,   116    , 0     , Z   ),"&
    "  114  (BC_2       , *                , control      , 0   )                          ,"&
    "  113  (LV_BC_7    , PCI_AD(14)       , bidir        , X    ,   114    , 0     , Z   ),"&
    "  112  (BC_2       , *                , control      , 0   )                          ,"&
    "  111  (LV_BC_7    , PCI_AD(13)       , bidir        , X    ,   112    , 0     , Z   ),"&
    "  110  (BC_2       , *                , control      , 0   )                          ,"&
    "  109  (LV_BC_7    , PCI_AD(12)       , bidir        , X    ,   110    , 0     , Z   ),"&
    "  108  (BC_2       , *                , control      , 0   )                          ,"&
    "  107  (LV_BC_7    , PCI_AD(11)       , bidir        , X    ,   108    , 0     , Z   ),"&
    "  106  (BC_2       , *                , control      , 0   )                          ,"&
    "  105  (LV_BC_7    , PCI_AD(10)       , bidir        , X    ,   106    , 0     , Z   ),"&
    "  104  (BC_2       , *                , control      , 0   )                          ,"&
    "  103  (LV_BC_7    , PCI_AD(9)        , bidir        , X    ,   104    , 0     , Z   ),"&
    "  102  (BC_2       , *                , control      , 0   )                          ,"&
    "  101  (LV_BC_7    , PCI_AD(8)        , bidir        , X    ,   102    , 0     , Z   ),"&
    "  100  (BC_2       , *                , control      , 0   )                          ,"&
    "  99   (LV_BC_7    , PCI_AD(7)        , bidir        , X    ,   100    , 0     , Z   ),"&
    "  98   (BC_2       , *                , control      , 0   )                          ,"&
    "  97   (LV_BC_7    , PCI_AD(6)        , bidir        , X    ,   98     , 0     , Z   ),"&
    "  96   (BC_2       , *                , control      , 0   )                          ,"&
    "  95   (LV_BC_7    , PCI_AD(5)        , bidir        , X    ,   96     , 0     , Z   ),"&
    "  94   (BC_2       , *                , control      , 0   )                          ,"&
    "  93   (LV_BC_7    , PCI_AD(4)        , bidir        , X    ,   94     , 0     , Z   ),"&
    "  92   (BC_2       , *                , control      , 0   )                          ,"&
    "  91   (LV_BC_7    , PCI_AD(3)        , bidir        , X    ,   92     , 0     , Z   ),"&
    "  90   (BC_2       , *                , control      , 0   )                          ,"&
    "  89   (LV_BC_7    , PCI_AD(2)        , bidir        , X    ,   90     , 0     , Z   ),"&
    "  88   (BC_2       , *                , control      , 0   )                          ,"&
    "  87   (LV_BC_7    , PCI_AD(1)        , bidir        , X    ,   88     , 0     , Z   ),"&
    "  86   (BC_2       , *                , control      , 0   )                          ,"&
    "  85   (LV_BC_7    , PCI_AD(0)        , bidir        , X    ,   86     , 0     , Z   ),"&
    "  84   (BC_2       , *                , control      , 0   )                          ,"&
    "  83   (LV_BC_7    , PCI_CBEn(3)      , bidir        , X    ,   84     , 0     , Z   ),"&
    "  82   (BC_2       , *                , control      , 0   )                          ,"&
    "  81   (LV_BC_7    , PCI_CBEn(2)      , bidir        , X    ,   82     , 0     , Z   ),"&
    "  80   (BC_2       , *                , control      , 0   )                          ,"&
    "  79   (LV_BC_7    , PCI_CBEn(1)      , bidir        , X    ,   80     , 0     , Z   ),"&
    "  78   (BC_2       , *                , control      , 0   )                          ,"&
    "  77   (LV_BC_7    , PCI_CBEn(0)      , bidir        , X    ,   78     , 0     , Z   ),"&
    "  76   (BC_2       , *                , control      , 0   )                          ,"&
    "  75   (LV_BC_7    , PCI_PMEn         , bidir        , X    ,   76     , 0     , Z   ),"&
    "  74   (BC_2       , *                , control      , 0   )                          ,"&
    "  73   (LV_BC_7    , PCI_GNTn(3)      , bidir        , X    ,   74     , 0     , Z   ),"&
    "  72   (BC_2       , *                , control      , 0   )                          ,"&
    "  71   (LV_BC_7    , PCI_GNTn(2)      , bidir        , X    ,   72     , 0     , Z   ),"&
    "  70   (BC_2       , *                , control      , 0   )                          ,"&
    "  69   (LV_BC_7    , PCI_GNTn(1)      , bidir        , X    ,   70     , 0     , Z   ),"&
    "  68   (BC_2       , *                , control      , 0   )                          ,"&
    "  67   (LV_BC_7    , PCI_GNTn(0)      , bidir        , X    ,   68     , 0     , Z   ),"&
    "  66   (BC_2       , *                , control      , 0   )                          ,"&
    "  65   (LV_BC_7    , PCI_REQn(3)      , bidir        , X    ,   66     , 0     , Z   ),"&
    "  64   (BC_2       , *                , control      , 0   )                          ,"&
    "  63   (LV_BC_7    , PCI_REQn(2)      , bidir        , X    ,   64     , 0     , Z   ),"&
    "  62   (BC_2       , *                , control      , 0   )                          ,"&
    "  61   (LV_BC_7    , PCI_REQn(1)      , bidir        , X    ,   62     , 0     , Z   ),"&
    "  60   (BC_2       , *                , control      , 0   )                          ,"&
    "  59   (LV_BC_7    , PCI_REQn(0)      , bidir        , X    ,   60     , 0     , Z   ),"&
    "  58   (BC_2       , *                , control      , 0   )                          ,"&
    "  57   (LV_BC_7    , PCI_RSTn         , bidir        , X    ,   58     , 0     , Z   ),"&
    "  56   (BC_4       , PCI_CLK          , clock        , X   )                          ,"&
    "  55   (BC_2       , *                , control      , 0   )                          ,"&
    "  54   (BC_2       , PCI_CLKO(4)      , output3      , X    ,   55     , 0     , Z   ),"&
    "  53   (BC_2       , *                , control      , 0   )                          ,"&
    "  52   (BC_2       , PCI_CLKO(3)      , output3      , X    ,   53     , 0     , Z   ),"&
    "  51   (BC_2       , *                , control      , 0   )                          ,"&
    "  50   (BC_2       , PCI_CLKO(2)      , output3      , X    ,   51     , 0     , Z   ),"&
    "  49   (BC_2       , *                , control      , 0   )                          ,"&
    "  48   (BC_2       , PCI_CLKO(1)      , output3      , X    ,   49     , 0     , Z   ),"&
    "  47   (BC_2       , *                , control      , 0   )                          ,"&
    "  46   (BC_2       , PCI_CLKO(0)      , output3      , X    ,   47     , 0     , Z   ),"&
    "  45   (BC_2       , PCI_INTCn        , input        , X   )                          ,"&
    "  44   (BC_2       , PCI_INTBn        , input        , X   )                          ,"&
    "  43   (BC_2       , PCI_INTAn        , input        , X   )                          ,"&
    "  42   (BC_2       , PCI_INTDn        , input        , X   )                          ,"&
    "  41   (BC_2       , PCIE_PERSTn      , input        , X   )                          ,"&
    "  40   (BC_1       , *                , control      , 0   )                          ,"&
    "  39   (AC_1       , PCIE_TXD_p       , output3      , X    ,   40     , 0     , Z   ),"&
    "  38   (BC_4       , PCIE_RXD_p       , observe_only , X   )                          ,"&
    "  37   (BC_4       , PCIE_RXD_n       , observe_only , X   )                          ,"&
    "  36   (BC_2       , *                , control      , 0   )                          ,"&
    "  35   (BC_2       , SR_CSn           , output3      , X    ,   36     , 0     , Z   ),"&
    "  34   (BC_2       , *                , control      , 0   )                          ,"&
    "  33   (BC_2       , SR_CLK           , output3      , X    ,   34     , 0     , Z   ),"&
    "  32   (BC_2       , SR_DOUT          , input        , X   )                          ,"&
    "  31   (BC_2       , *                , control      , 0   )                          ,"&
    "  30   (LV_BC_7    , SR_DIN           , bidir        , X    ,   31     , 0     , Z   ),"&
    "  29   (BC_2       , PCI_M66EN        , input        , X   )                          ,"&
    "  28   (BC_2       , *                , control      , 0   )                          ,"&
    "  27   (LV_BC_7    , PCI_SERRn        , bidir        , X    ,   28     , 0     , Z   ),"&
    "  26   (BC_2       , *                , control      , 0   )                          ,"&
    "  25   (LV_BC_7    , PCI_PAR          , bidir        , X    ,   26     , 0     , Z   ),"&
    "  24   (BC_2       , *                , control      , 0   )                          ,"&
    "  23   (LV_BC_7    , PCI_PERRn        , bidir        , X    ,   24     , 0     , Z   ),"&
    "  22   (BC_2       , *                , control      , 0   )                          ,"&
    "  21   (LV_BC_7    , PCI_LOCKn        , bidir        , X    ,   22     , 0     , Z   ),"&
    "  20   (BC_2       , *                , control      , 0   )                          ,"&
    "  19   (LV_BC_7    , PCI_STOPn        , bidir        , X    ,   20     , 0     , Z   ),"&
    "  18   (BC_2       , *                , control      , 0   )                          ,"&
    "  17   (LV_BC_7    , PCI_TRDYn        , bidir        , X    ,   18     , 0     , Z   ),"&
    "  16   (BC_2       , *                , control      , 0   )                          ,"&
    "  15   (LV_BC_7    , PCI_DEVSELn      , bidir        , X    ,   16     , 0     , Z   ),"&
    "  14   (BC_2       , *                , control      , 0   )                          ,"&
    "  13   (LV_BC_7    , PCI_IRDYn        , bidir        , X    ,   14     , 0     , Z   ),"&
    "  12   (BC_2       , *                , control      , 0   )                          ,"&
    "  11   (LV_BC_7    , PCI_FRAMEn       , bidir        , X    ,   12     , 0     , Z   ),"&
    "  10   (BC_2       , *                , control      , 0   )                          ,"&
    "  9    (LV_BC_7    , GPIO(3)          , bidir        , X    ,   10     , 0     , Z   ),"&
    "  8    (BC_2       , *                , control      , 0   )                          ,"&
    "  7    (LV_BC_7    , GPIO(2)          , bidir        , X    ,   8      , 0     , Z   ),"&
    "  6    (BC_2       , *                , control      , 0   )                          ,"&
    "  5    (LV_BC_7    , GPIO(1)          , bidir        , X    ,   6      , 0     , Z   ),"&
    "  4    (BC_2       , *                , control      , 0   )                          ,"&
    "  3    (LV_BC_7    , GPIO(0)          , bidir        , X    ,   4      , 0     , Z   ),"&
    "  2    (BC_2       , *                , internal     , X   )                          ,"&
    "  1    (BC_2       , *                , internal     , X   )                          ,"&
    "  0    (BC_2       , *                , internal     , X   )                           ";

    attribute AIO_COMPONENT_CONFORMANCE of Tsi382: entity is "STD_1149_6_2003";


    attribute AIO_Pin_Behavior of Tsi382: entity is 
        "PCIE_TXD_p;" &
        "PCIE_RXD_p[38]           : LP_Time=2.30e-07 HP_Time=7.00e-06";
end Tsi382;
-- VHDL package to be uploaded
--package LVS_BSCAN_CELLS is
--    use STD_1149_1_2001.all;
--        constant LV_BC_7: CELL_INFO;
--
--end LVS_BSCAN_CELLS;
--package body LVS_BSCAN_CELLS is
--    use STD_1149_1_2001.all;
--        constant LV_BC_7: CELL_INFO :=
--           ((BIDIR_IN, EXTEST,  PI),  (BIDIR_OUT, EXTEST,  PO),
--           (BIDIR_IN, SAMPLE,  PI),  (BIDIR_OUT, SAMPLE,  PI),
--           (BIDIR_IN, INTEST,  X),  (BIDIR_OUT, INTEST,  PI));
--
--end LVS_BSCAN_CELLS;