-- ***********************************************************************
-- BSDL file for design IDT82v2084
-- Created by Synopsys Version 1999.10 (Sep 02, 1999)
-- Designer:
-- Company: Integrated Devices Technolgy, Inc.
-- Date: Thu Aug 18 14:56:10 2005
-- ***********************************************************************
entity IDT82v2084 is
-- This section identifies the default device package selected.
generic (PHYSICAL_PIN_MAP: string:= "IDT82V2084PF");
-- This section declares all the ports in the design.
port (
IC : in bit;
INT_nMOT : in bit;
MCLK : in bit;
MCLKS : in bit;
P_nS : in bit;
RST : in bit;
SCLK : in bit;
SCLKE : in bit;
SDI_R_nW_nWR : in bit;
TCK : in bit;
TCLK1 : in bit;
TCLK2 : in bit;
TCLK3 : in bit;
TCLK4 : in bit;
TDI : in bit;
TDN1 : in bit;
TDN2 : in bit;
TDN3 : in bit;
TDN4 : in bit;
TDP1 : in bit;
TDP2 : in bit;
TDP3 : in bit;
TDP4 : in bit;
THZ : in bit;
TMS : in bit;
TRST : in bit;
nCS : in bit;
nDS_nRD : in bit;
A : in bit_vector (0 to 7);
D : inout bit_vector (0 to 7);
INT : out bit;
SDO : out bit;
TDO : out bit;
LOS1 : buffer bit;
LOS2 : buffer bit;
LOS3 : buffer bit;
LOS4 : buffer bit;
RCLK1 : buffer bit;
RCLK2 : buffer bit;
RCLK3 : buffer bit;
RCLK4 : buffer bit;
RDN1 : buffer bit;
RDN2 : buffer bit;
RDN3 : buffer bit;
RDN4 : buffer bit;
RDP1 : buffer bit;
RDP2 : buffer bit;
RDP3 : buffer bit;
RDP4 : buffer bit;
GNDA : linkage bit_vector (1 to 2);
GNDD : linkage bit_vector (1 to 2);
GNDIO : linkage bit_vector (1 to 5);
GNDR1 : linkage bit_vector (1 to 1);
GNDR2 : linkage bit_vector (1 to 1);
GNDR3 : linkage bit_vector (1 to 1);
GNDR4 : linkage bit_vector (1 to 1);
GNDT1 : linkage bit_vector (1 to 2);
GNDT2 : linkage bit_vector (1 to 2);
GNDT3 : linkage bit_vector (1 to 2);
GNDT4 : linkage bit_vector (1 to 2);
NC : linkage bit_vector (1 to 4);
VDDA : linkage bit_vector (1 to 2);
VDDD : linkage bit_vector (1 to 2);
VDDIO : linkage bit_vector (1 to 5);
VDDR1 : linkage bit_vector (1 to 1);
VDDR2 : linkage bit_vector (1 to 1);
VDDR3 : linkage bit_vector (1 to 1);
VDDR4 : linkage bit_vector (1 to 1);
VDDT1 : linkage bit_vector (1 to 2);
VDDT2 : linkage bit_vector (1 to 2);
VDDT3 : linkage bit_vector (1 to 2);
VDDT4 : linkage bit_vector (1 to 2)
);
use STD_1149_1_1994.all;
attribute COMPONENT_CONFORMANCE of IDT82v2084: entity is "STD_1149_1_1993";
attribute PIN_MAP of IDT82v2084: entity is PHYSICAL_PIN_MAP;
-- This section specifies the pin map for each port. This information
-- is extracted from the port-to-pin map file that was read in using
-- the "read_pin_map" command.
constant IDT82V2084PF: PIN_MAP_STRING :=
"IC : 7," &
"INT_nMOT : 6," &
"MCLK : 10," &
"MCLKS : 40," &
"P_nS : 8," &
"RST : 38," &
"SCLK : 33," &
"SCLKE : 5," &
"SDI_R_nW_nWR : 35," &
"TCK : 127," &
"TCLK1 : 97," &
"TCLK2 : 91," &
"TCLK3 : 82," &
"TCLK4 : 75," &
"TDI : 125," &
"TDN1 : 95," &
"TDN2 : 89," &
"TDN3 : 79," &
"TDN4 : 73," &
"TDP1 : 96," &
"TDP2 : 90," &
"TDP3 : 80," &
"TDP4 : 74," &
"THZ : 4," &
"TMS : 124," &
"TRST : 123," &
"nCS : 32," &
"nDS_nRD : 34," &
"A : (31, 30, 29, 28, 27, 26, 25, 24)," &
"D : (21, 20, 19, 18, 17, 16, 15, 14)," &
"INT : 37," &
"SDO : 36," &
"TDO : 126," &
"LOS1 : 128," &
"LOS2 : 1," &
"LOS3 : 2," &
"LOS4 : 3," &
"RCLK1 : 94," &
"RCLK2 : 88," &
"RCLK3 : 78," &
"RCLK4 : 72," &
"RDN1 : 92," &
"RDN2 : 86," &
"RDN3 : 76," &
"RDN4 : 70," &
"RDP1 : 93," &
"RDP2 : 87," &
"RDP3 : 77," &
"RDP4 : 71," &
"GNDA : (41, 122)," &
"GNDD : (11, 84)," &
"GNDIO : (12, 23, 69, 83, 98)," &
"GNDR1 : (107)," &
"GNDR2 : (117)," &
"GNDR3 : (51)," &
"GNDR4 : (61)," &
"GNDT1 : (105, 106)," &
"GNDT2 : (115, 116)," &
"GNDT3 : (49, 50)," &
"GNDT4 : (59, 60)," &
"NC : (65, 66, 67, 100)," &
"VDDA : (44, 121)," &
"VDDD : (9, 85)," &
"VDDIO : (13, 22, 68, 81, 99)," &
"VDDR1 : (110)," &
"VDDR2 : (120)," &
"VDDR3 : (54)," &
"VDDR4 : (64)," &
"VDDT1 : (101, 102)," &
"VDDT2 : (111, 112)," &
"VDDT3 : (45, 46)," &
"VDDT4 : (55, 56)";
-- This section specifies the TAP ports.
-- For the TAP TCK port, the parameters in the brackets are:
-- First Field : Maximum TCK frequency.
-- Second Field: Allowable states TCK may be stopped in.
attribute TAP_SCAN_CLOCK of TCK : signal is (10.0e6, BOTH);
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_RESET of TRST: signal is true;
-- Specifies the number of bits in the instruction register.
attribute INSTRUCTION_LENGTH of IDT82v2084: entity is 3;
-- Specifies the boundary-scan instructions implemented in the
-- design and their opcodes.
attribute INSTRUCTION_OPCODE of IDT82v2084: entity is
"BYPASS (111)," &
"EXTEST (000)," &
"SAMPLE (010, 011, 101, 110)," &
"IDCODE (001)," &
"USER1 (100)";
-- Specifies the bit pattern that is loaded into the instruction
-- register when the TAP controller passes through the Capture-IR
-- state. The standard mandates that the two LSBs must be "01".
-- The remaining bits are design specific.
attribute INSTRUCTION_CAPTURE of IDT82v2084: entity is "001";
-- Specifies the bit pattern that is loaded into the DEVICE_ID
-- register during the IDCODE instruction when the TAP controller
-- passes through the Capture-DR state.
attribute IDCODE_REGISTER of IDT82v2084: entity is
"0000" & -- 4-bit version number
"0000010011010011" & -- 16-bit part number
"00010110011" & -- 11-bit identity of the manufacturer
"1"; -- Required by IEEE Std 1149.1
-- This section specifies the test data register placed between TDI
-- and TDO for each implemented instruction.
attribute REGISTER_ACCESS of IDT82v2084: entity is
"BYPASS (BYPASS)," &
"BOUNDARY (EXTEST, SAMPLE)," &
"DEVICE_ID (IDCODE)," &
"UTDR1[2] (USER1)";
-- Specifies the length of the boundary scan register.
attribute BOUNDARY_LENGTH of IDT82v2084: entity is 93;
-- The following list specifies the characteristics of each cell
-- in the boundary scan register from TDI to TDO.
-- The following is a description of the label fields:
-- num : Is the cell number.
-- cell : Is the cell type as defined by the standard.
-- port : Is the design port name. Control cells do not
-- have a port name.
-- function: Is the function of the cell as defined by the
-- standard. Is one of input, output2, output3,
-- bidir, control or controlr.
-- safe : Specifies the value that the BSR cell should be
-- loaded with for safe operation when the software
-- might otherwise choose a random value.
-- ccell : The control cell number. Specifies the control
-- cell that drives the output enable for this port.
-- disval : Specifies the value that is loaded into the
-- control cell to disable the output enable for
-- the corresponding port.
-- rslt : Resulting state. Shows the state of the driver
-- when it is disabled.
attribute BOUNDARY_REGISTER of IDT82v2084: entity is
--
-- num cell port function safe [ccell disval rslt]
--
"92 (BC_1, LOS1, output2, X), " &
"91 (BC_0, *, internal, X), " &
"90 (BC_1, LOS2, output2, X), " &
"89 (BC_0, *, internal, X), " &
"88 (BC_1, LOS3, output2, X), " &
"87 (BC_0, *, internal, X), " &
"86 (BC_1, LOS4, output2, X), " &
"85 (BC_0, *, internal, X), " &
"84 (BC_3, THZ, input, X), " &
"83 (BC_3, SCLKE, input, X), " &
"82 (BC_3, INT_nMOT, input, X), " &
"81 (BC_3, IC, input, X), " &
"80 (BC_3, P_nS, input, X), " &
"79 (BC_3, MCLK, input, X), " &
"78 (BC_7, D(7), bidir, X, 70, 1, Z), " &
"77 (BC_7, D(6), bidir, X, 70, 1, Z), " &
"76 (BC_7, D(5), bidir, X, 70, 1, Z), " &
"75 (BC_7, D(4), bidir, X, 70, 1, Z), " &
"74 (BC_7, D(3), bidir, X, 70, 1, Z), " &
"73 (BC_7, D(2), bidir, X, 70, 1, Z), " &
"72 (BC_7, D(1), bidir, X, 70, 1, Z), " &
"71 (BC_7, D(0), bidir, X, 70, 1, Z), " &
"70 (BC_1, *, control, 1), " &
"69 (BC_3, A(7), input, X), " &
"68 (BC_3, A(6), input, X), " &
"67 (BC_3, A(5), input, X), " &
"66 (BC_3, A(4), input, X), " &
"65 (BC_3, A(3), input, X), " &
"64 (BC_3, A(2), input, X), " &
"63 (BC_3, A(1), input, X), " &
"62 (BC_3, A(0), input, X), " &
"61 (BC_3, nCS, input, X), " &
"60 (BC_3, SCLK, input, X), " &
"59 (BC_3, nDS_nRD, input, X), " &
"58 (BC_3, SDI_R_nW_nWR, input, X), " &
"57 (BC_1, SDO, output3, X, 56, 1, Z), " &
"56 (BC_1, *, control, 1), " &
"55 (BC_1, INT, output3, X, 54, 1, Z), " &
"54 (BC_1, *, control, 1), " &
"53 (BC_3, RST, input, X), " &
"52 (BC_0, *, internal, X), " &
"51 (BC_0, *, internal, X), " &
"50 (BC_0, *, internal, X), " &
"49 (BC_0, *, internal, X), " &
"48 (BC_3, MCLKS, input, X), " &
"47 (BC_0, *, internal, X), " &
"46 (BC_0, *, internal, X), " &
"45 (BC_0, *, internal, X), " &
"44 (BC_0, *, internal, X), " &
"43 (BC_0, *, internal, X), " &
"42 (BC_0, *, internal, X), " &
"41 (BC_1, RDN4, output2, X), " &
"40 (BC_1, RDP4, output2, X), " &
"39 (BC_1, RCLK4, output2, X), " &
"38 (BC_3, TDN4, input, X), " &
"37 (BC_3, TDP4, input, X), " &
"36 (BC_3, TCLK4, input, X), " &
"35 (BC_0, *, internal, X), " &
"34 (BC_0, *, internal, X), " &
"33 (BC_0, *, internal, X), " &
"32 (BC_0, *, internal, X), " &
"31 (BC_0, *, internal, X), " &
"30 (BC_0, *, internal, X), " &
"29 (BC_1, RDN3, output2, X), " &
"28 (BC_1, RDP3, output2, X), " &
"27 (BC_1, RCLK3, output2, X), " &
"26 (BC_3, TDN3, input, X), " &
"25 (BC_3, TDP3, input, X), " &
"24 (BC_3, TCLK3, input, X), " &
"23 (BC_0, *, internal, X), " &
"22 (BC_0, *, internal, X), " &
"21 (BC_0, *, internal, X), " &
"20 (BC_0, *, internal, X), " &
"19 (BC_0, *, internal, X), " &
"18 (BC_0, *, internal, X), " &
"17 (BC_1, RDN2, output2, X), " &
"16 (BC_1, RDP2, output2, X), " &
"15 (BC_1, RCLK2, output2, X), " &
"14 (BC_3, TDN2, input, X), " &
"13 (BC_3, TDP2, input, X), " &
"12 (BC_3, TCLK2, input, X), " &
"11 (BC_0, *, internal, X), " &
"10 (BC_0, *, internal, X), " &
"9 (BC_0, *, internal, X), " &
"8 (BC_0, *, internal, X), " &
"7 (BC_0, *, internal, X), " &
"6 (BC_0, *, internal, X), " &
"5 (BC_1, RDN1, output2, X), " &
"4 (BC_1, RDP1, output2, X), " &
"3 (BC_1, RCLK1, output2, X), " &
"2 (BC_3, TDN1, input, X), " &
"1 (BC_3, TDP1, input, X), " &
"0 (BC_3, TCLK1, input, X) ";
end IDT82v2084;