BSDL Files Library for JTAG

The only free public library that contains thousands of BSDL (Boundary Scan Description Language) models to use with BScan/JTAG tools

BSDL model: peb383

-- ***************************************************************
--      Company:  Integrated Device Technology, Inc.
--
--      Document number: PEB383_BSDL_QFN_132_02
--
--      Title: BSDL file of PEB383
--
--      Release status: formal issue
--      Security level: client use
--      BSDL Version 2001
--      Released by  :       
--      Revision History:
--              Jul 28, 2011:   JTAD ID rev changed to 4'b0001 for design version ZD
--     
--              
--      BSDL Syntax Checker ->  passed Jul 28, 2011 
--     
--              
--           
-- ***************************************************************
--
-- Generated by boundaryScanGenerate 4.2b-Build20051027.004 on 09/29/09 13:27:55
-- BSDL Version 2001
-- VHDL package LVS_BSCAN_CELLS is appended at the end of this file. This LVS_BSCAN_CELLS VHDL file need
-- to be uploaded when compiling this BSDL.


entity peb383 is 
    generic (PHYSICAL_PIN_MAP : string := "QFN_132_65");

    port (
        -- Port List
        PCIE_TXD_p           : out      bit;
        PCIE_TXD_n           : out      bit;
        PCIE_RXD_p           : in       bit;
        PCIE_RXD_n           : in       bit;
        PCI_AD               : inout    bit_vector( 31 downto 0 );
        PCI_CBEn             : inout    bit_vector( 3 downto 0 );
        PCI_PAR              : inout    bit;
        PCI_SERRn            : inout    bit;
        PCI_PERRn            : inout    bit;
        PCI_LOCKn            : inout    bit;
        PCI_STOPn            : inout    bit;
        PCI_DEVSELn          : inout    bit;
        PCI_TRDYn            : inout    bit;
        PCI_IRDYn            : inout    bit;
        PCI_FRAMEn           : inout    bit;
        PCI_M66EN            : inout    bit;
        PCI_REQn             : inout    bit_vector( 3 downto 0 );
        PCI_GNTn             : inout    bit_vector( 3 downto 0 );
        PCI_CLK              : in       bit;
        PCI_RSTn             : inout    bit;
        JTAG_TCK             : in       bit;
        JTAG_TRSTn           : in       bit;
        JTAG_TMS             : in       bit;
        JTAG_TDO             : out      bit;
        JTAG_TDI             : in       bit;
        PCI_PMEn             : inout    bit;
        PCI_INTAn            : inout    bit;
        PCI_INTBn            : inout    bit;
        PCI_INTCn            : inout    bit;
        PCI_INTDn            : inout    bit;
        PCI_CLKO             : inout    bit_vector( 4 downto 0 );
        SR_DIN               : inout    bit;
        SR_DOUT              : inout    bit;
        SR_CLK               : out      bit;
        SR_CSn               : inout    bit;
        TEST_BCE             : linkage  bit;
        PCIE_PERSTn          : in       bit;
        PCIE_REFCLK_p        : linkage  bit;
        PCIE_REFCLK_n        : linkage  bit;
        PWRUP_PLL_BYPASS     : linkage  bit;
        PCIE_REXT            : linkage  bit;
        VDDA_PLL             : linkage  bit;
        VSSA_PLL             : linkage  bit;
        VDDA_PCIE            : linkage  bit_vector( 1 downto 0 );
        VDD_PCIE             : linkage  bit_vector( 1 downto 0 );
        VIO_PCI              : linkage  bit_vector( 2 downto 0 );
        VDD_PCI              : linkage  bit_vector( 7 downto 0 );
        VDD                  : linkage  bit_vector( 5 downto 0 );
        VSS                  : linkage  bit_vector( 6 downto 0 ) );

    use STD_1149_1_2001.all;
    use STD_1149_6_2003.all;
    use LVS_BSCAN_CELLS.all;

    attribute COMPONENT_CONFORMANCE of peb383: entity is "STD_1149_1_2001";

    --Pin mappings

    attribute PIN_MAP of peb383: entity is PHYSICAL_PIN_MAP;

    constant QFN_132_65: PIN_MAP_STRING := 
    "PCIE_TXD_p           : A69    , " &
    "PCIE_TXD_n           : B59    , " &
    "PCIE_RXD_p           : A68    , " &
    "PCIE_RXD_n           : B57    , " &
    "PCI_AD               :(A40   , " &  -- PCI_AD[31]
                           "B31   , " &  -- PCI_AD[30]
                           "B30   , " &  -- PCI_AD[29]
                           "A34   , " &  -- PCI_AD[28]
                           "A33   , " &  -- PCI_AD[27]
                           "B28   , " &  -- PCI_AD[26]
                           "A32   , " &  -- PCI_AD[25]
                           "B27   , " &  -- PCI_AD[24]
                           "B26   , " &  -- PCI_AD[23]
                           "A30   , " &  -- PCI_AD[22]
                           "B25   , " &  -- PCI_AD[21]
                           "A29   , " &  -- PCI_AD[20]
                           "B24   , " &  -- PCI_AD[19]
                           "B22   , " &  -- PCI_AD[18]
                           "A26   , " &  -- PCI_AD[17]
                           "B21   , " &  -- PCI_AD[16]
                           "B12   , " &  -- PCI_AD[15]
                           "A13   , " &  -- PCI_AD[14]
                           "B10   , " &  -- PCI_AD[13]
                           "A11   , " &  -- PCI_AD[12]
                           "B9   , " &  -- PCI_AD[11]
                           "A10   , " &  -- PCI_AD[10]
                           "B8   , " &  -- PCI_AD[9]
                           "A9   , " &  -- PCI_AD[8]
                           "A8   , " &  -- PCI_AD[7]
                           "B6   , " &  -- PCI_AD[6]
                           "A7   , " &  -- PCI_AD[5]
                           "A5    , " &  -- PCI_AD[4]
                           "B3    , " &  -- PCI_AD[3]
                           "A4    , " &  -- PCI_AD[2]
                           "B2    , " &  -- PCI_AD[1]
                           "A3   ), " &  -- PCI_AD[0]
    "PCI_CBEn             :(A31   , " &  -- PCI_CBEn[3]
                           "B20   , " &  -- PCI_CBEn[2]
                           "A14   , " &  -- PCI_CBEn[1]
                           "B7  ), " &  -- PCI_CBEn[0]
    "PCI_PAR              : B13   , " &
    "PCI_SERRn            : A16   , " &
    "PCI_PERRn            : B14   , " &
    "PCI_LOCKn            : B15   , " &
    "PCI_STOPn            : B16   , " &
    "PCI_DEVSELn          : B17   , " &
    "PCI_TRDYn            : A22   , " &
    "PCI_IRDYn            : B18   , " &
    "PCI_FRAMEn           : A23   , " &
    "PCI_M66EN            : A25   , " &
    "PCI_REQn             :(A42   , " &  -- PCI_REQn[3]
                           "B33   , " &  -- PCI_REQn[2]
                           "A41   , " &  -- PCI_REQn[1]
                           "B32  ), " &  -- PCI_REQn[0]
    "PCI_GNTn             :(A45   , " &  -- PCI_GNTn[3]
                           "B36   , " &  -- PCI_GNTn[2]
                           "A43   , " &  -- PCI_GNTn[1]
                           "B35  ), " &  -- PCI_GNTn[0]
    "PCI_CLK              : B38   , " &
    "PCI_RSTn             : A46   , " &
    "JTAG_TCK             : B39   , " &
    "JTAG_TRSTn           : A47   , " &
    "JTAG_TMS             : B40   , " &
    "JTAG_TDO             : A48   , " &
    "JTAG_TDI             : A49   , " &
    "PCI_PMEn             : B42   , " &
    "PCI_INTAn            : B43   , " &
    "PCI_INTBn            : A51   , " &
    "PCI_INTCn            : B44   , " &
    "PCI_INTDn            : B45   , " &
    "PCI_CLKO             :(A52   , " &  -- PCI_CLKO[4]
                           "B46   , " &  -- PCI_CLKO[3]
                           "A57   , " &  -- PCI_CLKO[2]
                           "A58   , " &  -- PCI_CLKO[1]
                           "B48  ), " &  -- PCI_CLKO[0]
    "SR_DIN               : A59   , " &
    "SR_DOUT              : A60   , " &
    "SR_CLK               : B49   , " &
    "SR_CSn               : A61   , " &
    "TEST_BCE             : B51   , " &
    "PCIE_PERSTn          : A63   , " &
    "PCIE_REFCLK_p        : B55   , " &
    "PCIE_REFCLK_n        : A66   , " &
    "PWRUP_PLL_BYPASS     : B52   , " &
    "PCIE_REXT            : A67   , " &
    "VDDA_PLL             : B53   , " &
    "VSSA_PLL             : A64   , " &
    "VIO_PCI               :(B34  , " &  -- VIO_PCI[2]
                           "A28  , " &  -- VIO_PCI[1]
                           "A12 ), " &  -- VIO_PCI[0]

    "VDD_PCI               :(B50  , " &  -- VDD_PCI[7]
                           "B11  , " &  -- VDD_PCI[6]
                           "B4  , " &  -- VDD_PCI[5]
                           "A50  , " &  -- VDD_PCI[4]
                           "A44  , " &  -- VDD_PCI[3]
                           "A39  , " &  -- VDD_PCI[2]
                           "A27  , " &  -- VDD_PCI[1]
                           "A21 ), " &  -- VDD_PCI[0]

    "VDD_PCIE               :(B60  , " &  -- VDD_PCIE[1]
                           "B54 ), " &  -- VDD_PCIE[0]

    "VDDA_PCIE               :(A70  , " &  -- VDDA_PCIE[1]
                           "A65 ), " &  -- VDDA_PCIE[0]

    "VDD               :(B47  , " &  -- VDD[5]
                           "B41  , " &  -- VDD[4]
                           "B29  , " &  -- VDD[3]
                           "B23  , " &  -- VDD[2]
                           "B19  , " &  -- VDD[1]
                           "A15 ), " &  -- VDD[0]

    "VSS               :(A62  , " &  -- VSS[6]	-- TEST_ON
                           "B58  , " &  -- VSS[5]
                           "B56  , " &  -- VSS[4]
                           "B37  , " &  -- VSS[3]
                           "B5  , " &  -- VSS[2]
                           "B1  , " &  -- VSS[1]
                           "A24 ) " ;  -- VSS[0]


    attribute PORT_GROUPING of peb383 : entity is 
        "Differential_Current ( (PCIE_TXD_p, PCIE_TXD_n), " &
                                "(PCIE_RXD_p, PCIE_RXD_n)) " ;
 
 
 
   attribute TAP_SCAN_RESET of JTAG_TRSTn                   : signal is true;
   attribute TAP_SCAN_IN    of JTAG_TDI                     : signal is true;
   attribute TAP_SCAN_MODE  of JTAG_TMS                     : signal is true;
   attribute TAP_SCAN_OUT   of JTAG_TDO                     : signal is true;
   attribute TAP_SCAN_CLOCK of JTAG_TCK                     : signal is (1.0000000000000000000e+07, BOTH);

 
 
 
   attribute INSTRUCTION_LENGTH of peb383: entity is 64;
 
   attribute INSTRUCTION_OPCODE of peb383: entity is
      "IDCODE       (1111111111111111111111111111111111111111111111111111111111111110)," &
      "BYPASS       (0000000000000000000000000000000000000000000000000000000000000000, 1111111111111111111111111111111111111111111111111111111111111111)," &
      "EXTEST       (1111111111111111111111111111111111111111111111111111111111101000)," &
      "EXTEST_PULSE (1111111111111111111111111111111111111111111111101111111111101000)," &
      "EXTEST_TRAIN (1111111111111111111111111111111111111111111111011111111111101000)," &
      "SAMPLE       (1111111111111111111111111111111111111111111111111111111111111000)," &
      "PRELOAD      (1111111111111111111111111111111111111111111111111111111111111000)," &
      "HIGHZ        (1111111111111111111111111111111111111111111111111111111111001111)," &
      "CLAMP        (1111111111111111111111111111111111111111111111111111111111101111) " ;
 
   attribute INSTRUCTION_CAPTURE of peb383: entity is "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx01";
 
   attribute IDCODE_REGISTER of peb383: entity is
      "0001"             & -- version
      "0000001110000011" & -- part number
      "00010110011"      & -- manufacturer's identity
      "1";                   -- required by 1149.1
 
   attribute REGISTER_ACCESS of peb383: entity is
      "BOUNDARY     ( EXTEST_PULSE, EXTEST_TRAIN )," &
      "BOUNDARY     ( SAMPLE, PRELOAD )," &
      "BYPASS       ( HIGHZ, CLAMP, BYPASS ) " ;


    --Boundary scan definition
    attribute BOUNDARY_LENGTH of peb383: entity is 144;

    attribute BOUNDARY_REGISTER of peb383: entity is 
    -- num  cell         port               function       safe     [ccell disval  rslt]
    "  143  (BC_1       , *                , control      , 0   )                          ,"&
    "  142  (AC_1       , PCIE_TXD_p       , output3      , X    ,   143    , 0     , Z   ),"&
    "  141  (BC_4       , PCIE_RXD_p       , observe_only , X   )                          ,"&
    "  140  (BC_4       , PCIE_RXD_n       , observe_only , X   )                          ,"&
    "  139  (BC_2       , *                , control      , 1   )                          ,"&
    "  138  (LV_BC_7    , PCI_AD(0)        , bidir        , X    ,   139    , 1     , Z   ),"&
    "  137  (BC_2       , *                , control      , 1   )                          ,"&
    "  136  (LV_BC_7    , PCI_AD(1)        , bidir        , X    ,   137    , 1     , Z   ),"&
    "  135  (BC_2       , *                , control      , 1   )                          ,"&
    "  134  (LV_BC_7    , PCI_AD(2)        , bidir        , X    ,   135    , 1     , Z   ),"&
    "  133  (BC_2       , *                , control      , 1   )                          ,"&
    "  132  (LV_BC_7    , PCI_AD(3)        , bidir        , X    ,   133    , 1     , Z   ),"&
    "  131  (BC_2       , *                , control      , 1   )                          ,"&
    "  130  (LV_BC_7    , PCI_AD(4)        , bidir        , X    ,   131    , 1     , Z   ),"&
    "  129  (BC_2       , *                , control      , 1   )                          ,"&
    "  128  (LV_BC_7    , PCI_AD(5)        , bidir        , X    ,   129    , 1     , Z   ),"&
    "  127  (BC_2       , *                , control      , 1   )                          ,"&
    "  126  (LV_BC_7    , PCI_AD(6)        , bidir        , X    ,   127    , 1     , Z   ),"&
    "  125  (BC_2       , *                , control      , 1   )                          ,"&
    "  124  (LV_BC_7    , PCI_AD(7)        , bidir        , X    ,   125    , 1     , Z   ),"&
    "  123  (BC_2       , *                , control      , 1   )                          ,"&
    "  122  (LV_BC_7    , PCI_CBEn(0)      , bidir        , X    ,   123    , 1     , Z   ),"&
    "  121  (BC_2       , *                , control      , 1   )                          ,"&
    "  120  (LV_BC_7    , PCI_AD(8)        , bidir        , X    ,   121    , 1     , Z   ),"&
    "  119  (BC_2       , *                , control      , 1   )                          ,"&
    "  118  (LV_BC_7    , PCI_AD(9)        , bidir        , X    ,   119    , 1     , Z   ),"&
    "  117  (BC_2       , *                , control      , 1   )                          ,"&
    "  116  (LV_BC_7    , PCI_AD(10)       , bidir        , X    ,   117    , 1     , Z   ),"&
    "  115  (BC_2       , *                , control      , 1   )                          ,"&
    "  114  (LV_BC_7    , PCI_AD(11)       , bidir        , X    ,   115    , 1     , Z   ),"&
    "  113  (BC_2       , *                , control      , 1   )                          ,"&
    "  112  (LV_BC_7    , PCI_AD(12)       , bidir        , X    ,   113    , 1     , Z   ),"&
    "  111  (BC_2       , *                , control      , 1   )                          ,"&
    "  110  (LV_BC_7    , PCI_AD(13)       , bidir        , X    ,   111    , 1     , Z   ),"&
    "  109  (BC_2       , *                , control      , 1   )                          ,"&
    "  108  (LV_BC_7    , PCI_AD(14)       , bidir        , X    ,   109    , 1     , Z   ),"&
    "  107  (BC_2       , *                , control      , 1   )                          ,"&
    "  106  (LV_BC_7    , PCI_AD(15)       , bidir        , X    ,   107    , 1     , Z   ),"&
    "  105  (BC_2       , *                , control      , 1   )                          ,"&
    "  104  (LV_BC_7    , PCI_CBEn(1)      , bidir        , X    ,   105    , 1     , Z   ),"&
    "  103  (BC_2       , *                , control      , 1   )                          ,"&
    "  102  (LV_BC_7    , PCI_PAR          , bidir        , X    ,   103    , 1     , Z   ),"&
    "  101  (BC_2       , *                , control      , 1   )                          ,"&
    "  100  (LV_BC_7    , PCI_SERRn        , bidir        , X    ,   101    , 1     , Z   ),"&
    "  99   (BC_2       , *                , control      , 1   )                          ,"&
    "  98   (LV_BC_7    , PCI_PERRn        , bidir        , X    ,   99     , 1     , Z   ),"&
    "  97   (BC_2       , *                , control      , 1   )                          ,"&
    "  96   (LV_BC_7    , PCI_LOCKn        , bidir        , X    ,   97     , 1     , Z   ),"&
    "  95   (BC_2       , *                , control      , 1   )                          ,"&
    "  94   (LV_BC_7    , PCI_STOPn        , bidir        , X    ,   95     , 1     , Z   ),"&
    "  93   (BC_2       , *                , control      , 1   )                          ,"&
    "  92   (LV_BC_7    , PCI_DEVSELn      , bidir        , X    ,   93     , 1     , Z   ),"&
    "  91   (BC_2       , *                , control      , 1   )                          ,"&
    "  90   (LV_BC_7    , PCI_TRDYn        , bidir        , X    ,   91     , 1     , Z   ),"&
    "  89   (BC_2       , *                , control      , 1   )                          ,"&
    "  88   (LV_BC_7    , PCI_IRDYn        , bidir        , X    ,   89     , 1     , Z   ),"&
    "  87   (BC_2       , *                , control      , 1   )                          ,"&
    "  86   (LV_BC_7    , PCI_FRAMEn       , bidir        , X    ,   87     , 1     , Z   ),"&
    "  85   (BC_2       , *                , control      , 1   )                          ,"&
    "  84   (LV_BC_7    , PCI_CBEn(2)      , bidir        , X    ,   85     , 1     , Z   ),"&
    "  83   (BC_2       , *                , control      , 1   )                          ,"&
    "  82   (LV_BC_7    , PCI_M66EN        , bidir        , X    ,   83     , 1     , Z   ),"&
    "  81   (BC_2       , *                , control      , 1   )                          ,"&
    "  80   (LV_BC_7    , PCI_AD(16)       , bidir        , X    ,   81     , 1     , Z   ),"&
    "  79   (BC_2       , *                , control      , 1   )                          ,"&
    "  78   (LV_BC_7    , PCI_AD(17)       , bidir        , X    ,   79     , 1     , Z   ),"&
    "  77   (BC_2       , *                , control      , 1   )                          ,"&
    "  76   (LV_BC_7    , PCI_AD(18)       , bidir        , X    ,   77     , 1     , Z   ),"&
    "  75   (BC_2       , *                , control      , 1   )                          ,"&
    "  74   (LV_BC_7    , PCI_AD(19)       , bidir        , X    ,   75     , 1     , Z   ),"&
    "  73   (BC_2       , *                , control      , 1   )                          ,"&
    "  72   (LV_BC_7    , PCI_AD(20)       , bidir        , X    ,   73     , 1     , Z   ),"&
    "  71   (BC_2       , *                , control      , 1   )                          ,"&
    "  70   (LV_BC_7    , PCI_AD(21)       , bidir        , X    ,   71     , 1     , Z   ),"&
    "  69   (BC_2       , *                , control      , 1   )                          ,"&
    "  68   (LV_BC_7    , PCI_AD(22)       , bidir        , X    ,   69     , 1     , Z   ),"&
    "  67   (BC_2       , *                , control      , 1   )                          ,"&
    "  66   (LV_BC_7    , PCI_AD(23)       , bidir        , X    ,   67     , 1     , Z   ),"&
    "  65   (BC_2       , *                , control      , 1   )                          ,"&
    "  64   (LV_BC_7    , PCI_CBEn(3)      , bidir        , X    ,   65     , 1     , Z   ),"&
    "  63   (BC_2       , *                , control      , 1   )                          ,"&
    "  62   (LV_BC_7    , PCI_AD(24)       , bidir        , X    ,   63     , 1     , Z   ),"&
    "  61   (BC_2       , *                , control      , 1   )                          ,"&
    "  60   (LV_BC_7    , PCI_AD(25)       , bidir        , X    ,   61     , 1     , Z   ),"&
    "  59   (BC_2       , *                , control      , 1   )                          ,"&
    "  58   (LV_BC_7    , PCI_AD(26)       , bidir        , X    ,   59     , 1     , Z   ),"&
    "  57   (BC_2       , *                , control      , 1   )                          ,"&
    "  56   (LV_BC_7    , PCI_AD(27)       , bidir        , X    ,   57     , 1     , Z   ),"&
    "  55   (BC_2       , *                , control      , 1   )                          ,"&
    "  54   (LV_BC_7    , PCI_AD(28)       , bidir        , X    ,   55     , 1     , Z   ),"&
    "  53   (BC_2       , *                , control      , 1   )                          ,"&
    "  52   (LV_BC_7    , PCI_AD(29)       , bidir        , X    ,   53     , 1     , Z   ),"&
    "  51   (BC_2       , *                , control      , 1   )                          ,"&
    "  50   (LV_BC_7    , PCI_AD(30)       , bidir        , X    ,   51     , 1     , Z   ),"&
    "  49   (BC_2       , *                , control      , 1   )                          ,"&
    "  48   (LV_BC_7    , PCI_AD(31)       , bidir        , X    ,   49     , 1     , Z   ),"&
    "  47   (BC_2       , *                , control      , 1   )                          ,"&
    "  46   (LV_BC_7    , PCI_REQn(0)      , bidir        , X    ,   47     , 1     , Z   ),"&
    "  45   (BC_2       , *                , control      , 1   )                          ,"&
    "  44   (LV_BC_7    , PCI_REQn(1)      , bidir        , X    ,   45     , 1     , Z   ),"&
    "  43   (BC_2       , *                , control      , 1   )                          ,"&
    "  42   (LV_BC_7    , PCI_REQn(2)      , bidir        , X    ,   43     , 1     , Z   ),"&
    "  41   (BC_2       , *                , control      , 1   )                          ,"&
    "  40   (LV_BC_7    , PCI_REQn(3)      , bidir        , X    ,   41     , 1     , Z   ),"&
    "  39   (BC_2       , *                , control      , 1   )                          ,"&
    "  38   (LV_BC_7    , PCI_GNTn(0)      , bidir        , X    ,   39     , 1     , Z   ),"&
    "  37   (BC_2       , *                , control      , 1   )                          ,"&
    "  36   (LV_BC_7    , PCI_GNTn(1)      , bidir        , X    ,   37     , 1     , Z   ),"&
    "  35   (BC_2       , *                , control      , 1   )                          ,"&
    "  34   (LV_BC_7    , PCI_GNTn(2)      , bidir        , X    ,   35     , 1     , Z   ),"&
    "  33   (BC_2       , *                , control      , 1   )                          ,"&
    "  32   (LV_BC_7    , PCI_GNTn(3)      , bidir        , X    ,   33     , 1     , Z   ),"&
    "  31   (BC_4       , PCI_CLK          , clock        , X   )                          ,"&
    "  30   (BC_2       , *                , control      , 1   )                          ,"&
    "  29   (LV_BC_7    , PCI_RSTn         , bidir        , X    ,   30     , 1     , Z   ),"&
    "  28   (BC_2       , *                , control      , 1   )                          ,"&
    "  27   (LV_BC_7    , PCI_PMEn         , bidir        , X    ,   28     , 1     , Z   ),"&
    "  26   (BC_2       , *                , control      , 1   )                          ,"&
    "  25   (LV_BC_7    , PCI_INTAn        , bidir        , X    ,   26     , 1     , Z   ),"&
    "  24   (BC_2       , *                , control      , 1   )                          ,"&
    "  23   (LV_BC_7    , PCI_INTBn        , bidir        , X    ,   24     , 1     , Z   ),"&
    "  22   (BC_2       , *                , control      , 1   )                          ,"&
    "  21   (LV_BC_7    , PCI_INTCn        , bidir        , X    ,   22     , 1     , Z   ),"&
    "  20   (BC_2       , *                , control      , 1   )                          ,"&
    "  19   (LV_BC_7    , PCI_INTDn        , bidir        , X    ,   20     , 1     , Z   ),"&
    "  18   (BC_2       , *                , control      , 1   )                          ,"&
    "  17   (LV_BC_7    , PCI_CLKO(4)      , bidir        , X    ,   18     , 1     , Z   ),"&
    "  16   (BC_2       , *                , control      , 1   )                          ,"&
    "  15   (LV_BC_7    , PCI_CLKO(3)      , bidir        , X    ,   16     , 1     , Z   ),"&
    "  14   (BC_2       , *                , control      , 1   )                          ,"&
    "  13   (LV_BC_7    , PCI_CLKO(2)      , bidir        , X    ,   14     , 1     , Z   ),"&
    "  12   (BC_2       , *                , control      , 1   )                          ,"&
    "  11   (LV_BC_7    , PCI_CLKO(1)      , bidir        , X    ,   12     , 1     , Z   ),"&
    "  10   (BC_2       , *                , control      , 1   )                          ,"&
    "  9    (LV_BC_7    , PCI_CLKO(0)      , bidir        , X    ,   10     , 1     , Z   ),"&
    "  8    (BC_2       , *                , control      , 1   )                          ,"&
    "  7    (LV_BC_7    , SR_DIN           , bidir        , X    ,   8      , 1     , Z   ),"&
    "  6    (BC_2       , *                , control      , 1   )                          ,"&
    "  5    (LV_BC_7    , SR_DOUT          , bidir        , X    ,   6      , 1     , Z   ),"&
    "  4    (BC_2       , *                , control      , 1   )                          ,"&
    "  3    (BC_2       , SR_CLK           , output3      , X    ,   4      , 1     , Z   ),"&
    "  2    (BC_2       , *                , control      , 1   )                          ,"&
    "  1    (LV_BC_7    , SR_CSn           , bidir        , X    ,   2      , 1     , Z   ),"&
    "  0    (BC_4       , PCIE_PERSTn      , observe_only , X   )                           ";

    attribute AIO_COMPONENT_CONFORMANCE of peb383: entity is "STD_1149_6_2003";


    attribute AIO_Pin_Behavior of peb383: entity is 
        "PCIE_TXD_p;"&
        "PCIE_RXD_p[141]          : LP_Time=2.30e-07 HP_Time=7.00e-06";
end peb383;
--
-- VHDL package to be uploaded at compile time
--package LVS_BSCAN_CELLS is
--    use STD_1149_1_2001.all;
--        constant LV_BC_7: CELL_INFO;
--
--end LVS_BSCAN_CELLS;
--package body LVS_BSCAN_CELLS is
--    use STD_1149_1_2001.all;
--        constant LV_BC_7: CELL_INFO := 
--           ((BIDIR_IN, EXTEST,  PI),  (BIDIR_OUT, EXTEST,  PO),
--           (BIDIR_IN, SAMPLE,  PI),  (BIDIR_OUT, SAMPLE,  PI),
--           (BIDIR_IN, INTEST,  X),  (BIDIR_OUT, INTEST,  PI));
--
--end LVS_BSCAN_CELLS;
--